URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 118 to Rev 119
- ↔ Reverse comparison
Rev 118 → Rev 119
/trunk/rtl/verilog/eth_defines.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.18 2002/05/03 10:15:50 mohor |
// Outputs registered. Reset changed for eth_wishbone module. |
// |
// Revision 1.17 2002/04/24 08:52:19 mohor |
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision" |
// bug fixed. |
118,15 → 121,13
// |
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//`define EXTERNAL_DMA // Using DMA |
//`define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo |
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// Selection of the used memory |
//`define XILINX_RAMB4 // Core is going to be implemented in Virtex FPGA and contains Virtex |
// Selection of the used memory for Buffer descriptors |
//`define ETH_XILINX_RAMB4 // Core is going to be implemented in Virtex FPGA and contains Virtex |
// specific elements. |
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//`define ARTISAN_SDP // Core is going to be implemented in ASIC (using Artisan RAM) |
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`define ETH_MODER_ADR 8'h0 // 0x0 |
/trunk/rtl/verilog/eth_wishbone.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.29 2002/07/20 00:41:32 mohor |
// ShiftEnded synchronization changed. |
// |
// Revision 1.28 2002/07/18 16:11:46 mohor |
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. |
// |
426,7 → 429,7
assign WB_DAT_O = ram_do; |
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// Generic synchronous single-port RAM interface |
generic_spram #(8, 32) ram ( |
eth_spram_256x32 bd_ram ( |
// Generic synchronous single-port RAM interface |
.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do) |
); |