URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 13 to Rev 14
- ↔ Reverse comparison
Rev 13 → Rev 14
/trunk/rtl/verilog/miim.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// Revision 1.3 2001/06/01 22:28:56 mohor |
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. |
// |
99,7 → 102,7
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output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register |
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register |
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with readed data |
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data |
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parameter Tp = 1; |
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154,7 → 157,7
reg LatchByte0_d; |
reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register |
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reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with readed data |
reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data |
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/trunk/rtl/verilog/ethernettop.v
41,10 → 41,13
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// |
// |
// |
// |
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`timescale 1ns / 1ns |
128,17 → 131,14
wire Mdi; |
wire Mdo; |
wire MdoEn; |
wire Mdc; |
wire Scan_stat; |
wire NValid_stat; |
wire Busy_stat; |
wire Speed_stat; //kam prideta ta dva signala |
wire Duplex_stat; |
wire LinkFail; |
wire r_MiiMRst; |
wire [15:0] Prsd; // Read Status Data (data read from the PHY) |
wire WCtrlDataStart; |
wire RStatStart; |
wire UpdateMIIRX_DATAReg; |
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wire TxStartFrm; |
wire TxEndFrm; |
158,12 → 158,17
.Clk(WB_CLK_I), .Reset(r_MiiMRst), .Divider(r_ClkDiv), |
.NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD), |
.Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat), |
.ScanStat(Scan_stat), .Mdi(Mdi), .Mdo(Mdo), |
.ScanStat(r_ScanStat), .Mdi(Mdi), .Mdo(Mdo), |
.MdoEn(MdoEn), .Mdc(Mdc), .Busy(Busy_stat), |
.Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat), |
.WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg() |
.WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg) |
); |
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assign MDIO = MdoEn & Mdo; |
assign Mdi = ~MdoEn & MDIO; |
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wire RegCs; // Connected to registers |
wire [31:0] RegDataOut; // Multiplexed to WB_DAT_O |
wire r_DmaEn; // DMA enable |
246,8 → 251,7
.r_MiiMRst(r_MiiMRst), .r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv), |
.r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat), |
.r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData), |
.r_Prsd(), .Scan_stat(Scan_stat), .NValid_stat(NValid_stat), |
.Busy_stat(Busy_stat), .Speed_stat(Speed_stat), .Duplex_stat(Duplex_stat), |
.NValid_stat(NValid_stat), .Busy_stat(Busy_stat), |
.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart), |
.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd), |
.r_RxBDAddress(r_RxBDAddress), .RX_BD_ADR_Wr(RX_BD_ADR_Wr) |
/trunk/rtl/verilog/ethregisters.v
41,11 → 41,14
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// |
// |
// |
// |
// |
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`timescale 1ns / 1ns |
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60,8 → 63,8
TxB_MASK, r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet, |
r_CollValid, r_TxFlow, r_RxFlow, r_PassAll, |
r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat, |
r_RGAD, r_FIAD, r_CtrlData, r_Prsd,Scan_stat, NValid_stat, Busy_stat, |
Speed_stat, Duplex_stat, LinkFail, r_MAC, WCtrlDataStart, RStatStart, |
r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat, |
LinkFail, r_MAC, WCtrlDataStart, RStatStart, |
UpdateMIIRX_DATAReg, Prsd, r_RxBDAddress, RX_BD_ADR_Wr |
); |
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144,13 → 147,9
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output [15:0] r_CtrlData; |
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output [15:0] r_Prsd; |
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input Scan_stat; |
input NValid_stat; |
input Busy_stat; |
input Speed_stat; |
input Duplex_stat; |
input LinkFail; |
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output [47:0] r_MAC; |
362,15 → 361,12
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assign r_CtrlData[15:0] = MIITX_DATAOut[15:0]; |
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assign r_Prsd[15:0] = MIIRX_DATAOut[15:0]; |
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assign MIISTATUSOut[31:11] = 21'h0 ; |
assign MIISTATUSOut[10] = Scan_stat ; |
assign MIISTATUSOut[31:10] = 22'h0 ; |
assign MIISTATUSOut[9] = NValid_stat ; |
assign MIISTATUSOut[8] = Busy_stat ; |
assign MIISTATUSOut[7:3]= 5'h0 ; |
assign MIISTATUSOut[2] = Speed_stat ; |
assign MIISTATUSOut[1] = Duplex_stat ; |
assign MIISTATUSOut[2] = 1'b0; |
assign MIISTATUSOut[1] = 1'b0; |
assign MIISTATUSOut[0] = LinkFailRegister ; |
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assign r_MAC[31:0] = MAC_ADDR0Out[31:0]; |