URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 133 to Rev 134
- ↔ Reverse comparison
Rev 133 → Rev 134
/trunk/rtl/verilog/eth_defines.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.19 2002/07/23 15:28:31 mohor |
// Ram , used for BDs changed from generic_spram to eth_spram_256x32. |
// |
// Revision 1.18 2002/05/03 10:15:50 mohor |
// Outputs registered. Reset changed for eth_wishbone module. |
// |
161,7 → 164,7
`define ETH_PACKETLEN_DEF 32'h00400600 |
`define ETH_COLLCONF0_DEF 6'h3f |
`define ETH_COLLCONF1_DEF 4'hF |
`define ETH_TX_BD_NUM_DEF 8'h80 |
`define ETH_TX_BD_NUM_DEF 8'h40 |
`define ETH_CTRLMODER_DEF 3'h0 |
`define ETH_MIIMODER_DEF 11'h064 |
`define ETH_MIIADDRESS0_DEF 5'h00 |
/trunk/rtl/verilog/eth_wishbone.v
41,6 → 41,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.31 2002/07/25 18:29:01 mohor |
// WriteRxDataToMemory signal changed so end of frame (when last word is |
// written to fifo) is changed. |
// |
// Revision 1.30 2002/07/23 15:28:31 mohor |
// Ram , used for BDs changed from generic_spram to eth_spram_256x32. |
// |
1137,7 → 1141,7
|
// Temporary Tx and Rx buffer descriptor address |
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD) |
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum) | // Using first Rx BD |
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum<<1) | // Using first Rx BD |
{8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address) |
|
|
1156,10 → 1160,10
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF; |
RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF<<1; |
else |
if(TX_BD_NUM_Wr) // When r_TxBDNum is updated, RxBDAddress is also |
RxBDAddress <=#Tp WB_DAT_I[7:0]; |
RxBDAddress <=#Tp WB_DAT_I[7:0]<<1; |
else |
if(RxStatusWrite) |
RxBDAddress <=#Tp TempRxBDAddress; |