URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
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- This comparison shows the changes necessary to convert path
/
- from Rev 209 to Rev 210
- ↔ Reverse comparison
Rev 209 → Rev 210
/trunk/rtl/verilog/eth_spram_256x32.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/09/23 18:24:31 mohor |
// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). |
// |
// Revision 1.1 2002/07/23 16:36:09 mohor |
// ethernet spram added. So far a generic ram and xilinx RAMB4 are used. |
// |
53,6 → 56,13
module eth_spram_256x32( |
// Generic synchronous single-port RAM interface |
clk, rst, ce, we, oe, addr, di, do |
|
`ifdef ETH_BIST |
,trst, SO, SI, shift_DR, capture_DR, extest, tck |
`endif |
|
|
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); |
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// |
68,6 → 78,13
output [31:0] do; // output data bus |
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`ifdef ETH_BIST |
input trst; |
input shift_DR, capture_DR, tck, extest; |
input SI; |
output SO; |
`endif |
|
`ifdef ETH_XILINX_RAMB4 |
|
RAMB4_S16 ram0 |
94,17 → 111,35
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`else // !ETH_XILINX_RAMB4 |
`ifdef ETH_VIRTUAL_SILICON_RAM |
vs_hdsp_256x32 ram0 |
( |
.CK (clk), |
.CEN (!ce), |
.WEN (!we), |
.OEN (!oe), |
.ADR (addr), |
.DI (di), |
.DOUT (do) |
); |
`ifdef ETH_BIST |
vs_hdsp_256x32_bist ram0_bist |
`else |
vs_hdsp_256x32 ram0 |
`endif |
( |
.CK (clk), |
.CEN (!ce), |
.WEN (!we), |
.OEN (!oe), |
.ADR (addr), |
.DI (di), |
.DOUT (do) |
|
`ifdef ETH_BIST |
, |
// reset |
.trst (trst), |
|
// debug chain signals |
.SO (SO), |
.SI (SI), |
.shift_DR (shift_DR), |
.capture_DR(capture_DR), |
.extest (extest), |
.tck (tck) |
`endif |
); |
|
`else // !ETH_VIRTUAL_SILICON_RAM |
|
// |
/trunk/rtl/verilog/eth_wishbone.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.37 2002/09/11 14:18:46 mohor |
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. |
// |
// Revision 1.36 2002/09/10 13:48:46 mohor |
// Reception is possible after RxPointer is read and not after BD is read. For |
// that reason RxBDReady is changed to RxReady. |
212,6 → 215,13
// Tx Status |
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost |
|
// Bist |
`ifdef ETH_BIST |
, trst, SO, SI, shift_DR, capture_DR, extest, tck |
`endif |
|
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); |
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295,6 → 305,14
output Busy_IRQ; |
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// Bist |
`ifdef ETH_BIST |
input trst; |
input shift_DR, capture_DR, tck, extest; |
input SI; |
output SO; |
`endif |
|
reg TxB_IRQ; |
reg TxE_IRQ; |
reg RxB_IRQ; |
439,7 → 457,10
|
// Generic synchronous single-port RAM interface |
eth_spram_256x32 bd_ram ( |
.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do) |
.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do) |
`ifdef ETH_BIST |
, .trst(trst), .SO(SO), .SI(SI), .shift_DR(.shift_DR), .capture_DR(capture_DR), .extest(extest), .tck(tck) |
`endif |
); |
|
assign ram_ce = 1'b1; |
/trunk/rtl/verilog/eth_top.v
41,6 → 41,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.32 2002/09/20 17:12:58 mohor |
// CsMiss added. When address between 0x800 and 0xfff is accessed within |
// Ethernet Core, error acknowledge is generated. |
// |
// Revision 1.31 2002/09/12 14:50:17 mohor |
// CarrierSenseLost bug fixed when operating in full duplex mode. |
// |
193,6 → 197,10
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int_o |
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// Bist |
`ifdef ETH_BIST |
, trst, SO, SI, shift_DR, capture_DR, extest, tck |
`endif |
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); |
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251,6 → 259,14
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output int_o; // Interrupt output |
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// Bist |
`ifdef ETH_BIST |
input trst; |
input shift_DR, capture_DR, tck, extest; |
input SI; |
output SO; |
`endif |
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wire [7:0] r_ClkDiv; |
wire r_MiiNoPre; |
wire [15:0] r_CtrlData; |
720,6 → 736,12
.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched), |
.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood) |
|
`ifdef ETH_BIST |
, |
.trst(trst), .SO(SO), .SI(SI), |
.shift_DR(.shift_DR), .capture_DR(capture_DR), .extest(extest), |
.tck(tck) |
`endif |
); |
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