OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 21 to Rev 22
    ↔ Reverse comparison
  •

Rev 21 → Rev 22

/trunk/bench/verilog/tb_eth_top.v
1,4 → 1,4
//////////////////////////////////////////////////////////////////////
///////////3///////////////////////////////////////////////////////////
//// ////
//// tb_eth_top.v ////
//// ////
41,6 → 41,12
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/09/24 14:55:49 mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.2 2001/08/15 14:04:30 mohor
// Signal names changed on the top level for easier pad insertion (ASIC).
//
65,7 → 71,7
 
 
`include "eth_defines.v"
`include "eth_timescale.v"
`include "timescale.v"
 
module tb_eth_top();
 
139,7 → 145,9
.mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
// MIIM
.mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoen_o(Mdo_OE)
.mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoen_o(Mdo_OE),
.int_o()
);
 
 
220,11 → 228,11
begin
wait(StartTB); // Start of testbench
WishboneWrite(32'h00000800, {`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_MODER_ADR<<2}); // r_Rst = 1
WishboneWrite(32'h00000000, {`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_MODER_ADR<<2}); // r_Rst = 0
WishboneWrite(32'h00000080, {`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_RX_BD_ADR_ADR<<2});// r_RxBDAddress = 0x80
WishboneWrite(32'h0002A443, {`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_MODER_ADR<<2}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
WishboneWrite(32'h00000004, {`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_CTRLMODER_ADR<<2});//r_TxFlow = 1
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 1
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 0
WishboneWrite(32'h00000080, {26'h0, `ETH_RX_BD_ADR_ADR<<2}); // r_RxBDAddress = 0x80
WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR<<2}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
 
 
 
243,19 → 251,19
ReceivePacket(16'h0018, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
 
WishboneRead({`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_MODER_ADR<<2}); // Read from MODER register
WishboneRead({26'h0, `ETH_MODER_ADR}); // Read from MODER register
 
WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h0<<2)}); // Read from TxBD register
WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h1<<2)}); // Read from TxBD register
WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h2<<2)}); // Read from TxBD register
WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h3<<2)}); // Read from TxBD register
WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h4<<2)}); // Read from TxBD register
WishboneRead({24'h100, (8'h0<<2)}); // Read from TxBD register
WishboneRead({24'h100, (8'h1<<2)}); // Read from TxBD register
WishboneRead({24'h100, (8'h2<<2)}); // Read from TxBD register
WishboneRead({24'h100, (8'h3<<2)}); // Read from TxBD register
WishboneRead({24'h100, (8'h4<<2)}); // Read from TxBD register
WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h80<<2)}); // Read from RxBD register
WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h81<<2)}); // Read from RxBD register
WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h82<<2)}); // Read from RxBD register
WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h83<<2)}); // Read from RxBD register
WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h84<<2)}); // Read from RxBD register
WishboneRead({22'h40, (10'h80<<2)}); // Read from RxBD register
WishboneRead({22'h40, (10'h81<<2)}); // Read from RxBD register
WishboneRead({22'h40, (10'h82<<2)}); // Read from RxBD register
WishboneRead({22'h40, (10'h83<<2)}); // Read from RxBD register
WishboneRead({22'h40, (10'h84<<2)}); // Read from RxBD register
 
#10000 $stop;
end
299,23 → 307,20
 
// Writing information about the access to the screen
@ (posedge WB_CLK_I);
if(Address[31:16] == `ETH_ETHERNET_SPACE)
if(Address[15:12] == `ETH_REG_SPACE)
$write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address[9:2]);
if(~Address[17] & ~Address[16])
$write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
else
if(Address[15:12] == `ETH_BD_SPACE)
if(~Address[17] & Address[16])
if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
begin
$write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address[9:2]);
$write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address);
if(Data[13])
$write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);
end
else
$write("\nWrite to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address[9:2]);
$write("\nWrite to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
else
$write("\nWB write Data: 0x%x Addr: 0x%0x", Data, Address);
else
$write("\nWARNING !!! WB write to non-ethernet space (Data: 0x%x, Addr: 0x%0x)", Data, Address);
$write("\nWB write ?????????????? Data: 0x%x Addr: 0x%0x", Data, Address);
#1;
WB_ADR_I = 32'hx;
WB_DAT_I = 32'hx;
358,21 → 363,18
end
 
@ (posedge WB_CLK_I);
if(Address[31:16] == `ETH_ETHERNET_SPACE)
if(Address[15:12] == `ETH_REG_SPACE)
$write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address[9:2]);
if(~Address[17] & ~Address[16])
$write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
else
if(Address[15:12] == `ETH_BD_SPACE)
if(~Address[17] & Address[16])
if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
begin
$write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address[9:2]);
$write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address);
end
else
$write("\nRead from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address[9:2]);
$write("\nRead from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
else
$write("\nWB read Data: 0x%x Addr: 0x%0x", Data, Address);
else
$write("\nWARNING !!! WB read to non-ethernet space (Data: 0x%x, Addr: 0x%0x)", Data, Address);
$write("\nWB read ????????? Data: 0x%x Addr: 0x%0x", Data, Address);
#1;
WB_ADR_I = 32'hx;
WB_WE_I = 1'bx;
399,8 → 401,8
else
Wrap = 1'b0;
 
TempAddr = {`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (TxBDIndex<<2)};
TempData = {Length[15:0], 1'b1, Wrap, ControlFrame, 5'h0, TxBDIndex[7:0]}; // Ready and Wrap = 1
TempAddr = {22'h40, (TxBDIndex<<2)};
TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]}; // Ready and Wrap = 1
 
#1;
if(TxBDIndex == 3) // Only 4 buffer descriptors are used
436,9 → 438,9
else
WrapRx = 1'b0;
 
TempRxAddr = {`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, ((tb_eth_top.ethtop.r_RxBDAddress + RxBDIndex)<<2)};
TempRxAddr = {22'h40, ((tb_eth_top.ethtop.r_RxBDAddress + RxBDIndex)<<2)};
 
TempRxData = {LengthRx[15:0], 1'b1, WrapRx, 6'h0, RxBDIndex[7:0]}; // Ready and WrapRx = 1 or 0
TempRxData = {LengthRx[15:0], 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]}; // Ready and WrapRx = 1 or 0
 
#1;
if(RxBDIndex == 3) // Only 4 buffer descriptors are used
489,7 → 491,7
WishboneBusy = 1;
#1;
WB_DAT_I = {a, b, c, d};
WB_ADR_I = {`ETH_ETHERNET_SPACE, `ETH_TX_DATA, pp[11:0]};
WB_ADR_I = {20'h20, pp[11:0]};
$display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
 
WB_WE_I = 1'b1;
525,7 → 527,7
wait (~WishboneBusy);
WishboneBusy = 1;
#1;
WB_ADR_I = {`ETH_ETHERNET_SPACE, `ETH_RX_DATA, rr[11:0]};
WB_ADR_I = {20'h20, rr[11:0]};
$display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
 
WB_WE_I = 1'b1;
/trunk/rtl/verilog/eth_timescale.v File deleted
/trunk/rtl/verilog/eth_rxethmac.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
64,7 → 67,7
//
//
 
`include "eth_timescale.v"
`include "timescale.v"
 
 
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
/trunk/rtl/verilog/eth_shiftreg.v
41,6 → 41,16
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
49,7 → 59,7
//
//
 
`include "eth_timescale.v"
`include "timescale.v"
 
 
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
/trunk/rtl/verilog/eth_rxcounters.v
43,6 → 43,16
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
56,7 → 66,7
//
 
 
`include "eth_timescale.v"
`include "timescale.v"
 
 
module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
/trunk/rtl/verilog/eth_txethmac.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
69,7 → 72,7
//
//
 
`include "eth_timescale.v"
`include "timescale.v"
 
 
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
/trunk/rtl/verilog/eth_txcounters.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
69,7 → 72,7
//
 
 
`include "eth_timescale.v"
`include "timescale.v"
 
 
module eth_txcounters (StatePreamble, StateIPG, StateData, StatePAD, StateFCS, StateJam,
/trunk/rtl/verilog/eth_random.v
43,6 → 43,16
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
60,7 → 70,7
//
//
 
`include "eth_timescale.v"
`include "timescale.v"
 
module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
RandomEq0, RandomEqByteCnt);
/trunk/rtl/verilog/eth_receivecontrol.v
41,6 → 41,16
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
53,7 → 63,7
//
 
 
`include "eth_timescale.v"
`include "timescale.v"
 
 
module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
/trunk/rtl/verilog/eth_register.v
41,6 → 41,15
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
//
//
47,8 → 56,9
//
//
//
//
 
`include "eth_timescale.v"
`include "timescale.v"
 
 
module eth_register(DataIn, DataOut, Write, Clk, Reset, Default);
/trunk/rtl/verilog/eth_clockgen.v
41,6 → 41,16
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
49,7 → 59,7
//
//
 
`include "eth_timescale.v"
`include "timescale.v"
 
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
 
/trunk/rtl/verilog/eth_miim.v
41,6 → 41,16
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.2 2001/08/02 09:25:31 mohor
// Unconnected signals are now connected.
//
52,7 → 62,7
//
//
 
`include "eth_timescale.v"
`include "timescale.v"
 
 
module eth_miim
/trunk/rtl/verilog/eth_wishbonedma.v
41,6 → 41,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2001/10/18 12:07:11 mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.3 2001/09/24 15:02:56 mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
70,7 → 74,7
 
 
`include "eth_defines.v"
`include "eth_timescale.v"
`include "timescale.v"
 
 
module eth_wishbonedma
/trunk/rtl/verilog/eth_maccontrol.v
41,6 → 41,16
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
52,7 → 62,7
//
 
 
`include "eth_timescale.v"
`include "timescale.v"
 
 
module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn,
/trunk/rtl/verilog/eth_outputcontrol.v
41,6 → 41,16
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
49,7 → 59,7
//
//
 
`include "eth_timescale.v"
`include "timescale.v"
 
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
 
/trunk/rtl/verilog/eth_sync_clk1_clk2.v
41,12 → 41,18
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/09/24 15:02:56 mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
//
//
//
//
 
`include "eth_timescale.v"
`include "timescale.v"
 
// FF in clock domain 1 is being set by a signal from the clock domain 2
module eth_sync_clk1_clk2 (clk1, clk2, reset1, reset2, set2, sync_out);
/trunk/rtl/verilog/eth_top.v
41,6 → 41,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2001/10/18 12:07:11 mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.3 2001/09/24 15:02:56 mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
72,7 → 76,7
 
 
`include "eth_defines.v"
`include "eth_timescale.v"
`include "timescale.v"
 
 
module eth_top
/trunk/rtl/verilog/eth_transmitcontrol.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
64,7 → 67,7
//
 
 
`include "eth_timescale.v"
`include "timescale.v"
 
 
module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
/trunk/rtl/verilog/eth_macstatus.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
59,7 → 62,7
//
//
 
`include "eth_timescale.v"
`include "timescale.v"
 
 
module eth_macstatus(
/trunk/rtl/verilog/timescale.v
0,0 → 1,7
`timescale 1ns / 1ns
/trunk/rtl/verilog/eth_rxstatem.v
43,6 → 43,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/10/18 12:07:11 mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
71,7 → 75,7
//
 
 
`include "eth_timescale.v"
`include "timescale.v"
 
 
module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,
/trunk/rtl/verilog/eth_registers.v
41,6 → 41,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/10/18 12:07:11 mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.2 2001/09/24 15:02:56 mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
70,7 → 74,7
//
 
`include "eth_defines.v"
`include "eth_timescale.v"
`include "timescale.v"
 
 
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut, r_DmaEn,
/trunk/rtl/verilog/eth_crc.v
43,6 → 43,16
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
60,7 → 70,7
//
 
 
`include "eth_timescale.v"
`include "timescale.v"
 
module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
 
/trunk/rtl/verilog/eth_txstatem.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
71,7 → 74,7
//
 
 
`include "eth_timescale.v"
`include "timescale.v"
 
 
module eth_txstatem (MTxClk, Reset, ExcessiveDefer, CarrierSense, NibCnt, IPGT, IPGR1,

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.