URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
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- This comparison shows the changes necessary to convert path
/
- from Rev 252 to Rev 253
- ↔ Reverse comparison
Rev 252 → Rev 253
/trunk/rtl/verilog/eth_defines.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.28 2002/11/15 14:27:15 mohor |
// Since r_Rst bit is not used any more, default value is changed to 0xa000. |
// |
// Revision 1.27 2002/11/01 18:19:34 mohor |
// Defines fixed to use generic RAM by default. |
// |
224,7 → 227,7
`define ETH_PACKETLEN_WIDTH 32 |
`define ETH_TX_BD_NUM_WIDTH 8 |
`define ETH_CTRLMODER_WIDTH 3 |
`define ETH_MIIMODER_WIDTH 10 |
`define ETH_MIIMODER_WIDTH 9 |
`define ETH_MIITX_DATA_WIDTH 16 |
`define ETH_MIIRX_DATA_WIDTH 16 |
`define ETH_MIISTATUS_WIDTH 3 |
/trunk/rtl/verilog/eth_top.v
41,6 → 41,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.40 2002/11/19 17:34:25 mohor |
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying |
// that a frame was received because of the promiscous mode. |
// |
// Revision 1.39 2002/11/18 17:31:55 mohor |
// wb_rst_i is used for MIIM reset. |
// |
314,7 → 318,6
wire NValid_stat; |
wire Busy_stat; |
wire LinkFail; |
wire r_MiiMRst; |
wire [15:0] Prsd; // Read Status Data (data read from the PHY) |
wire WCtrlDataStart; |
wire RStatStart; |
469,7 → 472,7
.r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL), |
.r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid), |
.r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll), |
.r_MiiMRst(r_MiiMRst), .r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv), |
.r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv), |
.r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat), |
.r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData), |
.NValid_stat(NValid_stat), .Busy_stat(Busy_stat), |
/trunk/rtl/verilog/eth_registers.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.22 2002/11/14 18:37:20 mohor |
// r_Rst signal does not reset any module any more and is removed from the design. |
// |
// Revision 1.21 2002/09/10 10:35:23 mohor |
// Ethernet debug registers removed. |
// |
145,7 → 148,7
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, |
r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet, |
r_CollValid, r_TxFlow, r_RxFlow, r_PassAll, |
r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat, |
r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat, |
r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat, |
LinkFail, r_MAC, WCtrlDataStart, RStatStart, |
UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o, |
213,7 → 216,6
output r_RxFlow; |
output r_PassAll; |
|
output r_MiiMRst; |
output r_MiiNoPre; |
output [7:0] r_ClkDiv; |
|
682,7 → 684,6
assign r_RxFlow = CTRLMODEROut[1]; |
assign r_PassAll = CTRLMODEROut[0]; |
|
assign r_MiiMRst = MIIMODEROut[9]; |
assign r_MiiNoPre = MIIMODEROut[8]; |
assign r_ClkDiv[7:0] = MIIMODEROut[7:0]; |
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