URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 300 to Rev 301
- ↔ Reverse comparison
Rev 300 → Rev 301
/trunk/rtl/verilog/eth_top.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.46 2003/01/30 13:30:22 tadejm |
// Defer indication changed. |
// |
// Revision 1.45 2003/01/22 13:49:26 tadejm |
// When control packets were received, they were ignored in some cases. |
// |
571,8 → 574,8
reg Collision_Tx2; |
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reg RxEnSync; // Synchronized Receive Enable |
reg CarrierSense_Rx1; |
reg RxCarrierSense; // Synchronized CarrierSense (to Rx clock) |
//reg CarrierSense_Rx1; |
//reg RxCarrierSense; // Synchronized CarrierSense (to Rx clock) |
reg WillTransmit_q; |
reg WillTransmit_q2; |
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684,19 → 687,19
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// Carrier sense is synchronized to receive clock. |
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
begin |
CarrierSense_Rx1 <= #Tp 1'h0; |
RxCarrierSense <= #Tp 1'h0; |
end |
else |
begin |
CarrierSense_Rx1 <= #Tp mcrs_pad_i; |
RxCarrierSense <= #Tp CarrierSense_Rx1; |
end |
end |
//always @ (posedge mrx_clk_pad_i or posedge wb_rst_i) |
//begin |
// if(wb_rst_i) |
// begin |
// CarrierSense_Rx1 <= #Tp 1'h0; |
// RxCarrierSense <= #Tp 1'h0; |
// end |
// else |
// begin |
// CarrierSense_Rx1 <= #Tp mcrs_pad_i; |
// RxCarrierSense <= #Tp CarrierSense_Rx1; |
// end |
//end |
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// Delayed WillTransmit |
717,7 → 720,8
if(wb_rst_i) |
RxEnSync <= #Tp 1'b0; |
else |
if(~RxCarrierSense | RxCarrierSense & Transmitting) |
//if(~RxCarrierSense | RxCarrierSense & Transmitting) |
if(~mrxdv_pad_i) |
RxEnSync <= #Tp r_RxEn; |
end |
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