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URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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    from Rev 314 to Rev 315
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Rev 314 → Rev 315

/trunk/bench/verilog/tb_ethernet.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.30 2003/10/17 07:45:17 markom
// mbist signals updated according to newest convention
//
// Revision 1.29 2003/08/20 12:06:24 mohor
// Artisan RAMs added.
//
180,9 → 183,10
wire [3:0] eth_ma_wb_sel_o;
wire eth_ma_wb_we_o, eth_ma_wb_cyc_o, eth_ma_wb_stb_o, eth_ma_wb_ack_i, eth_ma_wb_err_i;
 
wire [2:0] eth_ma_wb_cti_o;
wire [1:0] eth_ma_wb_bte_o;
 
 
 
// Connecting Ethernet top module
eth_top eth_top
(
199,6 → 203,10
.m_wb_dat_i(eth_ma_wb_dat_i), .m_wb_dat_o(eth_ma_wb_dat_o), .m_wb_cyc_o(eth_ma_wb_cyc_o),
.m_wb_stb_o(eth_ma_wb_stb_o), .m_wb_ack_i(eth_ma_wb_ack_i), .m_wb_err_i(eth_ma_wb_err_i),
 
`ifdef ETH_WISHBONE_B3
.m_wb_cti_o(eth_ma_wb_cti_o), .m_wb_bte_o(eth_ma_wb_bte_o),
`endif
 
//TX
.mtx_clk_pad_i(mtx_clk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
 
291,7 → 299,7
.SEL_I(eth_ma_wb_sel_o),
.STB_I(eth_ma_wb_stb_o),
.WE_I (eth_ma_wb_we_o),
.CAB_I(1'b0) // inactive (1'b0)
.CAB_I(1'b0)
);
 
 
318,8 → 326,17
.STB_O(eth_sl_wb_stb_i),
.WE_O (eth_sl_wb_we_i),
.TAG_I({`WB_TAG_WIDTH{1'b0}}),
.TAG_O(),
`ifdef ETH_WISHBONE_B3
.TAG_O({eth_ma_wb_cti_o, eth_ma_wb_bte_o}),
`else
.TAG_O(5'h0),
`endif
.CAB_O(1'b0),
`ifdef ETH_WISHBONE_B3
.check_CTI (1'b1),
`else
.check_CTI (1'b0),
`endif
.log_file_desc (wb_s_mon_log_file_desc)
);
 
341,8 → 358,9
.STB_O(eth_ma_wb_stb_o),
.WE_O (eth_ma_wb_we_o),
.TAG_I({`WB_TAG_WIDTH{1'b0}}),
.TAG_O(),
.TAG_O(5'h0),
.CAB_O(1'b0),
.check_CTI(1'b0), // NO need
.log_file_desc(wb_m_mon_log_file_desc)
);
 
475,13 → 493,15
 
// Call tests
// ----------
// test_access_to_mac_reg(0, 0); // 0 - 3
// test_mii(0, 17); // 0 - 17
test_access_to_mac_reg(0, 4); // 0 - 4
test_mii(0, 17); // 0 - 17
test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
eth_phy.carrier_sense_real_delay(0);
test_mac_full_duplex_transmit(0, 21); // 0 - (21)
test_mac_full_duplex_receive(0, 13); // 0 - 13
test_mac_full_duplex_flow_control(0, 4); // 0 - 4
// test_mac_full_duplex_transmit(0, 21); // 0 - (21)
 
 
// test_mac_full_duplex_receive(2, 2); // 0 - 13
// test_mac_full_duplex_flow_control(0, 4); // 0 - 4
// 4 is executed, everything is OK
// test_mac_half_duplex_flow(0, 0);
 
527,6 → 547,8
integer test_num;
reg [31:0] addr;
reg [31:0] data;
reg [3:0] sel;
reg [3:0] rand_sel;
reg [31:0] data_max;
begin
// ACCESS TO MAC REGISTERS TEST
537,9 → 559,6
 
// reset MAC registers
hard_reset;
// reset MAC and MII LOGIC with soft reset
//reset_mac;
//reset_mii;
 
 
//////////////////////////////////////////////////////////////////////
546,11 → 565,12
//// ////
//// test_access_to_mac_reg: ////
//// ////
//// 0: Walking 1 with single cycles across MAC regs. ////
//// 1: Walking 1 with single cycles across MAC buffer descript. ////
//// 2: Test max reg. values and reg. values after writing ////
//// 0: Byte selects on 3 32-bit RW registers. ////
//// 1: Walking 1 with single cycles across MAC regs. ////
//// 2: Walking 1 with single cycles across MAC buffer descript. ////
//// 3: Test max reg. values and reg. values after writing ////
//// inverse reset values and hard reset of the MAC ////
//// 3: Test buffer desc. RAM preserving values after hard reset ////
//// 4: Test buffer desc. RAM preserving values after hard reset ////
//// of the MAC and resetting the logic ////
//// ////
//////////////////////////////////////////////////////////////////////
559,206 → 579,313
 
////////////////////////////////////////////////////////////////////
//// ////
//// Walking 1 with single cycles across MAC regs. ////
//// Byte selects on 4 32-bit RW registers. ////
//// ////
////////////////////////////////////////////////////////////////////
if (test_num == 0) // Walking 1 with single cycles across MAC regs.
begin
// TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
test_name = "TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
`TIME; $display(" TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
// TEST 0: BYTE SELECTS ON 3 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )
test_name = "TEST 0: BYTE SELECTS ON 3 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )";
`TIME; $display(" TEST 0: BYTE SELECTS ON 3 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )");
data = 0;
for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
rand_sel = 0;
sel = 0;
for (i = 1; i <= 3; i = i + 1) // num of active byte selects at each register
begin
wbm_init_waits = 0;
wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
case (i)
1: i_addr = `ETH_MAC_ADDR0;
2: i_addr = `ETH_HASH_ADDR0;
default: i_addr = `ETH_HASH_ADDR1;
endcase
addr = `ETH_BASE + i_addr;
sel = 4'hF;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data !== 32'h0)
begin
wbm_init_waits = i;
wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
for (i_addr = 0; i_addr <= 32'h4C; i_addr = i_addr + 4) // register address
fail = fail + 1;
test_fail_num("Register default value is not ZERO", i_addr);
`TIME;
$display("Register default value is not ZERO - addr %h, tmp_data %h", addr, tmp_data);
end
for (i1 = 0; i1 <= 3; i1 = i1 + 1) // position of first active byte select
begin
case ({i, i1})
10: sel = 4'b0001; // data = 32'hFFFF_FF00;
11: sel = 4'b0010; // data = 32'hFFFF_00FF;
12: sel = 4'b0100; // data = 32'hFF00_FFFF;
13: sel = 4'b1000; // data = 32'h00FF_FFFF;
20: sel = 4'b0011; // data = 32'hFFFF_0000;
21: sel = 4'b0110; // data = 32'hFF00_00FF;
22: sel = 4'b1100; // data = 32'h0000_FFFF;
23: sel = 4'b1001; // data = 32'h00FF_FF00;
30: sel = 4'b0111; // data = 32'hFF00_0000;
31: sel = 4'b1110; // data = 32'h0000_00FF;
32: sel = 4'b1101; // data = 32'h0000_FF00;
default: sel = 4'b1011; // data = 32'h00FF_0000;
endcase
// set value to 32'hFFFF_FFFF
data = 32'hFFFF_FFFF;
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
wait (wbm_working == 0);
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data !== data)
begin
fail = fail + 1;
test_fail_num("Register could not be written to FFFF_FFFF", i_addr);
`TIME;
$display("Register could not be written to FFFF_FFFF - addr %h, tmp_data %h", addr, tmp_data);
end
// write appropriate byte(s) to 0
data = 32'h0;
wbm_write(addr, data, sel, 1, wbm_init_waits, wbm_subseq_waits);
wait (wbm_working == 0);
if (i1[0])
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
else
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
data = {({8{~sel[3]}}), ({8{~sel[2]}}), ({8{~sel[1]}}), ({8{~sel[0]}})};
if (tmp_data !== data)
begin
fail = fail + 1;
test_fail_num("Wrong data read out form register", i_addr);
`TIME;
$display("Wrong data read out from register - addr %h, data %h, tmp_data %h, sel %b",
addr, data, tmp_data, sel);
end
end
end
if(fail == 0)
test_ok;
else
fail = 0; // Errors were reported previously
end
 
 
////////////////////////////////////////////////////////////////////
//// ////
//// Walking 1 with single cycles across MAC regs. ////
//// ////
////////////////////////////////////////////////////////////////////
if (test_num == 1) // Walking 1 with single cycles across MAC regs.
begin
// TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
test_name = "TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
`TIME; $display(" TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
data = 0;
rand_sel = 0;
sel = 0;
for (i_addr = 0; i_addr <= {22'h0, `ETH_TX_CTRL_ADR, 2'h0}; i_addr = i_addr + 4) // register address
begin
if (i_addr[6:4] < 5)
wbm_init_waits = i_addr[6:4];
else
wbm_init_waits = 4;
wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
addr = `ETH_BASE + i_addr;
// set ranges of R/W bits
case (addr)
`ETH_MODER:
begin
bit_start_1 = 0;
bit_end_1 = 16;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_INT: // READONLY - tested within INT test
begin
bit_start_1 = 32; // not used
bit_end_1 = 32; // not used
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_INT_MASK:
begin
bit_start_1 = 0;
bit_end_1 = 6;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_IPGT:
begin
bit_start_1 = 0;
bit_end_1 = 6;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_IPGR1:
begin
bit_start_1 = 0;
bit_end_1 = 6;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_IPGR2:
begin
bit_start_1 = 0;
bit_end_1 = 6;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_PACKETLEN:
begin
bit_start_1 = 0;
bit_end_1 = 31;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_COLLCONF:
begin
bit_start_1 = 0;
bit_end_1 = 5;
bit_start_2 = 16;
bit_end_2 = 19;
end
`ETH_TX_BD_NUM:
begin
bit_start_1 = 0;
bit_end_1 = 7;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_CTRLMODER:
begin
bit_start_1 = 0;
bit_end_1 = 2;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MIIMODER:
begin
bit_start_1 = 0;
bit_end_1 = 8;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
begin
bit_start_1 = 32; // not used
bit_end_1 = 32; // not used
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MIIADDRESS:
begin
bit_start_1 = 0;
bit_end_1 = 4;
bit_start_2 = 8;
bit_end_2 = 12;
end
`ETH_MIITX_DATA:
begin
bit_start_1 = 0;
bit_end_1 = 15;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MIIRX_DATA: // READONLY - tested within MIIM test
begin
bit_start_1 = 32; // not used
bit_end_1 = 32; // not used
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MIISTATUS: // READONLY - tested within MIIM test
begin
bit_start_1 = 32; // not used
bit_end_1 = 32; // not used
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MAC_ADDR0:
begin
bit_start_1 = 0;
bit_end_1 = 31;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MAC_ADDR1:
begin
bit_start_1 = 0;
bit_end_1 = 15;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_HASH_ADDR0:
begin
bit_start_1 = 0;
bit_end_1 = 31;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_HASH_ADDR1:
begin
bit_start_1 = 0;
bit_end_1 = 31;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
default: // `ETH_TX_CTRL_ADR:
begin
bit_start_1 = 0;
bit_end_1 = 16;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
endcase
for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
begin
data = 1'b1 << i_data;
if ( (addr == `ETH_MIICOMMAND)/* && (i_data <= 2)*/ ) // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
;
else
begin
rand_sel[2:0] = {$random} % 8;
if ((i_data >= 0) && (i_data < 8))
sel = {rand_sel[2:0], 1'b1};
else if ((i_data >= 8) && (i_data < 16))
sel = {rand_sel[2:1], 1'b1, rand_sel[0]};
else if ((i_data >= 16) && (i_data < 24))
sel = {rand_sel[2], 1'b1, rand_sel[1:0]};
else // if ((i_data >= 24) && (i_data < 32))
sel = {1'b1, rand_sel[2:0]};
wbm_write(addr, data, sel, 1, wbm_init_waits, wbm_subseq_waits);
wait (wbm_working == 0);
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
begin
addr = `ETH_BASE + i_addr;
// set ranges of R/W bits
case (addr)
`ETH_MODER:
begin
bit_start_1 = 0;
bit_end_1 = 16;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_INT: // READONLY - tested within INT test
begin
bit_start_1 = 32; // not used
bit_end_1 = 32; // not used
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_INT_MASK:
begin
bit_start_1 = 0;
bit_end_1 = 6;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_IPGT:
begin
bit_start_1 = 0;
bit_end_1 = 6;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_IPGR1:
begin
bit_start_1 = 0;
bit_end_1 = 6;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_IPGR2:
begin
bit_start_1 = 0;
bit_end_1 = 6;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_PACKETLEN:
begin
bit_start_1 = 0;
bit_end_1 = 31;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_COLLCONF:
begin
bit_start_1 = 0;
bit_end_1 = 5;
bit_start_2 = 16;
bit_end_2 = 19;
end
`ETH_TX_BD_NUM:
begin
bit_start_1 = 0;
bit_end_1 = 7;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_CTRLMODER:
begin
bit_start_1 = 0;
bit_end_1 = 2;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MIIMODER:
begin
bit_start_1 = 0;
bit_end_1 = 9;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
begin
bit_start_1 = 32; // not used
bit_end_1 = 32; // not used
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MIIADDRESS:
begin
bit_start_1 = 0;
bit_end_1 = 4;
bit_start_2 = 8;
bit_end_2 = 12;
end
`ETH_MIITX_DATA:
begin
bit_start_1 = 0;
bit_end_1 = 15;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MIIRX_DATA: // READONLY - tested within MIIM test
begin
bit_start_1 = 32; // not used
bit_end_1 = 32; // not used
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MIISTATUS: // READONLY - tested within MIIM test
begin
bit_start_1 = 32; // not used
bit_end_1 = 32; // not used
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MAC_ADDR0:
begin
bit_start_1 = 0;
bit_end_1 = 31;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MAC_ADDR1:
begin
bit_start_1 = 0;
bit_end_1 = 15;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_HASH_ADDR0:
begin
bit_start_1 = 0;
bit_end_1 = 31;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
default: // `ETH_HASH_ADDR1:
begin
bit_start_1 = 0;
bit_end_1 = 31;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
endcase
for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
begin
data = 1'b1 << i_data;
if ( (addr == `ETH_MIICOMMAND) && (i_data <= 2) ) // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
;
else
begin
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
wait (wbm_working == 0);
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
begin
if (tmp_data !== data)
begin
fail = fail + 1;
test_fail("RW bit of the MAC register was not written or not read");
`TIME;
$display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
wbm_init_waits, addr, data, tmp_data);
end
end
else // data should not be equal to tmp_data
begin
if (tmp_data === data)
begin
fail = fail + 1;
test_fail("NON RW bit of the MAC register was written, but it shouldn't be");
`TIME;
$display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
wbm_init_waits, addr, data, tmp_data);
end
end
end
end
if ( ((tmp_data[31:24] !== data[31:24]) && sel[3]) || ((tmp_data[23:16] !== data[23:16]) && sel[2]) ||
((tmp_data[15: 8] !== data[15: 8]) && sel[1]) || ((tmp_data[ 7: 0] !== data[ 7: 0]) && sel[0]) )
begin
fail = fail + 1;
test_fail_num("RW bit of the MAC register was not written or not read", i_addr);
`TIME;
$display("Wrong RW bit - wbm_init_waits %d, addr %h, data %h, tmp_data %h, sel %b",
wbm_init_waits, addr, data, tmp_data, sel);
end
end
else // data should not be equal to tmp_data
begin
if ( ((tmp_data[31:24] === data[31:24]) && sel[3]) && ((tmp_data[23:16] === data[23:16]) && sel[2]) &&
((tmp_data[15: 8] === data[15: 8]) && sel[1]) && ((tmp_data[ 7: 0] === data[ 7: 0]) && sel[0]) )
begin
fail = fail + 1;
test_fail_num("NON RW bit of the MAC register was written, but it shouldn't be", i_addr);
`TIME;
$display("Wrong NON RW bit - wbm_init_waits %d, addr %h, data %h, tmp_data %h, sel %b",
wbm_init_waits, addr, data, tmp_data, sel);
end
end
end
end
end
// INTERMEDIATE DISPLAYS (The only one)
$display(" ->buffer descriptors tested with 0, 1, 2, 3 and 4 bus delay cycles");
$display(" ->registers tested with 0, 1, 2, 3 and 4 bus delay cycles");
if(fail == 0)
test_ok;
else
771,108 → 898,121
//// Walking 1 with single cycles across MAC buffer descript. ////
//// ////
////////////////////////////////////////////////////////////////////
if (test_num == 1) // Start Walking 1 with single cycles across MAC buffer descript.
if (test_num == 2) // Start Walking 1 with single cycles across MAC buffer descript.
begin
// TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
test_name = "TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )";
`TIME; $display(" TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )");
// TEST 2: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
test_name = "TEST 2: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )";
`TIME; $display(" TEST 2: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )");
data = 0;
rand_sel = 0;
sel = 0;
// set TX and RX buffer descriptors
tx_bd_num = 32'h40;
wbm_write(`ETH_TX_BD_NUM, tx_bd_num, 4'hF, 1, 0, 0);
for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
begin
wbm_init_waits = i;
if (i_addr[11:8] < 8)
wbm_init_waits = i_addr[10:8] - 3'h4;
else
wbm_init_waits = 3;
wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
addr = `ETH_BASE + i_addr;
if (i_addr < (32'h400 + (tx_bd_num << 3))) // TX buffer descriptors
begin
addr = `ETH_BASE + i_addr;
if (i_addr < (32'h400 + (tx_bd_num << 3))) // TX buffer descriptors
// set ranges of R/W bits
case (addr[3])
1'b0: // buffer control bits
begin
bit_start_1 = 0;
bit_end_1 = 31; // 8;
bit_start_2 = 11;
bit_end_2 = 31;
end
default: // 1'b1: // buffer pointer
begin
bit_start_1 = 0;
bit_end_1 = 31;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
endcase
end
else // RX buffer descriptors
begin
// set ranges of R/W bits
case (addr[3])
1'b0: // buffer control bits
begin
bit_start_1 = 0;
bit_end_1 = 31; // 7;
bit_start_2 = 13;
bit_end_2 = 31;
end
default: // 1'b1: // buffer pointer
begin
bit_start_1 = 0;
bit_end_1 = 31;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
endcase
end
for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
begin
data = 1'b1 << i_data;
if ( (addr[3] == 0) && (i_data == 15) ) // DO NOT WRITE to this bit !!!
;
else
begin
// set ranges of R/W bits
case (addr[3])
1'b0: // buffer control bits
rand_sel[2:0] = {$random} % 8;
if ((i_data >= 0) && (i_data < 8))
sel = {rand_sel[2:0], 1'b1};
else if ((i_data >= 8) && (i_data < 16))
sel = {rand_sel[2:1], 1'b1, rand_sel[0]};
else if ((i_data >= 16) && (i_data < 24))
sel = {rand_sel[2], 1'b1, rand_sel[1:0]};
else // if ((i_data >= 24) && (i_data < 32))
sel = {1'b1, rand_sel[2:0]};
wbm_write(addr, data, sel, 1, wbm_init_waits, wbm_subseq_waits);
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
begin
if ( ((tmp_data[31:24] !== data[31:24]) && sel[3]) || ((tmp_data[23:16] !== data[23:16]) && sel[2]) ||
((tmp_data[15: 8] !== data[15: 8]) && sel[1]) || ((tmp_data[ 7: 0] !== data[ 7: 0]) && sel[0]) )
begin
bit_start_1 = 0;
bit_end_1 = 31; // 8;
bit_start_2 = 11;
bit_end_2 = 31;
fail = fail + 1;
test_fail("RW bit of the MAC buffer descriptors was not written or not read");
`TIME;
$display("Wrong RW bit - wbm_init_waits %d, addr %h, data %h, tmp_data %h, sel %b",
wbm_init_waits, addr, data, tmp_data, sel);
end
default: // 1'b1: // buffer pointer
begin
bit_start_1 = 0;
bit_end_1 = 31;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
endcase
end
else // RX buffer descriptors
begin
// set ranges of R/W bits
case (addr[3])
1'b0: // buffer control bits
begin
bit_start_1 = 0;
bit_end_1 = 31; // 7;
bit_start_2 = 13;
bit_end_2 = 31;
end
default: // 1'b1: // buffer pointer
begin
bit_start_1 = 0;
bit_end_1 = 31;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
endcase
end
for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
begin
data = 1'b1 << i_data;
if ( (addr[3] == 0) && (i_data == 15) ) // DO NOT WRITE to this bit !!!
;
else
end
else // data should not be equal to tmp_data
begin
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
if ( ((tmp_data[31:24] === data[31:24]) && sel[3]) && ((tmp_data[23:16] === data[23:16]) && sel[2]) &&
((tmp_data[15: 8] === data[15: 8]) && sel[1]) && ((tmp_data[ 7: 0] === data[ 7: 0]) && sel[0]) )
begin
if (tmp_data !== data)
begin
fail = fail + 1;
test_fail("RW bit of the MAC buffer descriptors was not written or not read");
`TIME;
$display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
wbm_init_waits, addr, data, tmp_data);
end
fail = fail + 1;
test_fail("NON RW bit of the MAC buffer descriptors was written, but it shouldn't be");
`TIME;
$display("Wrong NON RW bit - wbm_init_waits %d, addr %h, data %h, tmp_data %h, sel %b",
wbm_init_waits, addr, data, tmp_data, sel);
end
else // data should not be equal to tmp_data
begin
if (tmp_data === data)
begin
fail = fail + 1;
test_fail("NON RW bit of the MAC buffer descriptors was written, but it shouldn't be");
`TIME;
$display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
wbm_init_waits, addr, data, tmp_data);
end
end
end
end
end
// INTERMEDIATE DISPLAYS
case (i)
0: $display(" ->buffer descriptors tested with 0 bus delay");
1: $display(" ->buffer descriptors tested with 1 bus delay cycle");
2: $display(" ->buffer descriptors tested with 2 bus delay cycles");
3: $display(" ->buffer descriptors tested with 3 bus delay cycles");
default: $display(" ->buffer descriptors tested with 4 bus delay cycles");
endcase
if (i_addr[11:0] == 12'h500)
$display(" ->buffer descriptors tested with 0 bus delay");
else if (i_addr[11:0] == 12'h600)
$display(" ->buffer descriptors tested with 1 bus delay cycle");
else if (i_addr[11:0] == 12'h700)
$display(" ->buffer descriptors tested with 2 bus delay cycles");
end
$display(" ->buffer descriptors tested with 3 bus delay cycles");
if(fail == 0)
test_ok;
else
886,123 → 1026,128
//// inverse reset values and hard reset of the MAC ////
//// ////
////////////////////////////////////////////////////////////////////
if (test_num == 2) // Start this task
if (test_num == 3) // Start this task
begin
// TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
// TEST 3: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
test_name =
"TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC";
"TEST 3: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC";
`TIME; $display(
" TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC");
" TEST 3: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC");
// reset MAC registers
hard_reset;
for (i = 0; i <= 4; i = i + 1) // 0, 2 - WRITE; 1, 3, 4 - READ
begin
for (i_addr = 0; i_addr <= 32'h4C; i_addr = i_addr + 4) // register address
for (i_addr = 0; i_addr <= {22'h0, `ETH_TX_CTRL_ADR, 2'h0}; i_addr = i_addr + 4) // register address
begin
addr = `ETH_BASE + i_addr;
// set ranges of R/W bits
case (addr)
`ETH_MODER:
begin
data = 32'h0000_A800;
data_max = 32'h0001_FFFF;
end
`ETH_INT: // READONLY - tested within INT test
begin
data = 32'h0000_0000;
data_max = 32'h0000_0000;
end
`ETH_INT_MASK:
begin
data = 32'h0000_0000;
data_max = 32'h0000_007F;
end
`ETH_IPGT:
begin
data = 32'h0000_0012;
data_max = 32'h0000_007F;
end
`ETH_IPGR1:
begin
data = 32'h0000_000C;
data_max = 32'h0000_007F;
end
`ETH_IPGR2:
begin
data = 32'h0000_0012;
data_max = 32'h0000_007F;
end
`ETH_PACKETLEN:
begin
data = 32'h0040_0600;
data_max = 32'hFFFF_FFFF;
end
`ETH_COLLCONF:
begin
data = 32'h000F_003F;
data_max = 32'h000F_003F;
end
`ETH_TX_BD_NUM:
begin
data = 32'h0000_0040;
data_max = 32'h0000_0080;
end
`ETH_CTRLMODER:
begin
data = 32'h0000_0000;
data_max = 32'h0000_0007;
end
`ETH_MIIMODER:
begin
data = 32'h0000_0064;
data_max = 32'h0000_03FF;
end
`ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
begin
data = 32'h0000_0000;
data_max = 32'h0000_0007;
end
`ETH_MIIADDRESS:
begin
data = 32'h0000_0000;
data_max = 32'h0000_1F1F;
end
`ETH_MIITX_DATA:
begin
data = 32'h0000_0000;
data_max = 32'h0000_FFFF;
end
`ETH_MIIRX_DATA: // READONLY - tested within MIIM test
begin
data = 32'h0000_0000;
data_max = 32'h0000_0000;
end
`ETH_MIISTATUS: // READONLY - tested within MIIM test
begin
data = 32'h0000_0000;
data_max = 32'h0000_0000;
end
`ETH_MAC_ADDR0:
begin
data = 32'h0000_0000;
data_max = 32'hFFFF_FFFF;
end
`ETH_MAC_ADDR1:
begin
data = 32'h0000_0000;
data_max = 32'h0000_FFFF;
end
`ETH_HASH_ADDR0:
begin
data = 32'h0000_0000;
data_max = 32'hFFFF_FFFF;
end
default: // `ETH_HASH_ADDR1:
begin
data = 32'h0000_0000;
data_max = 32'hFFFF_FFFF;
end
`ETH_MODER:
begin
data = 32'h0000_A000; // bit 11 not used any more
data_max = 32'h0001_FFFF;
end
`ETH_INT: // READONLY - tested within INT test
begin
data = 32'h0000_0000;
data_max = 32'h0000_0000;
end
`ETH_INT_MASK:
begin
data = 32'h0000_0000;
data_max = 32'h0000_007F;
end
`ETH_IPGT:
begin
data = 32'h0000_0012;
data_max = 32'h0000_007F;
end
`ETH_IPGR1:
begin
data = 32'h0000_000C;
data_max = 32'h0000_007F;
end
`ETH_IPGR2:
begin
data = 32'h0000_0012;
data_max = 32'h0000_007F;
end
`ETH_PACKETLEN:
begin
data = 32'h0040_0600;
data_max = 32'hFFFF_FFFF;
end
`ETH_COLLCONF:
begin
data = 32'h000F_003F;
data_max = 32'h000F_003F;
end
`ETH_TX_BD_NUM:
begin
data = 32'h0000_0040;
data_max = 32'h0000_0080;
end
`ETH_CTRLMODER:
begin
data = 32'h0000_0000;
data_max = 32'h0000_0007;
end
`ETH_MIIMODER:
begin
data = 32'h0000_0064;
data_max = 32'h0000_01FF;
end
`ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
begin
data = 32'h0000_0000;
data_max = 32'h0000_0000;
end
`ETH_MIIADDRESS:
begin
data = 32'h0000_0000;
data_max = 32'h0000_1F1F;
end
`ETH_MIITX_DATA:
begin
data = 32'h0000_0000;
data_max = 32'h0000_FFFF;
end
`ETH_MIIRX_DATA: // READONLY - tested within MIIM test
begin
data = 32'h0000_0000;
data_max = 32'h0000_0000;
end
`ETH_MIISTATUS: // READONLY - tested within MIIM test
begin
data = 32'h0000_0000;
data_max = 32'h0000_0000;
end
`ETH_MAC_ADDR0:
begin
data = 32'h0000_0000;
data_max = 32'hFFFF_FFFF;
end
`ETH_MAC_ADDR1:
begin
data = 32'h0000_0000;
data_max = 32'h0000_FFFF;
end
`ETH_HASH_ADDR0:
begin
data = 32'h0000_0000;
data_max = 32'hFFFF_FFFF;
end
`ETH_HASH_ADDR1:
begin
data = 32'h0000_0000;
data_max = 32'hFFFF_FFFF;
end
default: // `ETH_TX_CTRL_ADR:
begin
data = 32'h0000_0000;
data_max = 32'h0000_FFFF;
end
endcase
wbm_init_waits = {$random} % 3;
1009,10 → 1154,16
wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
if (i == 0)
begin
if (addr == `ETH_MIICOMMAND) // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
;
else
wbm_write(addr, ~data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
end
else if (i == 2)
begin
if (addr == `ETH_MIICOMMAND) // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
;
else
wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
end
else if ((i == 1) || (i == 4))
1098,18 → 1249,15
//// of the mac and reseting the logic ////
//// ////
////////////////////////////////////////////////////////////////////
if (test_num == 3) // Start this task
if (test_num == 4) // Start this task
begin
// TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
test_name = "TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC";
// TEST 4: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
test_name = "TEST 4: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC";
`TIME;
$display(" TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");
$display(" TEST 4: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");
// reset MAC registers
hard_reset;
// reset LOGIC with soft reset
// reset_mac;
// reset_mii;
for (i = 0; i <= 3; i = i + 1) // 0, 2 - WRITE; 1, 3 - READ
begin
for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
1144,9 → 1292,6
begin
// reset MAC registers
hard_reset;
// reset LOGIC with soft reset
// reset_mac;
// reset_mii;
end
end
if(fail == 0)
1156,11 → 1301,11
end
 
 
if (test_num == 4) // Start this task
if (test_num == 5) // Start this task
begin
/* // TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
test_name = "TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
`TIME; $display(" TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
/* // TEST 5: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
test_name = "TEST 5: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
`TIME; $display(" TEST 5: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
data = 0;
burst_data = 0;
1433,9 → 1578,6
 
// reset MAC registers
hard_reset;
// reset MAC and MII LOGIC with soft reset
//reset_mac;
//reset_mii;
 
 
//////////////////////////////////////////////////////////////////////
1928,7 → 2070,7
#Tp mii_read_req(phy_addr, reg_addr);
check_mii_busy; // wait for read to finish
// read data
$display(" => Two errors will be displayed from WB Bus Monitor, because correct HIGH Z data was read");
$display(" => Two error lines will be displayed from WB Bus Monitor, because correct HIGH Z data was read");
wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data !== 16'hzzzz)
begin
3019,12 → 3161,6
// MII mode register
wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
if (i)
begin
// change saved data when preamble is suppressed
#Tp tmp_data = tmp_data | 16'h0040; // put bit 6 to ONE
end
// scan request
#Tp mii_scan_req(phy_addr, reg_addr);
check_mii_scan_valid; // wait for scan to make first data valid
3264,12 → 3400,6
// MII mode register
#Tp wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
wbm_subseq_waits);
if (i2)
begin
// change saved data when preamble is suppressed
#Tp tmp_data = tmp_data | 16'h0040; // put bit 6 to ONE
end
i = 0;
while (i < 80) // delay for sliding of LinkFail bit
begin
8005,6 → 8135,7
min_tmp = 0;
num_of_frames = 0;
num_of_bd = 0;
tx_bd_num = 0;
// set 13 TX buffer descriptors - must be set before TX enable
wait (wbm_working == 0);
wbm_write(`ETH_TX_BD_NUM, 32'hD, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8053,22 → 8184,29
set_tx_bd_ready(0, 0);
end
else if (num_of_bd == 1)
begin
set_tx_bd_ready(1, 1);
tx_bd_num = 1;
end
else if (num_of_bd == 2)
begin
set_tx_bd_ready(2, 2);
tx_bd_num = 2;
end
else if (num_of_bd == 3)
begin
set_tx_bd(0, 0, 100, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
set_tx_bd_wrap(2);
set_tx_bd_ready(0, 0);
i_length = 96;
i_length = 100;
tx_bd_num = 0;
end
 
// CHECK END OF TRANSMITION
check_tx_bd(num_of_bd, data);
check_tx_bd(tx_bd_num, data);
wait (MTxEn === 1'b1); // start transmit
check_tx_bd(num_of_bd, data);
check_tx_bd(tx_bd_num, data);
if (data[15] !== 1)
begin
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
8077,7 → 8215,7
wait (MTxEn === 1'b0); // end transmit
while (data[15] === 1)
begin
check_tx_bd(num_of_bd, data);
check_tx_bd(tx_bd_num, data);
@(posedge wb_clk);
end
repeat (1) @(posedge wb_clk);
8084,11 → 8222,22
// check length of a PACKET
tmp_len = eth_phy.tx_len;
#1;
if (tmp_len != (i_length + 4))
if ((i_length + 4) <= max_tmp)
begin
test_fail("Wrong length of the packet out from MAC");
fail = fail + 1;
if (tmp_len != (i_length + 4))
begin
test_fail("Wrong length of the packet out from MAC");
fail = fail + 1;
end
end
else
begin
if (tmp_len != (i_length + 4 - 1))
begin
test_fail("Wrong length of the packet out from MAC");
fail = fail + 1;
end
end
 
// check transmitted TX packet data
if ((i_length + 4) == 100)
8123,7 → 8272,7
fail = fail + 1;
end
 
check_tx_bd(num_of_bd, data);
check_tx_bd(tx_bd_num, data);
if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
((data[15:0] !== 16'h5800) && (num_of_bd < 2)) ) // without wrap bit
begin
8207,6 → 8356,7
min_tmp = 0;
num_of_frames = 0;
num_of_bd = 0;
tx_bd_num = 0;
// set 13 TX buffer descriptors - must be set before TX enable
wait (wbm_working == 0);
wbm_write(`ETH_TX_BD_NUM, 32'hD, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8255,22 → 8405,29
set_tx_bd_ready(0, 0);
end
else if (num_of_bd == 1)
begin
set_tx_bd_ready(1, 1);
tx_bd_num = 1;
end
else if (num_of_bd == 2)
begin
set_tx_bd_ready(2, 2);
tx_bd_num = 2;
end
else if (num_of_bd == 3)
begin
set_tx_bd(0, 0, 100, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
set_tx_bd_wrap(2);
set_tx_bd_ready(0, 0);
i_length = 96;
i_length = 100;
tx_bd_num = 0;
end
 
// CHECK END OF TRANSMITION
check_tx_bd(num_of_bd, data);
check_tx_bd(tx_bd_num, data);
wait (MTxEn === 1'b1); // start transmit
check_tx_bd(num_of_bd, data);
check_tx_bd(tx_bd_num, data);
if (data[15] !== 1)
begin
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
8279,7 → 8436,7
wait (MTxEn === 1'b0); // end transmit
while (data[15] === 1)
begin
check_tx_bd(num_of_bd, data);
check_tx_bd(tx_bd_num, data);
@(posedge wb_clk);
end
repeat (1) @(posedge wb_clk);
8287,11 → 8444,22
// check length of a PACKET
tmp_len = eth_phy.tx_len;
#1;
if (tmp_len != (i_length + 4))
if ((i_length + 4) <= max_tmp)
begin
test_fail("Wrong length of the packet out from MAC");
fail = fail + 1;
if (tmp_len != (i_length + 4))
begin
test_fail("Wrong length of the packet out from MAC");
fail = fail + 1;
end
end
else
begin
if (tmp_len != (i_length + 4 - 1))
begin
test_fail("Wrong length of the packet out from MAC");
fail = fail + 1;
end
end
 
// check transmitted TX packet data
if ((i_length + 4) == 100)
8326,7 → 8494,7
fail = fail + 1;
end
 
check_tx_bd(num_of_bd, data);
check_tx_bd(tx_bd_num, data);
if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
((data[15:0] !== 16'h5800) && (num_of_bd < 2)) ) // without wrap bit
begin
8411,6 → 8579,7
min_tmp = 0;
num_of_frames = 0;
num_of_bd = 0;
tx_bd_num = 0;
// set 47 TX buffer descriptors - must be set before TX enable
wait (wbm_working == 0);
wbm_write(`ETH_TX_BD_NUM, 32'h2F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8454,20 → 8623,26
// prepare BDs
if (num_of_bd == 0)
begin
set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
set_tx_bd(0, 0, i_length+4, 1'b1, 1'b1, 1'b0, `MEMORY_BASE); // no CRC adding
set_tx_bd(1, 1, i_length+1, 1'b1, 1'b0, 1'b1, `MEMORY_BASE); // no PADDING
set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
set_tx_bd_wrap(2);
set_tx_bd_ready(0, 0);
end
else if (num_of_bd == 1)
begin
set_tx_bd_ready(1, 1);
tx_bd_num = 1;
end
else if (num_of_bd == 2)
begin
set_tx_bd_ready(2, 2);
tx_bd_num = 2;
end
// CHECK END OF TRANSMITION
check_tx_bd(num_of_bd, data);
check_tx_bd(tx_bd_num, data);
wait (MTxEn === 1'b1); // start transmit
check_tx_bd(num_of_bd, data);
check_tx_bd(tx_bd_num, data);
if (data[15] !== 1)
begin
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
8476,7 → 8651,7
wait (MTxEn === 1'b0); // end transmit
while (data[15] === 1)
begin
check_tx_bd(num_of_bd, data);
check_tx_bd(tx_bd_num, data);
@(posedge wb_clk);
end
repeat (5) @(posedge mtx_clk);
8483,13 → 8658,28
// check length of a PACKET
tmp_len = eth_phy.tx_len;
#1;
if (tmp_len != (i_length + 4))
if ((i_length + 4) <= max_tmp)
begin
test_fail("Wrong length of the packet out from MAC");
fail = fail + 1;
if (tmp_len != (i_length + 4))
begin
test_fail("Wrong length of the packet out from MAC");
fail = fail + 1;
end
end
else
begin
if (tmp_len != (i_length + 4 - 1))
begin
test_fail("Wrong length of the packet out from MAC");
fail = fail + 1;
end
end
 
// checking packet
check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
if (num_of_bd === 0)
check_tx_packet(`MEMORY_BASE, 0, i_length + 4, tmp); // also data representing CRC
else
check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
if (tmp > 0)
begin
test_fail("Wrong data of the transmitted packet");
8496,7 → 8686,7
fail = fail + 1;
end
// check transmited TX packet CRC
if (num_of_bd !== 2)
if (num_of_bd === 1)
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
if (tmp > 0)
begin
8511,9 → 8701,10
fail = fail + 1;
end
// check TX buffer descriptor of a packet
check_tx_bd(num_of_bd, data);
check_tx_bd(tx_bd_num, data);
if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
((data[15:0] !== 16'h5800) && (num_of_bd < 2)) ) // without wrap bit
((data[15:0] !== 16'h4800) && (num_of_bd == 1)) || // without wrap bit and without pad bit
((data[15:0] !== 16'h5000) && (num_of_bd == 0)) ) // without wrap bit and without crc bit
begin
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
test_fail("TX buffer descriptor status is not correct");
8589,6 → 8780,7
min_tmp = 0;
num_of_frames = 0;
num_of_bd = 0;
tx_bd_num = 0;
// set 47 TX buffer descriptors - must be set before TX enable
wait (wbm_working == 0);
wbm_write(`ETH_TX_BD_NUM, 32'h2F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8632,20 → 8824,26
// prepare BDs
if (num_of_bd == 0)
begin
set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
set_tx_bd(0, 0, i_length+4, 1'b1, 1'b1, 1'b0, `MEMORY_BASE); // no CRC adding
set_tx_bd(1, 1, i_length+1, 1'b1, 1'b0, 1'b1, `MEMORY_BASE); // no PADDING
set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
set_tx_bd_wrap(2);
set_tx_bd_ready(0, 0);
end
else if (num_of_bd == 1)
begin
set_tx_bd_ready(1, 1);
tx_bd_num = 1;
end
else if (num_of_bd == 2)
begin
set_tx_bd_ready(2, 2);
tx_bd_num = 2;
end
// CHECK END OF TRANSMITION
check_tx_bd(num_of_bd, data);
check_tx_bd(tx_bd_num, data);
wait (MTxEn === 1'b1); // start transmit
check_tx_bd(num_of_bd, data);
check_tx_bd(tx_bd_num, data);
if (data[15] !== 1)
begin
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
8654,7 → 8852,7
wait (MTxEn === 1'b0); // end transmit
while (data[15] === 1)
begin
check_tx_bd(num_of_bd, data);
check_tx_bd(tx_bd_num, data);
@(posedge wb_clk);
end
repeat (5) @(posedge mtx_clk);
8661,13 → 8859,28
// check length of a PACKET
tmp_len = eth_phy.tx_len;
#1;
if (tmp_len != (i_length + 4))
if ((i_length + 4) <= max_tmp)
begin
test_fail("Wrong length of the packet out from MAC");
fail = fail + 1;
if (tmp_len != (i_length + 4))
begin
test_fail("Wrong length of the packet out from MAC");
fail = fail + 1;
end
end
else
begin
if (tmp_len != (i_length + 4 - 1))
begin
test_fail("Wrong length of the packet out from MAC");
fail = fail + 1;
end
end
 
// checking packet
check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
if (num_of_bd === 0)
check_tx_packet(`MEMORY_BASE, 0, i_length + 4, tmp); // also data representing CRC
else
check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
if (tmp > 0)
begin
test_fail("Wrong data of the transmitted packet");
8674,7 → 8887,7
fail = fail + 1;
end
// check transmited TX packet CRC
if (num_of_bd !== 2)
if (num_of_bd === 1)
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
if (tmp > 0)
begin
8689,9 → 8902,10
fail = fail + 1;
end
// check TX buffer descriptor of a packet
check_tx_bd(num_of_bd, data);
check_tx_bd(tx_bd_num, data);
if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
((data[15:0] !== 16'h5800) && (num_of_bd < 2)) ) // without wrap bit
((data[15:0] !== 16'h4800) && (num_of_bd == 1)) || // without wrap bit and without pad bit
((data[15:0] !== 16'h5000) && (num_of_bd == 0)) ) // without wrap bit and without crc bit
begin
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
test_fail("TX buffer descriptor status is not correct");
8845,11 → 9059,22
// check length of a PACKET
tmp_len = eth_phy.tx_len;
#1;
if (tmp_len != (i_length + 4))
if ((i_length + 4) >= min_tmp)
begin
test_fail("Wrong length of the packet out from MAC");
fail = fail + 1;
if (tmp_len != (i_length + 4))
begin
test_fail("Wrong length of the packet out from MAC");
fail = fail + 1;
end
end
else
begin
if (tmp_len != (i_length + 4 + 1))
begin
test_fail("Wrong length of the packet out from MAC");
fail = fail + 1;
end
end
// checking packet
check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
if (tmp > 0)
9028,11 → 9253,22
// check length of a PACKET
tmp_len = eth_phy.tx_len;
#1;
if (tmp_len != (i_length + 4))
if ((i_length + 4) >= min_tmp)
begin
test_fail("Wrong length of the packet out from MAC");
fail = fail + 1;
if (tmp_len != (i_length + 4))
begin
test_fail("Wrong length of the packet out from MAC");
fail = fail + 1;
end
end
else
begin
if (tmp_len != (i_length + 4 + 1))
begin
test_fail("Wrong length of the packet out from MAC");
fail = fail + 1;
end
end
// checking packet
check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
if (tmp > 0)
18453,7 → 18689,8
end
else
begin
wb_slave.wr_mem(addr_wb, {crc[7:0], crc[15:8], crc[23:16], crc[31:24]}, 4'hF);
// wb_slave.wr_mem(addr_wb, {crc[7:0], crc[15:8], crc[23:16], crc[31:24]}, 4'hF);
wb_slave.wr_mem(addr_wb, crc[31:0], 4'hF);
end
delta_t = !delta_t;
end
18829,7 → 19066,7
nibble_cnt = ((len + 4) << 1) + 1'b1; // one nibble longer
else
nibble_cnt = ((len + 4) << 1);
load_reg = wb_slave.wb_memory[{12'h0, addr_cnt}];
load_reg = wb_slave.wb_memory[{12'h0, addr_cnt[21:2]}];
addr_cnt = addr_cnt + 4;
while (nibble_cnt > 0)
begin
18890,7 → 19127,7
if ((word_cnt+3) == 7)//4)
begin
// because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
load_reg = wb_slave.wb_memory[{12'h0, addr_cnt}];
load_reg = wb_slave.wb_memory[{12'h0, addr_cnt[21:2]}];
addr_cnt = addr_cnt + 4;
end
// set new load bit position
19494,6 → 19731,38
endtask // test_fail
 
 
task test_fail_num ;
input [7999:0] failure_reason ;
input [31:0] number ;
// reg [8007:0] display_failure ;
reg [7999:0] display_failure ;
reg [799:0] display_test ;
begin
tests_failed = tests_failed + 1 ;
 
display_failure = failure_reason; // {failure_reason, "!"} ;
while ( display_failure[7999:7992] == 0 )
display_failure = display_failure << 8 ;
 
display_test = test_name ;
while ( display_test[799:792] == 0 )
display_test = display_test << 8 ;
 
$fdisplay( tb_log_file, " *************************************************************************************" ) ;
$fdisplay( tb_log_file, " At time: %t ", $time ) ;
$fdisplay( tb_log_file, " Test: %s", display_test ) ;
$fdisplay( tb_log_file, " *FAILED* because") ;
$fdisplay( tb_log_file, " %s; %d", display_failure, number ) ;
$fdisplay( tb_log_file, " *************************************************************************************" ) ;
$fdisplay( tb_log_file, " " ) ;
 
`ifdef STOP_ON_FAILURE
#20 $stop ;
`endif
end
endtask // test_fail_num
 
 
task test_ok ;
reg [799:0] display_test ;
begin
/trunk/bench/verilog/wb_model_defines.v
42,9 → 42,12
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/09/13 12:29:14 mohor
// Headers changed.
//
//
//
//
 
// WISHBONE frequency in GHz
`define WB_FREQ 0.100
70,7 → 73,7
`define WB_ADDR_WIDTH 32
`define WB_DATA_WIDTH 32
`define WB_SEL_WIDTH `WB_DATA_WIDTH/8
`define WB_TAG_WIDTH 1
`define WB_TAG_WIDTH 5
`define WB_ADDR_TYPE [(`WB_ADDR_WIDTH - 1):0]
`define WB_DATA_TYPE [(`WB_DATA_WIDTH - 1):0]
`define WB_SEL_TYPE [(`WB_SEL_WIDTH - 1):0]
/trunk/bench/verilog/wb_bus_mon.v
2,19 → 2,20
//// ////
//// File name "wb_bus_mon.v" ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// This file is part of the "PCI bridge" project ////
//// http://www.opencores.org/cores/pci/ ////
//// ////
//// Author(s): ////
//// - Miha Dolenc (mihad@opencores.org) ////
//// - mihad@opencores.org ////
//// - Miha Dolenc ////
//// ////
//// All additional information is available in the README.pdf ////
//// All additional information is avaliable in the README.pdf ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
42,6 → 43,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/10/09 13:16:51 tadejm
// Just back-up; not completed testbench and some testcases are not
// wotking properly yet.
//
// Revision 1.2 2002/09/13 12:29:14 mohor
// Headers changed.
//
76,6 → 81,7
TAG_I,
TAG_O,
CAB_O,
check_CTI,
log_file_desc
) ;
 
94,191 → 100,233
input [(`WB_TAG_WIDTH-1):0] TAG_I ;
input [(`WB_TAG_WIDTH-1):0] TAG_O ;
input CAB_O ;
input check_CTI ;
input [31:0] log_file_desc ;
 
always@(posedge CLK_I or posedge RST_I)
always@(posedge CLK_I)
begin
if (RST_I)
if (RST_I !== 1'b0)
begin
// when reset is applied, all control signals must be low
if (CYC_O)
if (CYC_O !== 1'b0)
begin
$display("*E (%0t) CYC_O active under reset", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)CYC_O active under reset", $time) ;
message_out("CYC_O active under reset") ;
end
if (STB_O)
 
if (STB_O !== 1'b0)
begin
$display("*E (%0t) STB_O active under reset", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)STB_O active under reset", $time) ;
message_out("STB_O active under reset") ;
end
/*if (ACK_I)
$display("ACK_I active under reset") ;*/
if (ERR_I)
if (ACK_I !== 1'b0)
message_out("ACK_I active under reset") ;
 
if (ERR_I !== 1'b0)
begin
$display("*E (%0t) ERR_I active under reset", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I active under reset", $time) ;
message_out("ERR_I active under reset") ;
end
if (RTY_I)
 
if (RTY_I !== 1'b0)
begin
$display("*E (%0t) RTY_I active under reset", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I active under reset", $time) ;
message_out("RTY_I active under reset") ;
end
if (CAB_O)
begin
$display("*E (%0t) CAB_O active under reset", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O active under reset", $time) ;
end
 
end // reset
else
if (~CYC_O)
if (CYC_O !== 1'b1)
begin
// when cycle indicator is low, all control signals must be low
if (STB_O)
if (STB_O !== 1'b0)
begin
$display("*E (%0t) STB_O active without CYC_O being active", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)STB_O active without CYC_O being active", $time) ;
message_out("STB_O active without CYC_O being active") ;
end
if (ACK_I)
 
if (ACK_I !== 1'b0)
begin
$display("*E (%0t) ACK_I active without CYC_O being active", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I active without CYC_O being active", $time) ;
message_out("ACK_I active without CYC_O being active") ;
end
if (ERR_I)
 
if (ERR_I !== 1'b0)
begin
$display("*E (%0t) ERR_I active without CYC_O being active", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I active without CYC_O being active", $time) ;
message_out("ERR_I active without CYC_O being active") ;
end
if (RTY_I)
 
if (RTY_I !== 1'b0)
begin
$display("*E (%0t) RTY_I active without CYC_O being active", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I active without CYC_O being active", $time) ;
message_out("RTY_I active without CYC_O being active") ;
end
if (CAB_O)
begin
$display("*E (%0t) CAB_O active without CYC_O being active", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O active without CYC_O being active", $time) ;
end
 
end // ~CYC_O
end
 
reg [`WB_DATA_WIDTH-1:0] previous_data ;
reg [`WB_DATA_WIDTH-1:0] previous_data_o ;
reg [`WB_DATA_WIDTH-1:0] previous_data_i ;
reg [`WB_ADDR_WIDTH-1:0] previous_address ;
reg [`WB_SEL_WIDTH-1:0] previous_sel ;
reg [`WB_TAG_WIDTH-1:0] previous_tag ;
reg previous_stb ;
reg previous_ack ;
reg previous_err ;
reg previous_rty ;
reg previous_cyc ;
reg can_change ;
reg previous_we ;
 
always@(posedge CLK_I or posedge RST_I)
begin
if (RST_I)
begin
previous_stb <= 1'b0 ;
previous_ack <= 1'b0 ;
previous_err <= 1'b0 ;
previous_rty <= 1'b0 ;
previous_cyc <= 1'b0 ;
previous_stb <= 1'b0 ;
previous_ack <= 1'b0 ;
previous_err <= 1'b0 ;
previous_rty <= 1'b0 ;
previous_cyc <= 1'b0 ;
previous_tag <= 'd0 ;
previous_we <= 1'b0 ;
previous_data_o <= 0 ;
previous_data_i <= 0 ;
previous_address <= 0 ;
previous_sel <= 0 ;
end
else
begin
previous_stb <= STB_O ;
previous_ack <= ACK_I ;
previous_err <= ERR_I ;
previous_rty <= RTY_I ;
previous_cyc <= CYC_O ;
previous_stb <= STB_O ;
previous_ack <= ACK_I ;
previous_err <= ERR_I ;
previous_rty <= RTY_I ;
previous_cyc <= CYC_O ;
previous_tag <= TAG_O ;
previous_we <= WE_O ;
previous_data_o <= DAT_O ;
previous_data_i <= DAT_I ;
previous_address <= ADDR_O ;
previous_sel <= SEL_O ;
end
end
 
// cycle monitor
always@(posedge CLK_I)
begin
if (CYC_O && ~RST_I) // cycle in progress
begin:cycle_monitor_blk
reg master_can_change ;
reg slave_can_change ;
 
if ((CYC_O !== 1'b0) & (RST_I !== 1'b1)) // cycle in progress
begin
if (STB_O)
// check for two control signals active at same edge
if ( (ACK_I !== 1'b0) & (RTY_I !== 1'b0) )
begin
// check for two control signals active at same edge
if ( ACK_I && RTY_I )
begin
$display("*E (%0t) ACK_I and RTY_I asserted at the same time during cycle", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I and RTY_I asserted at the same time during cycle", $time) ;
end
if ( ACK_I && ERR_I )
begin
$display("*E (%0t) ACK_I and ERR_I asserted at the same time during cycle", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I and ERR_I asserted at the same time during cycle", $time) ;
end
if ( RTY_I && ERR_I )
begin
$display("*E (%0t) RTY_I and ERR_I asserted at the same time during cycle", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I and ERR_I asserted at the same time during cycle", $time) ;
end
message_out("ACK_I and RTY_I asserted at the same time during cycle") ;
end
 
if ( can_change !== 1 )
begin
if ( ADDR_O !== previous_address )
begin
$display("*E (%0t) WB bus monitor detected address change in the middle of the cycle!", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected address change in the middle of the cycle!", $time) ;
end
if ( (ACK_I !== 1'b0) & (ERR_I !== 1'b0) )
begin
message_out("ACK_I and ERR_I asserted at the same time during cycle") ;
end
 
if ( SEL_O !== previous_sel )
begin
$display("*E (%0t) WB bus monitor detected select lines changed in the middle of the cycle!", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected select lines changed in the middle of the cycle!", $time) ;
end
if ( (RTY_I !== 1'b0) & (ERR_I !== 1'b0) )
begin
message_out("RTY_I and ERR_I asserted at the same time during cycle") ;
end
 
if ( (WE_O !== 0) && ( DAT_O !== previous_data ) )
begin
$display("*E (%0t) WB bus monitor detected data lines changed in the middle of the cycle!", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected data lines changed in the middle of the cycle!", $time) ;
end
if (previous_cyc === 1'b1)
begin
if (previous_stb === 1'b1)
begin
if ((previous_ack === 1'b1) | (previous_rty === 1'b1) | (previous_err === 1'b1))
master_can_change = 1'b1 ;
else
master_can_change = 1'b0 ;
end
 
if ( ACK_I || RTY_I || ERR_I )
can_change = 1 ;
else
begin
previous_data = DAT_O ;
previous_address = ADDR_O ;
previous_sel = SEL_O ;
can_change = 0 ;
master_can_change = 1'b1 ;
end
 
end // STB_O
else
begin //~STB_O
// while STB_O is inactive, only ACK_I is allowed to be active
if ( ERR_I )
if ((previous_ack === 1'b1) | (previous_err === 1'b1) | (previous_rty === 1'b1))
begin
$display("*E (%0t) ERR_I asserted during cycle without STB_O", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I asserted during cycle without STB_O", $time) ;
if (previous_stb === 1'b1)
slave_can_change = 1'b1 ;
else
slave_can_change = 1'b0 ;
end
if ( RTY_I )
else
begin
$display("*E (%0t) RTY_I asserted during cycle without STB_O", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I asserted during cycle without STB_O", $time) ;
slave_can_change = 1'b1 ;
end
end
else
begin
master_can_change = 1'b1 ;
slave_can_change = 1'b1 ;
end
end
else
begin
master_can_change = 1'b1 ;
slave_can_change = 1'b1 ;
end
 
if ((previous_ack !== 1) && (previous_err !== 1) && (previous_rty !== 1) && (previous_stb !== 0))
if (master_can_change !== 1'b1)
begin
if (CYC_O !== previous_cyc)
begin
message_out("Master violated WISHBONE protocol by changing the value of CYC_O signal at inappropriate time!") ;
end
 
if (STB_O !== previous_stb)
begin
message_out("Master violated WISHBONE protocol by changing the value of STB_O signal at inappropriate time!") ;
end
 
if (TAG_O !== previous_tag)
begin
message_out("Master violated WISHBONE protocol by changing the value of TAG_O signals at inappropriate time!") ;
end
 
if (ADDR_O !== previous_address)
begin
message_out("Master violated WISHBONE protocol by changing the value of ADR_O signals at inappropriate time!") ;
end
 
if (SEL_O !== previous_sel)
begin
message_out("Master violated WISHBONE protocol by changing the value of SEL_O signals at inappropriate time!") ;
end
 
if (WE_O !== previous_we)
begin
message_out("Master violated WISHBONE protocol by changing the value of WE_O signal at inappropriate time!") ;
end
 
if (WE_O !== 1'b0)
begin
if (DAT_O !== previous_data_o)
begin
$display("STB_O de-asserted without reception of slave response") ;
$fdisplay(log_file_desc, "STB_O de-asserted without reception of slave response") ;
message_out("Master violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;
end
end
end
 
can_change = 1 ;
end // ~STB_O
end // cycle in progress
else if (!RST_I)
if (slave_can_change !== 1'b1)
begin
// cycle not in progress anymore
can_change = 1 ;
if ((previous_ack !== 1) && (previous_err !== 1) && (previous_rty !== 1) && (previous_stb !== 0))
if (previous_ack !== ACK_I)
begin
$display("STB_O de-asserted without reception of slave response") ;
$fdisplay(log_file_desc, "STB_O de-asserted without reception of slave response") ;
message_out("Slave violated WISHBONE protocol by changing the value of ACK_O signal at inappropriate time!") ;
end
 
if (previous_rty !== RTY_I)
begin
message_out("Slave violated WISHBONE protocol by changing the value of RTY_O signal at inappropriate time!") ;
end
 
if (previous_err !== ERR_I)
begin
message_out("Slave violated WISHBONE protocol by changing the value of ERR_O signal at inappropriate time!") ;
end
 
if (previous_data_i !== DAT_I)
begin
message_out("Slave violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;
end
end
end // cycle monitor
 
295,12 → 343,55
first_cab_val <= {1'b1, CAB_O} ;
else if ( first_cab_val[0] !== CAB_O )
begin
$display("*E (%0t) CAB_O value changed during cycle", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O value changed during cycle", $time) ;
$display("CAB_O value changed during cycle") ;
$fdisplay(log_file_desc, "CAB_O value changed during cycle") ;
end
end
end // CAB_O monitor
 
// CTI_O[2:0] (TAG_O[4:2]) monitor for bursts
reg [2:0] first_cti_val ;
always@(posedge CLK_I or posedge RST_I)
begin
if (RST_I)
first_cti_val <= 3'b000 ;
// logging for burst cycle
else if ( check_CTI && ((CYC_O === 0) && (first_cti_val == 3'b011) && ~(previous_rty || previous_err)))
begin
message_out("Master violated WISHBONE protocol by NOT changing the CTI_O signals to '111' when end of burst!") ;
$display("CTI_O didn't change to '111' when end of burst") ;
$fdisplay(log_file_desc, "CTI_O didn't change to '111' when end of burst") ;
first_cti_val <= 3'b000 ;
end
else if (CYC_O === 0)
first_cti_val <= 3'b000 ;
else
begin
if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b000) && (ACK_I || ERR_I || RTY_I))
first_cti_val <= 3'b001 ;
else if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b111) && (ACK_I || ERR_I || RTY_I))
first_cti_val <= 3'b010 ;
else if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b010) && (ACK_I || ERR_I || RTY_I))
first_cti_val <= 3'b011 ;
else if ((first_cti_val == 3'b011) && (TAG_O[4:2] === 3'b111) && (ACK_I || ERR_I || RTY_I))
first_cti_val <= 3'b010 ;
// logging for clasic cycles
else if (check_CTI && ((first_cti_val == 3'b001) && (TAG_O[4:2] !== 3'b000)))
begin
message_out("Master violated WISHBONE protocol by changing the CTI_O signals during CYC_O when clasic cycle!") ;
$display("CTI_O change during CYC_O when clasic cycle") ;
$fdisplay(log_file_desc, "CTI_O change during CYC_O when clasic cycle") ;
end
// logging for end of burs cycle
else if (check_CTI && (first_cti_val == 3'b010))
begin
message_out("Master violated WISHBONE protocol by changing the CTI_O signals to '111' before end of burst!") ;
$display("CTI_O change to '111' before end of burst") ;
$fdisplay(log_file_desc, "CTI_O change to '111' before end of burst") ;
end
end
end
 
// WE_O monitor for consecutive address bursts
reg [1:0] first_we_val ;
always@(posedge CLK_I or posedge RST_I)
315,8 → 406,8
first_we_val <= {1'b1, WE_O} ;
else if ( first_we_val[0] != WE_O )
begin
$display("*E (%0t) WE_O value changed during CAB cycle", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)WE_O value changed during CAB cycle", $time) ;
$display("WE_O value changed during CAB cycle") ;
$fdisplay(log_file_desc, "WE_O value changed during CAB cycle") ;
end
end
end // CAB_O monitor
332,16 → 423,18
if (STB_O && ACK_I)
begin
if (address[`WB_ADDR_WIDTH] == 1'b0)
address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
begin
address <= (ADDR_O + `WB_SEL_WIDTH) | { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
end
else
begin
if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
begin
$display("*E (%0t) Consecutive address burst address incrementing incorrect", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)Consecutive address burst address incrementing incorrect", $time) ;
$display("Expected ADR_O = 0x%h, Actual = 0x%h", address[(`WB_ADDR_WIDTH-1):0], ADDR_O) ;
message_out("Consecutive address burst address incrementing incorrect") ;
end
else
address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
address <= (ADDR_O + `WB_SEL_WIDTH) | { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
end
end
end
349,53 → 442,78
 
// data monitor
always@(posedge CLK_I or posedge RST_I)
begin
if (CYC_O && STB_O && ~RST_I)
begin:data_monitor_blk
reg last_valid_we ;
reg [`WB_SEL_WIDTH - 1:0] last_valid_sel ;
 
if ((CYC_O !== 1'b0) & (RST_I !== 1'b1))
begin
if ( ((^ADDR_O) !== 1'b1) && ((^ADDR_O) !== 1'b0) )
if (STB_O !== 1'b0)
begin
$display("*E (%0t) Master provided invalid address and qualified it with STB_O", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)Master provided invalid address and qualified it with STB_O", $time) ;
end
if ( WE_O )
begin
if (
(SEL_O[0] && (((^DAT_O[7:0]) !== 1'b0) && ((^DAT_O[7:0]) !== 1'b1))) ||
(SEL_O[1] && (((^DAT_O[15:8]) !== 1'b0) && ((^DAT_O[15:8]) !== 1'b1))) ||
(SEL_O[2] && (((^DAT_O[23:16]) !== 1'b0) && ((^DAT_O[23:16]) !== 1'b1))) ||
(SEL_O[3] && (((^DAT_O[31:24]) !== 1'b0) && ((^DAT_O[31:24]) !== 1'b1)))
)
last_valid_we = WE_O ;
last_valid_sel = SEL_O ;
 
if ( (ADDR_O ^ ADDR_O) !== 0 )
begin
$display("*E (%0t) Master provided invalid data during write and qualified it with STB_O", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)Master provided invalid data during write and qualified it with STB_O", $time) ;
$display("*E (%0t) Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", $time, SEL_O, DAT_O) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", $time, SEL_O, DAT_O) ;
message_out("Master provided invalid ADR_O and qualified it with STB_O") ;
end
if ( (SEL_O ^ SEL_O) !== 0 )
begin
message_out("Master provided invalid SEL_O and qualified it with STB_O") ;
end
 
if ( WE_O )
begin
if (
( SEL_O[0] & ((DAT_O[ 7:0 ] ^ DAT_O[ 7:0 ]) !== 0) ) |
( SEL_O[1] & ((DAT_O[15:8 ] ^ DAT_O[15:8 ]) !== 0) ) |
( SEL_O[2] & ((DAT_O[23:16] ^ DAT_O[23:16]) !== 0) ) |
( SEL_O[3] & ((DAT_O[31:24] ^ DAT_O[31:24]) !== 0) )
)
begin
message_out("Master provided invalid data during write and qualified it with STB_O") ;
$display("Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", SEL_O, DAT_O) ;
$fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", SEL_O, DAT_O) ;
end
end
 
if ((TAG_O ^ TAG_O) !== 0)
begin
message_out("Master provided invalid TAG_O and qualified it with STB_O!") ;
end
end
else
if (~WE_O && ACK_I)
 
if ((last_valid_we !== 1'b1) & (ACK_I !== 1'b0))
begin
if (
(SEL_O[0] && (((^DAT_I[7:0]) !== 1'b0) && ((^DAT_I[7:0]) !== 1'b1))) ||
(SEL_O[1] && (((^DAT_I[15:8]) !== 1'b0) && ((^DAT_I[15:8]) !== 1'b1))) ||
(SEL_O[2] && (((^DAT_I[23:16]) !== 1'b0) && ((^DAT_I[23:16]) !== 1'b1))) ||
(SEL_O[3] && (((^DAT_I[31:24]) !== 1'b0) && ((^DAT_I[31:24]) !== 1'b1)))
( SEL_O[0] & ((DAT_I[ 7:0 ] ^ DAT_I[ 7:0 ]) !== 0) ) |
( SEL_O[1] & ((DAT_I[15:8 ] ^ DAT_I[15:8 ]) !== 0) ) |
( SEL_O[2] & ((DAT_I[23:16] ^ DAT_I[23:16]) !== 0) ) |
( SEL_O[3] & ((DAT_I[31:24] ^ DAT_I[31:24]) !== 0) )
)
begin
$display("*E (%0t) Slave provided invalid data during read and qualified it with ACK_I", $time) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)Slave provided invalid data during read and qualified it with ACK_I", $time) ;
$display("*E (%0t) Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", $time, SEL_O, DAT_I) ;
$fdisplay(log_file_desc, "*E (%0t)(%m)Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", $time, SEL_O, DAT_I) ;
message_out("Slave provided invalid data during read and qualified it with ACK_I") ;
$display("Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", last_valid_sel, DAT_I) ;
$fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", last_valid_sel, DAT_I) ;
end
end
end
else
begin
last_valid_sel = {`WB_SEL_WIDTH{1'bx}} ;
last_valid_we = 1'bx ;
end
end
 
initial
task message_out ;
input [7999:0] message_i ;
begin
previous_data = 0 ;
previous_address = 0 ;
can_change = 1 ;
$display("Time: %t", $time) ;
$display("%m, %0s", message_i) ;
$fdisplay(log_file_desc, "Time: %t", $time) ;
$fdisplay(log_file_desc, "%m, %0s", message_i) ;
end
endtask // display message
 
endmodule // BUS_MON

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