URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 32 to Rev 33
- ↔ Reverse comparison
Rev 32 → Rev 33
/trunk/rtl/verilog/eth_wishbonedma.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.7 2001/11/13 14:23:56 mohor |
// Generic memory model is used. Defines are changed for the same reason. |
// |
// Revision 1.6 2001/10/19 11:24:29 mohor |
// Number of addresses (wb_adr_i) minimized. |
// |
103,7 → 106,7
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, |
|
// Register |
r_TxEn, r_RxEn, r_RxBDAddress, r_DmaEn, RX_BD_ADR_Wr, |
r_TxEn, r_RxEn, r_RxBDNum, r_DmaEn, RX_BD_NUM_Wr, |
|
WillSendControlFrame, TxCtrlEndFrm, |
|
162,9 → 165,9
//Register |
input r_TxEn; // Transmit enable |
input r_RxEn; // Receive enable |
input [7:0] r_RxBDAddress; // Receive buffer descriptor address |
input [7:0] r_RxBDNum; // Receive buffer descriptor number |
input r_DmaEn; // DMA enable |
input RX_BD_ADR_Wr; // RxBDAddress written |
input RX_BD_NUM_Wr; // RxBDNumber written |
|
// Interrupts |
output TxB_IRQ; |
780,7 → 783,7
|
// Temporary Tx and Rx buffer descriptor address |
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1) ; // Tx BD increment or wrap (last BD) |
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_RxBDAddress) | // Using first Rx BD |
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_RxBDNum) | // Using first Rx BD |
{8{~WrapRxStatusBit}} & (RxBDAddress + 1) ; // Using next Rx BD (incremenrement address) |
|
|
801,7 → 804,7
if(WB_RST_I) |
RxBDAddress <=#Tp 8'h0; |
else |
if(RX_BD_ADR_Wr) // When r_RxBDAddress is updated, RxBDAddress is also |
if(RX_BD_NUM_Wr) // When r_RxBDNum is updated, RxBDAddress is also |
RxBDAddress <=#Tp WB_DAT_I[7:0]; |
else |
if(RxStatusWrite) |
/trunk/rtl/verilog/eth_top.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2001/10/19 11:24:29 mohor |
// Number of addresses (wb_adr_i) minimized. |
// |
// Revision 1.5 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
218,7 → 221,7
wire [15:0] r_MinFL; // Minimum frame length |
wire [47:0] r_MAC; // MAC address |
|
wire [7:0] r_RxBDAddress; // Receive buffer descriptor base address |
wire [7:0] r_RxBDNum; // Receive buffer descriptor number |
wire [6:0] r_IPGT; // |
wire [6:0] r_IPGR1; // |
wire [6:0] r_IPGR2; // |
228,7 → 231,7
wire [3:0] r_MaxRet; // |
wire r_NoBckof; // |
wire r_ExDfrEn; // |
wire RX_BD_ADR_Wr; // Write enable that writes RX_BD_ADR to the registers. |
wire RX_BD_NUM_Wr; // Write enable that writes RX_BD_NUM to the registers. |
wire TPauseRq; // Sinhronized Tx PAUSE request |
wire [15:0] TxPauseTV; // Tx PAUSE timer value |
wire r_TxFlow; // Tx flow control enable |
280,7 → 283,7
.NValid_stat(NValid_stat), .Busy_stat(Busy_stat), |
.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart), |
.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd), |
.r_RxBDAddress(r_RxBDAddress), .RX_BD_ADR_Wr(RX_BD_ADR_Wr), .int_o(int_o) |
.r_RxBDNum(r_RxBDNum), .RX_BD_NUM_Wr(RX_BD_NUM_Wr), .int_o(int_o) |
); |
|
|
505,8 → 508,8
.TxCtrlEndFrm(TxCtrlEndFrm), |
|
// Register |
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_RxBDAddress(r_RxBDAddress), |
.r_DmaEn(r_DmaEn), .RX_BD_ADR_Wr(RX_BD_ADR_Wr), |
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_RxBDNum(r_RxBDNum), |
.r_DmaEn(r_DmaEn), .RX_BD_NUM_Wr(RX_BD_NUM_Wr), |
|
//RX |
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid), |