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URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 320 to Rev 321
    Reverse comparison

Rev 320 → Rev 321

/trunk/rtl/verilog/eth_rxethmac.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11 2004/03/17 09:32:15 igorm
// Multicast detection fixed. Only the LSB of the first byte is checked.
//
// Revision 1.10 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
146,7 → 149,7
reg RxEndFrm;
reg Broadcast;
reg Multicast;
reg [8:0] CrcHash;
reg [5:0] CrcHash;
reg CrcHashGood;
reg DelayData;
reg [3:0] LatchedNibble;
212,7 → 215,7
.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
.ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
.HASH0(r_HASH0), .HASH1(r_HASH1),
.CrcHash(CrcHash[5:0]), .CrcHashGood(CrcHashGood), .StateData(StateData),
.CrcHash(CrcHash), .CrcHashGood(CrcHashGood), .StateData(StateData),
.Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort),
.RxEndFrm(RxEndFrm), .AddressMiss(AddressMiss), .PassAll(PassAll),
.ControlFrmAddressOK(ControlFrmAddressOK)
245,10 → 248,10
always @ (posedge MRxClk)
begin
if(Reset | StateIdle)
CrcHash[8:0] <= #Tp 9'h0;
CrcHash[5:0] <= #Tp 6'h0;
else
if(StateData[0] & ByteCntEq6)
CrcHash[8:0] <= #Tp Crc[31:23];
CrcHash[5:0] <= #Tp Crc[31:26];
end
 
 
/trunk/rtl/verilog/eth_wishbone.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.54 2003/11/12 18:24:59 tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
// Revision 1.53 2003/10/17 07:46:17 markom
// mbist signals updated according to newest convention
//
264,7 → 267,7
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
// Register
r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RxFlow, r_PassAll,
r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
 
// Interrupts
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
372,7 → 375,6
input r_TxEn; // Transmit enable
input r_RxEn; // Receive enable
input [7:0] r_TxBDNum; // Receive buffer descriptor number
input TX_BD_NUM_Wr; // RxBDNumber written
 
// Interrupts
output TxB_IRQ;
505,6 → 507,8
reg WbEn, WbEn_q;
reg RxEn, RxEn_q;
reg TxEn, TxEn_q;
reg r_TxEn_q;
reg r_RxEn_q;
 
wire ram_ce;
wire [3:0] ram_we;
649,6 → 653,8
WbEn_q <=#Tp 1'b0;
RxEn_q <=#Tp 1'b0;
TxEn_q <=#Tp 1'b0;
r_TxEn_q <=#Tp 1'b0;
r_RxEn_q <=#Tp 1'b0;
end
else
begin
655,6 → 661,7
WbEn_q <=#Tp WbEn;
RxEn_q <=#Tp RxEn;
TxEn_q <=#Tp TxEn;
r_RxEn_q <=#Tp r_RxEn;
end
end
 
1340,8 → 1347,9
begin
if(Reset)
TxBDAddress <=#Tp 8'h0;
else
if(TxStatusWrite)
else if (r_TxEn & (~r_TxEn_q))
TxBDAddress <=#Tp 8'h0;
else if (TxStatusWrite)
TxBDAddress <=#Tp TempTxBDAddress;
end
 
1350,12 → 1358,10
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF_0 << 1;
else
if(TX_BD_NUM_Wr) // When r_TxBDNum is updated, RxBDAddress is also
RxBDAddress <=#Tp WB_DAT_I[7:0] << 1;
else
if(RxStatusWrite)
RxBDAddress <=#Tp 8'h0;
else if(r_RxEn & (~r_RxEn_q))
RxBDAddress <=#Tp r_TxBDNum << 1;
else if(RxStatusWrite)
RxBDAddress <=#Tp TempRxBDAddress;
end
 
/trunk/rtl/verilog/eth_top.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.49 2003/11/12 18:24:59 tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
// Revision 1.48 2003/10/17 07:46:16 markom
// mbist signals updated according to newest convention
//
416,7 → 419,6
wire [3:0] r_MaxRet; //
wire r_NoBckof; //
wire r_ExDfrEn; //
wire TX_BD_NUM_Wr; // Write enable that writes RX_BD_NUM to the registers.
wire r_TxFlow; // Tx flow control enable
wire r_IFG; // Minimum interframe gap for incoming packets
 
514,7 → 516,7
.NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
.r_TxBDNum(r_TxBDNum), .TX_BD_NUM_Wr(TX_BD_NUM_Wr), .int_o(int_o),
.r_TxBDNum(r_TxBDNum), .int_o(int_o),
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq),
.r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm),
.StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i),
882,7 → 884,7
 
// Register
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum),
.TX_BD_NUM_Wr(TX_BD_NUM_Wr), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
.r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
 
//RX
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
/trunk/rtl/verilog/eth_registers.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.27 2004/04/26 11:42:17 igorm
// TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.
//
// Revision 1.26 2003/11/12 18:24:59 tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
165,7 → 168,7
r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
LinkFail, r_MAC, WCtrlDataStart, RStatStart,
UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o,
r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
StartTxDone, TxClk, RxClk, SetPauseTimer
);
249,7 → 252,6
 
output [47:0]r_MAC;
output [7:0] r_TxBDNum;
output TX_BD_NUM_Wr;
output int_o;
output [15:0]r_TxPauseTV;
output r_TxPauseRq;
326,6 → 328,7
wire [3:0] HASH1_Wr;
wire [2:0] TXCTRL_Wr;
wire [1:0] RXCTRL_Wr;
wire [0:0] TX_BD_NUM_Wr;
 
assign MODER_Wr[0] = Write[0] & MODER_Sel;
assign MODER_Wr[1] = Write[1] & MODER_Sel;
371,7 → 374,7
assign TXCTRL_Wr[2] = Write[2] & TXCTRL_Sel;
assign RXCTRL_Wr[0] = Write[0] & RXCTRL_Sel;
assign RXCTRL_Wr[1] = Write[1] & RXCTRL_Sel;
assign TX_BD_NUM_Wr = Write[0] & TX_BD_NUM_Sel & (DataIn<='h80);
assign TX_BD_NUM_Wr[0] = Write[0] & TX_BD_NUM_Sel & (DataIn<='h80);
 
 
 
541,7 → 544,7
(
.DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
.DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
.Write (TX_BD_NUM_Wr),
.Write (TX_BD_NUM_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)

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