URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 33 to Rev 34
- ↔ Reverse comparison
Rev 33 → Rev 34
/trunk/rtl/verilog/eth_defines.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2001/12/05 10:21:37 mohor |
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. |
// |
// Revision 1.4 2001/11/13 14:23:56 mohor |
// Generic memory model is used. Defines are changed for the same reason. |
// |
91,7 → 94,7
`define ETH_IPGR2_ADR 6'h5 // 0x14 |
`define ETH_PACKETLEN_ADR 6'h6 // 0x18 |
`define ETH_COLLCONF_ADR 6'h7 // 0x1C |
`define ETH_RX_BD_NUM_ADR 6'h8 // 0x20 |
`define ETH_TX_BD_NUM_ADR 6'h8 // 0x20 |
`define ETH_CTRLMODER_ADR 6'h9 // 0x24 |
`define ETH_MIIMODER_ADR 6'hA // 0x28 |
`define ETH_MIICOMMAND_ADR 6'hB // 0x2C |
122,4 → 125,4
`define ETH_MAC_ADDR0_DEF 32'h00000000 |
`define ETH_MAC_ADDR1_DEF 32'h00000000 |
|
`define ETH_RX_BD_NUM_DEF 8'h80 |
`define ETH_TX_BD_NUM_DEF 8'h80 |
/trunk/rtl/verilog/eth_wishbonedma.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2001/12/05 10:45:59 mohor |
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. |
// |
// Revision 1.7 2001/11/13 14:23:56 mohor |
// Generic memory model is used. Defines are changed for the same reason. |
// |
106,7 → 109,7
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, |
|
// Register |
r_TxEn, r_RxEn, r_RxBDNum, r_DmaEn, RX_BD_NUM_Wr, |
r_TxEn, r_RxEn, r_TxBDNum, r_DmaEn, TX_BD_NUM_Wr, |
|
WillSendControlFrame, TxCtrlEndFrm, |
|
165,9 → 168,9
//Register |
input r_TxEn; // Transmit enable |
input r_RxEn; // Receive enable |
input [7:0] r_RxBDNum; // Receive buffer descriptor number |
input [7:0] r_TxBDNum; // Receive buffer descriptor number |
input r_DmaEn; // DMA enable |
input RX_BD_NUM_Wr; // RxBDNumber written |
input TX_BD_NUM_Wr; // RxBDNumber written |
|
// Interrupts |
output TxB_IRQ; |
783,7 → 786,7
|
// Temporary Tx and Rx buffer descriptor address |
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1) ; // Tx BD increment or wrap (last BD) |
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_RxBDNum) | // Using first Rx BD |
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum) | // Using first Rx BD |
{8{~WrapRxStatusBit}} & (RxBDAddress + 1) ; // Using next Rx BD (incremenrement address) |
|
|
804,7 → 807,7
if(WB_RST_I) |
RxBDAddress <=#Tp 8'h0; |
else |
if(RX_BD_NUM_Wr) // When r_RxBDNum is updated, RxBDAddress is also |
if(TX_BD_NUM_Wr) // When r_TxBDNum is updated, RxBDAddress is also |
RxBDAddress <=#Tp WB_DAT_I[7:0]; |
else |
if(RxStatusWrite) |
/trunk/rtl/verilog/eth_top.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.7 2001/12/05 10:45:59 mohor |
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. |
// |
// Revision 1.6 2001/10/19 11:24:29 mohor |
// Number of addresses (wb_adr_i) minimized. |
// |
221,7 → 224,7
wire [15:0] r_MinFL; // Minimum frame length |
wire [47:0] r_MAC; // MAC address |
|
wire [7:0] r_RxBDNum; // Receive buffer descriptor number |
wire [7:0] r_TxBDNum; // Receive buffer descriptor number |
wire [6:0] r_IPGT; // |
wire [6:0] r_IPGR1; // |
wire [6:0] r_IPGR2; // |
231,7 → 234,7
wire [3:0] r_MaxRet; // |
wire r_NoBckof; // |
wire r_ExDfrEn; // |
wire RX_BD_NUM_Wr; // Write enable that writes RX_BD_NUM to the registers. |
wire TX_BD_NUM_Wr; // Write enable that writes RX_BD_NUM to the registers. |
wire TPauseRq; // Sinhronized Tx PAUSE request |
wire [15:0] TxPauseTV; // Tx PAUSE timer value |
wire r_TxFlow; // Tx flow control enable |
283,7 → 286,7
.NValid_stat(NValid_stat), .Busy_stat(Busy_stat), |
.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart), |
.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd), |
.r_RxBDNum(r_RxBDNum), .RX_BD_NUM_Wr(RX_BD_NUM_Wr), .int_o(int_o) |
.r_TxBDNum(r_TxBDNum), .TX_BD_NUM_Wr(TX_BD_NUM_Wr), .int_o(int_o) |
); |
|
|
508,8 → 511,8
.TxCtrlEndFrm(TxCtrlEndFrm), |
|
// Register |
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_RxBDNum(r_RxBDNum), |
.r_DmaEn(r_DmaEn), .RX_BD_NUM_Wr(RX_BD_NUM_Wr), |
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum), |
.r_DmaEn(r_DmaEn), .TX_BD_NUM_Wr(TX_BD_NUM_Wr), |
|
//RX |
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid), |
/trunk/rtl/verilog/eth_registers.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2001/12/05 10:22:19 mohor |
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. |
// |
// Revision 1.4 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
91,7 → 94,7
r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat, |
r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat, |
LinkFail, r_MAC, WCtrlDataStart, RStatStart, |
UpdateMIIRX_DATAReg, Prsd, r_RxBDNum, RX_BD_NUM_Wr, int_o |
UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o |
); |
|
parameter Tp = 1; |
173,8 → 176,8
input LinkFail; |
|
output [47:0]r_MAC; |
output [7:0] r_RxBDNum; |
output RX_BD_NUM_Wr; |
output [7:0] r_TxBDNum; |
output TX_BD_NUM_Wr; |
output int_o; |
|
reg irq_txb; |
204,7 → 207,7
wire MIISTATUS_Wr = (Address == `ETH_MIISTATUS_ADR ) & Write; |
wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR ) & Write; |
wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR ) & Write; |
assign RX_BD_NUM_Wr = (Address == `ETH_RX_BD_NUM_ADR ) & Write; |
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR ) & Write; |
|
|
|
225,7 → 228,7
wire [31:0] MIISTATUSOut; |
wire [31:0] MAC_ADDR0Out; |
wire [31:0] MAC_ADDR1Out; |
wire [31:0] RX_BD_NUMOut; |
wire [31:0] TX_BD_NUMOut; |
|
eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF)); |
eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF)); |
259,8 → 262,8
eth_register #(32) MAC_ADDR0 (.DataIn(DataIn), .DataOut(MAC_ADDR0Out), .Write(MAC_ADDR0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR0_DEF)); |
eth_register #(32) MAC_ADDR1 (.DataIn(DataIn), .DataOut(MAC_ADDR1Out), .Write(MAC_ADDR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR1_DEF)); |
|
assign RX_BD_NUMOut[31:8] = 24'h0; |
eth_register #(8) RX_BD_NUM (.DataIn(DataIn[7:0]), .DataOut(RX_BD_NUMOut[7:0]), .Write(RX_BD_NUM_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_RX_BD_NUM_DEF)); |
assign TX_BD_NUMOut[31:8] = 24'h0; |
eth_register #(8) TX_BD_NUM (.DataIn(DataIn[7:0]), .DataOut(TX_BD_NUMOut[7:0]), .Write(TX_BD_NUM_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_TX_BD_NUM_DEF)); |
|
|
reg LinkFailRegister; |
292,7 → 295,7
IPGR1Out or IPGR2Out or PACKETLENOut or COLLCONFOut or CTRLMODEROut or |
MIIMODEROut or MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or |
MIIRX_DATAOut or MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or |
RX_BD_NUMOut) |
TX_BD_NUMOut) |
begin |
if(Read) // read |
begin |
314,7 → 317,7
`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut; |
`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out; |
`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out; |
`ETH_RX_BD_NUM_ADR : DataOut<=RX_BD_NUMOut; |
`ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut; |
default: DataOut<=32'h0; |
endcase |
end |
382,7 → 385,7
assign r_MAC[31:0] = MAC_ADDR0Out[31:0]; |
assign r_MAC[47:32] = MAC_ADDR1Out[15:0]; |
|
assign r_RxBDNum[7:0] = RX_BD_NUMOut[7:0]; |
assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0]; |
|
|
// Interrupt generation |