OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 332 to Rev 333
    ↔ Reverse comparison
  •

Rev 332 → Rev 333

/trunk/rtl/verilog/eth_wishbone.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.57 2005/02/21 11:35:33 igorm
// Defer indication fixed.
//
// Revision 1.56 2004/04/30 10:30:00 igorm
// Accidently deleted line put back.
//
1828,13 → 1831,13
reg RxAbortSyncb1;
reg RxAbortSyncb2;
 
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 | r_RxEn & ~r_RxEn_q;
 
// Reading the Rx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDRead <=#Tp 1'b1;
RxBDRead <=#Tp 1'b0;
else
if(StartRxBDRead & ~RxReady)
RxBDRead <=#Tp 1'b1;
1878,7 → 1881,7
if(Reset)
RxReady <=#Tp 1'b0;
else
if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q)
RxReady <=#Tp 1'b0;
else
if(RxEn & RxEn_q & RxPointerRead)
/trunk/rtl/verilog/eth_miim.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2005/02/21 12:48:07 igorm
// Warning fixes.
//
// Revision 1.5 2003/05/16 10:08:27 mohor
// Busy was set 2 cycles too late. Reported by Dennis Scott.
//
173,7 → 176,6
reg [6:0] BitCounter; // Bit Counter
 
 
wire MdcFrame; // Frame window for limiting the Mdc
wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
/trunk/rtl/verilog/eth_top.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.51 2005/02/21 11:13:17 igorm
// Defer indication fixed.
//
// Revision 1.50 2004/04/26 15:26:23 igorm
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
// previous update of the core.
366,7 → 369,6
wire TxAbort;
wire TxUnderRun;
wire TxDone;
wire [5:0] CollValid;
 
 
reg WillSendControlFrame_sync1;
440,7 → 442,6
 
//wire DWord;
wire ByteSelected;
wire [3:0] ByteSel;
wire BDAck;
wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
wire [3:0] BDCs; // Buffer descriptor CS
634,8 → 635,6
reg Collision_Tx2;
 
reg RxEnSync; // Synchronized Receive Enable
//reg CarrierSense_Rx1;
//reg RxCarrierSense; // Synchronized CarrierSense (to Rx clock)
reg WillTransmit_q;
reg WillTransmit_q2;
 
746,22 → 745,6
 
 
 
// Carrier sense is synchronized to receive clock.
//always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
//begin
// if(wb_rst_i)
// begin
// CarrierSense_Rx1 <= #Tp 1'h0;
// RxCarrierSense <= #Tp 1'h0;
// end
// else
// begin
// CarrierSense_Rx1 <= #Tp mcrs_pad_i;
// RxCarrierSense <= #Tp CarrierSense_Rx1;
// end
//end
 
 
// Delayed WillTransmit
always @ (posedge mrx_clk_pad_i)
begin
780,7 → 763,6
if(wb_rst_i)
RxEnSync <= #Tp 1'b0;
else
//if(~RxCarrierSense | RxCarrierSense & Transmitting)
if(~mrxdv_pad_i)
RxEnSync <= #Tp r_RxEn;
end
853,7 → 835,6
wire LatchedMRxErr;
reg RxAbort_latch;
reg RxAbort_sync1;
reg RxAbort_sync2;
reg RxAbort_wb;
reg RxAbortRst_sync1;
reg RxAbortRst;
/trunk/rtl/verilog/eth_macstatus.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.16 2005/02/21 10:42:11 igorm
// Defer indication fixed.
//
// Revision 1.15 2003/01/30 13:28:19 tadejm
// Defer indication changed.
//
372,7 → 375,7
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryLimit <=#Tp 4'h0;
RetryLimit <=#Tp 1'h0;
else
if(StartTxDone | StartTxAbort)
RetryLimit <=#Tp MaxCollisionOccured;
/trunk/rtl/verilog/eth_registers.v
41,6 → 41,14
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.28 2004/04/26 15:26:23 igorm
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
// previous update of the core.
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
// register. (thanks to Mathias and Torbjorn)
// - Multicast reception was fixed. Thanks to Ulrich Gries
//
// Revision 1.27 2004/04/26 11:42:17 igorm
// TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.
//
327,7 → 335,6
wire [3:0] HASH0_Wr;
wire [3:0] HASH1_Wr;
wire [2:0] TXCTRL_Wr;
wire [1:0] RXCTRL_Wr;
wire [0:0] TX_BD_NUM_Wr;
 
assign MODER_Wr[0] = Write[0] & MODER_Sel;
372,8 → 379,6
assign TXCTRL_Wr[0] = Write[0] & TXCTRL_Sel;
assign TXCTRL_Wr[1] = Write[1] & TXCTRL_Sel;
assign TXCTRL_Wr[2] = Write[2] & TXCTRL_Sel;
assign RXCTRL_Wr[0] = Write[0] & RXCTRL_Sel;
assign RXCTRL_Wr[1] = Write[1] & RXCTRL_Sel;
assign TX_BD_NUM_Wr[0] = Write[0] & TX_BD_NUM_Sel & (DataIn<='h80);
 
 
399,7 → 404,6
wire [31:0] HASH0Out;
wire [31:0] HASH1Out;
wire [31:0] TXCTRLOut;
wire [31:0] RXCTRLOut;
 
// MODER Register
eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0) MODER_0
834,26 → 838,6
);
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
 
// RXCTRL Register
eth_register #(`ETH_RX_CTRL_WIDTH_0, `ETH_RX_CTRL_DEF_0) RXCTRL_0
(
.DataIn (DataIn[`ETH_RX_CTRL_WIDTH_0 - 1:0]),
.DataOut (RXCTRLOut[`ETH_RX_CTRL_WIDTH_0 - 1:0]),
.Write (RXCTRL_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_RX_CTRL_WIDTH_1, `ETH_RX_CTRL_DEF_1) RXCTRL_1
(
.DataIn (DataIn[`ETH_RX_CTRL_WIDTH_1 + 7:8]),
.DataOut (RXCTRLOut[`ETH_RX_CTRL_WIDTH_1 + 7:8]),
.Write (RXCTRL_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign RXCTRLOut[31:`ETH_RX_CTRL_WIDTH_1 + 8] = 0;
 
 
// Reading data from registers
862,7 → 846,7
PACKETLENOut or COLLCONFOut or CTRLMODEROut or MIIMODEROut or
MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or MIIRX_DATAOut or
MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or TX_BD_NUMOut or
HASH0Out or HASH1Out or TXCTRLOut or RXCTRLOut
HASH0Out or HASH1Out or TXCTRLOut
)
begin
if(Read) // read
889,7 → 873,6
`ETH_HASH0_ADR : DataOut<=HASH0Out;
`ETH_HASH1_ADR : DataOut<=HASH1Out;
`ETH_TX_CTRL_ADR : DataOut<=TXCTRLOut;
`ETH_RX_CTRL_ADR : DataOut<=RXCTRLOut;
 
default: DataOut<=32'h0;
endcase

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.