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Rev 45 → Rev 46

/trunk/rtl/verilog/eth_defines.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.8 2002/02/05 16:44:38 mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still need
98,24 → 101,26
//`define ARTISAN_SDP // Core is going to be implemented in ASIC (using Artisan RAM)
 
 
`define ETH_MODER_ADR 6'h0 // 0x0
`define ETH_INT_SOURCE_ADR 6'h1 // 0x4
`define ETH_INT_MASK_ADR 6'h2 // 0x8
`define ETH_IPGT_ADR 6'h3 // 0xC
`define ETH_IPGR1_ADR 6'h4 // 0x10
`define ETH_IPGR2_ADR 6'h5 // 0x14
`define ETH_PACKETLEN_ADR 6'h6 // 0x18
`define ETH_COLLCONF_ADR 6'h7 // 0x1C
`define ETH_TX_BD_NUM_ADR 6'h8 // 0x20
`define ETH_CTRLMODER_ADR 6'h9 // 0x24
`define ETH_MIIMODER_ADR 6'hA // 0x28
`define ETH_MIICOMMAND_ADR 6'hB // 0x2C
`define ETH_MIIADDRESS_ADR 6'hC // 0x30
`define ETH_MIITX_DATA_ADR 6'hD // 0x34
`define ETH_MIIRX_DATA_ADR 6'hE // 0x38
`define ETH_MIISTATUS_ADR 6'hF // 0x3C
`define ETH_MAC_ADDR0_ADR 6'h10 // 0x40
`define ETH_MAC_ADDR1_ADR 6'h11 // 0x44
`define ETH_MODER_ADR 8'h0 // 0x0
`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
`define ETH_INT_MASK_ADR 8'h2 // 0x8
`define ETH_IPGT_ADR 8'h3 // 0xC
`define ETH_IPGR1_ADR 8'h4 // 0x10
`define ETH_IPGR2_ADR 8'h5 // 0x14
`define ETH_PACKETLEN_ADR 8'h6 // 0x18
`define ETH_COLLCONF_ADR 8'h7 // 0x1C
`define ETH_TX_BD_NUM_ADR 8'h8 // 0x20
`define ETH_CTRLMODER_ADR 8'h9 // 0x24
`define ETH_MIIMODER_ADR 8'hA // 0x28
`define ETH_MIICOMMAND_ADR 8'hB // 0x2C
`define ETH_MIIADDRESS_ADR 8'hC // 0x30
`define ETH_MIITX_DATA_ADR 8'hD // 0x34
`define ETH_MIIRX_DATA_ADR 8'hE // 0x38
`define ETH_MIISTATUS_ADR 8'hF // 0x3C
`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40
`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44
`define ETH_HASH0_ADR 8'h12 // 0x48
`define ETH_HASH1_ADR 8'h13 // 0x4C
 
 
 
136,7 → 141,11
`define ETH_MIISTATUS_DEF 32'h00000000
`define ETH_MAC_ADDR0_DEF 32'h00000000
`define ETH_MAC_ADDR1_DEF 32'h00000000
`define ETH_HASH0_DEF 32'h00000000
`define ETH_HASH1_DEF 32'h00000000
 
 
 
`define ETH_TX_BD_NUM_DEF 8'h80
 
 
/trunk/rtl/verilog/eth_registers.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.6 2001/12/05 15:00:16 mohor
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
// instead of the number of RX descriptors).
98,13 → 101,14
r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
LinkFail, r_MAC, WCtrlDataStart, RStatStart,
UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o
UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
r_HASH0, r_HASH1
);
 
parameter Tp = 1;
 
input [31:0] DataIn;
input [5:0] Address;
input [7:0] Address;
 
input Rw;
input Cs;
174,7 → 178,10
 
output [15:0]r_CtrlData;
 
output [31:0]r_HASH0;
output [31:0]r_HASH1;
 
 
input NValid_stat;
input Busy_stat;
input LinkFail;
212,6 → 219,8
wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR ) & Write;
wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR ) & Write;
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR ) & Write;
wire MAC_HASH0_Wr = (Address == `ETH_HASH0_ADR ) & Write;
wire MAC_HASH1_Wr = (Address == `ETH_HASH1_ADR ) & Write;
 
 
 
233,7 → 242,10
wire [31:0] MAC_ADDR0Out;
wire [31:0] MAC_ADDR1Out;
wire [31:0] TX_BD_NUMOut;
wire [31:0] MAC_HASH0Out;
wire [31:0] MAC_HASH1Out;
 
 
eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF));
eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF));
eth_register #(32) IPGT (.DataIn(DataIn), .DataOut(IPGTOut), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF));
269,7 → 281,10
assign TX_BD_NUMOut[31:8] = 24'h0;
eth_register #(8) TX_BD_NUM (.DataIn(DataIn[7:0]), .DataOut(TX_BD_NUMOut[7:0]), .Write(TX_BD_NUM_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_TX_BD_NUM_DEF));
 
eth_register #(32) MAC_HASH0 (.DataIn(DataIn), .DataOut(MAC_HASH0Out), .Write(MAC_HASH0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH0_DEF));
eth_register #(32) MAC_HASH1 (.DataIn(DataIn), .DataOut(MAC_HASH1Out), .Write(MAC_HASH1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH1_DEF));
 
 
reg LinkFailRegister;
wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read;
reg ResetLinkFailRegister_q1;
299,7 → 314,7
IPGR1Out or IPGR2Out or PACKETLENOut or COLLCONFOut or CTRLMODEROut or
MIIMODEROut or MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or
MIIRX_DATAOut or MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or
TX_BD_NUMOut)
TX_BD_NUMOut or MAC_HASH0Out or MAC_HASH1Out)
begin
if(Read) // read
begin
322,6 → 337,8
`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
`ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
`ETH_HASH0_ADR : DataOut<=MAC_HASH0Out;
`ETH_HASH1_ADR : DataOut<=MAC_HASH1Out;
default: DataOut<=32'h0;
endcase
end
391,6 → 408,8
 
assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
 
assign r_HASH0 = MAC_HASH0Out;
assign r_HASH1 = MAC_HASH1Out;
 
// Interrupt generation
 

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