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https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
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Rev 51 → Rev 52
/trunk/rtl/verilog/eth_rxcounters.v
43,6 → 43,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.2 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
75,7 → 78,9
|
module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble, |
MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24, |
ByteCntEq0, ByteCntEq1, ByteCntEq6, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, |
ByteCntEq0, ByteCntEq1, |
ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6, |
ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, |
ByteCnt |
); |
|
100,7 → 105,12
output [3:0] DlyCrcCnt; // Delayed CRC counter |
output ByteCntEq0; // Byte counter = 0 |
output ByteCntEq1; // Byte counter = 1 |
output ByteCntEq2; // Byte counter = 2 |
output ByteCntEq3; // Byte counter = 3 |
output ByteCntEq4; // Byte counter = 4 |
output ByteCntEq5; // Byte counter = 5 |
output ByteCntEq6; // Byte counter = 6 |
output ByteCntEq7; // Byte counter = 7 |
output ByteCntGreat2; // Byte counter > 2 |
output ByteCntSmall7; // Byte counter < 7 |
output ByteCntMaxFrame; // Byte counter = MaxFL |
142,7 → 152,12
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assign ByteCntEq0 = ByteCnt == 16'h0; |
assign ByteCntEq1 = ByteCnt == 16'h1; |
assign ByteCntEq2 = ByteCnt == 16'h2; |
assign ByteCntEq3 = ByteCnt == 16'h3; |
assign ByteCntEq4 = ByteCnt == 16'h4; |
assign ByteCntEq5 = ByteCnt == 16'h5; |
assign ByteCntEq6 = ByteCnt == 16'h6; |
assign ByteCntEq7 = ByteCnt == 16'h7; |
assign ByteCntGreat2 = ByteCnt > 16'h2; |
assign ByteCntSmall7 = ByteCnt < 16'h7; |
assign ByteCntMax = ByteCnt == 16'hffff; |
/trunk/rtl/verilog/eth_defines.v
101,29 → 101,28
//`define ARTISAN_SDP // Core is going to be implemented in ASIC (using Artisan RAM) |
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`define ETH_MODER_ADR 8'h0 // 0x0 |
`define ETH_INT_SOURCE_ADR 8'h1 // 0x4 |
`define ETH_INT_MASK_ADR 8'h2 // 0x8 |
`define ETH_IPGT_ADR 8'h3 // 0xC |
`define ETH_IPGR1_ADR 8'h4 // 0x10 |
`define ETH_IPGR2_ADR 8'h5 // 0x14 |
`define ETH_PACKETLEN_ADR 8'h6 // 0x18 |
`define ETH_COLLCONF_ADR 8'h7 // 0x1C |
`define ETH_TX_BD_NUM_ADR 8'h8 // 0x20 |
`define ETH_CTRLMODER_ADR 8'h9 // 0x24 |
`define ETH_MIIMODER_ADR 8'hA // 0x28 |
`define ETH_MIICOMMAND_ADR 8'hB // 0x2C |
`define ETH_MIIADDRESS_ADR 8'hC // 0x30 |
`define ETH_MIITX_DATA_ADR 8'hD // 0x34 |
`define ETH_MIIRX_DATA_ADR 8'hE // 0x38 |
`define ETH_MIISTATUS_ADR 8'hF // 0x3C |
`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40 |
`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44 |
`define ETH_HASH0_ADR 8'h12 // 0x48 |
`define ETH_HASH1_ADR 8'h13 // 0x4C |
`define ETH_MODER_ADR 6'h0 // 0x0 |
`define ETH_INT_SOURCE_ADR 6'h1 // 0x4 |
`define ETH_INT_MASK_ADR 6'h2 // 0x8 |
`define ETH_IPGT_ADR 6'h3 // 0xC |
`define ETH_IPGR1_ADR 6'h4 // 0x10 |
`define ETH_IPGR2_ADR 6'h5 // 0x14 |
`define ETH_PACKETLEN_ADR 6'h6 // 0x18 |
`define ETH_COLLCONF_ADR 6'h7 // 0x1C |
`define ETH_TX_BD_NUM_ADR 6'h8 // 0x20 |
`define ETH_CTRLMODER_ADR 6'h9 // 0x24 |
`define ETH_MIIMODER_ADR 6'hA // 0x28 |
`define ETH_MIICOMMAND_ADR 6'hB // 0x2C |
`define ETH_MIIADDRESS_ADR 6'hC // 0x30 |
`define ETH_MIITX_DATA_ADR 6'hD // 0x34 |
`define ETH_MIIRX_DATA_ADR 6'hE // 0x38 |
`define ETH_MIISTATUS_ADR 6'hF // 0x3C |
`define ETH_MAC_ADDR0_ADR 6'h10 // 0x40 |
`define ETH_MAC_ADDR1_ADR 6'h11 // 0x44 |
`define ETH_HASH0_ADR 6'h12 // 0x48 |
`define ETH_HASH1_ADR 6'h13 // 0x4C |
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`define ETH_MODER_DEF 32'h0000A800 |
`define ETH_INT_SOURCE_DEF 32'h00000000 |
`define ETH_INT_MASK_DEF 32'h00000000 |
144,8 → 143,6
`define ETH_HASH0_DEF 32'h00000000 |
`define ETH_HASH1_DEF 32'h00000000 |
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`define ETH_TX_BD_NUM_DEF 8'h80 |
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160,3 → 157,6
`define RX_FIFO_DEPTH 8 |
`define RX_FIFO_DATA_WIDTH 32 |
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`define MULTICAST_XFR 0 |
`define UNICAST_XFR 1 |
`define BROADCAST_XFR 2 |
/trunk/rtl/verilog/eth_top.v
41,9 → 41,6
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.12 2002/02/11 09:18:22 mohor |
// Tx status is written back to the BD. |
// |
// Revision 1.11 2002/02/08 16:21:54 mohor |
// Rx status is written back to the BD. |
// |
271,7 → 268,8
wire ReceivedPacketTooBig; // Received packet is too big |
wire [47:0] r_MAC; // MAC address |
wire LoadRxStatus; // Rx status was loaded |
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wire [31:0] r_HASH0; // HASH table, lower 4 bytes |
wire [31:0] r_HASH1; // HASH table, upper 4 bytes |
wire [7:0] r_TxBDNum; // Receive buffer descriptor number |
wire [6:0] r_IPGT; // |
wire [6:0] r_IPGR1; // |
320,8 → 318,8
.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn), |
.r_DlyCrcEn(r_DlyCrcEn), .r_Rst(r_Rst), .r_FullD(r_FullD), |
.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck), |
.r_IFG(r_IFG), .r_Pro(), .r_Iam(), |
.r_Bro(), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn), |
.r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(), |
.r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn), |
.r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxF_IRQ(RxF_IRQ), |
.RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ), |
.r_IPGT(r_IPGT), |
335,7 → 333,7
.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart), |
.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd), |
.r_TxBDNum(r_TxBDNum), .TX_BD_NUM_Wr(TX_BD_NUM_Wr), .int_o(int_o), |
.r_HASH0(), .r_HASH1() |
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1) |
); |
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358,16 → 356,7
wire InvalidSymbol; |
wire LatchedCrcError; |
wire RxLateCollision; |
wire [3:0] RetryCntLatched; |
wire [3:0] RetryCnt; |
wire StartTxDone; |
wire StartTxAbort; |
wire MaxCollisionOccured; |
wire RetryLimit; |
wire StatePreamble; |
wire [1:0] StateData; |
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// Connecting MACControl |
eth_maccontrol maccontrol1 |
( |
434,10 → 423,7
.MaxFL(r_MaxFL), .MTxEn(mtxen_pad_o), .MTxD(mtxd_pad_o), |
.MTxErr(mtxerr_pad_o), .TxUsedData(TxUsedDataIn), .TxDone(TxDoneIn), |
.TxRetry(TxRetry), .TxAbort(TxAbortIn), .WillTransmit(WillTransmit), |
.ResetCollision(ResetCollision), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone), |
.StartTxAbort(StartTxAbort), .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision), |
.StartDefer(StartDefer), .StatePreamble(StatePreamble), .StateData(StateData) |
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.ResetCollision(ResetCollision) |
); |
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467,7 → 453,9
.Broadcast(), .Multicast(), .ByteCnt(RxByteCnt), |
.ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame), |
.CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble), |
.StateSFD(RxStateSFD), .StateData(RxStateData) |
.StateSFD(RxStateSFD), .StateData(RxStateData), |
.MAC(r_MAC), .r_Pro(r_Pro), .r_Bro(r_Bro), // ditt |
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1) |
); |
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585,7 → 573,7
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//TX |
.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), |
.TxUsedData(TxUsedData), .TxData(TxData), |
.TxUsedData(TxUsedData), .TxData(TxData), .StatusIzTxEthMACModula(16'h0), |
.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun), |
.TxDone(TxDone), .TPauseRq(TPauseRq), .TxPauseTV(TxPauseTV), |
.PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad), .WillSendControlFrame(WillSendControlFrame), |
608,9 → 596,7
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.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt), |
.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble), |
.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched), |
.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched), |
.CarrierSenseLost(CarrierSenseLost) |
.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus) |
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); |
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630,14 → 616,8
.CollValid(r_CollValid), .RxLateCollision(RxLateCollision), .r_RecSmall(r_RecSmall), |
.r_MinFL(r_MinFL), .r_MaxFL(r_MaxFL), .ShortFrame(ShortFrame), |
.DribbleNibble(DribbleNibble), .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn), |
.LoadRxStatus(LoadRxStatus), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone), |
.StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i), |
.MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision), |
.LateCollLatched(LateCollLatched), .StartDefer(StartDefer), .DeferLatched(DeferLatched), |
.TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData), |
.CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn) |
.LoadRxStatus(LoadRxStatus) |
); |
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endmodule |
/trunk/rtl/verilog/eth_registers.v
102,7 → 102,7
r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat, |
LinkFail, r_MAC, WCtrlDataStart, RStatStart, |
UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o, |
r_HASH0, r_HASH1 |
r_HASH0, r_HASH1 |
); |
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parameter Tp = 1; |
142,6 → 142,8
output r_NoPre; |
output r_TxEn; |
output r_RxEn; |
output [31:0] r_HASH0; |
output [31:0] r_HASH1; |
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input TxB_IRQ; |
input TxE_IRQ; |
178,10 → 180,7
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output [15:0]r_CtrlData; |
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output [31:0]r_HASH0; |
output [31:0]r_HASH1; |
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input NValid_stat; |
input Busy_stat; |
input LinkFail; |
218,9 → 217,9
wire MIISTATUS_Wr = (Address == `ETH_MIISTATUS_ADR ) & Write; |
wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR ) & Write; |
wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR ) & Write; |
wire HASH0_Wr = (Address == `ETH_HASH0_ADR ) & Write; |
wire HASH1_Wr = (Address == `ETH_HASH1_ADR ) & Write; |
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR ) & Write; |
wire MAC_HASH0_Wr = (Address == `ETH_HASH0_ADR ) & Write; |
wire MAC_HASH1_Wr = (Address == `ETH_HASH1_ADR ) & Write; |
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242,10 → 241,11
wire [31:0] MAC_ADDR0Out; |
wire [31:0] MAC_ADDR1Out; |
wire [31:0] TX_BD_NUMOut; |
wire [31:0] MAC_HASH0Out; |
wire [31:0] MAC_HASH1Out; |
wire [31:0] HASH0Out; |
wire [31:0] HASH1Out; |
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eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF)); |
eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF)); |
eth_register #(32) IPGT (.DataIn(DataIn), .DataOut(IPGTOut), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF)); |
253,7 → 253,11
eth_register #(32) IPGR2 (.DataIn(DataIn), .DataOut(IPGR2Out), .Write(IPGR2_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR2_DEF)); |
eth_register #(32) PACKETLEN (.DataIn(DataIn), .DataOut(PACKETLENOut), .Write(PACKETLEN_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_PACKETLEN_DEF)); |
eth_register #(32) COLLCONF (.DataIn(DataIn), .DataOut(COLLCONFOut), .Write(COLLCONF_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_COLLCONF_DEF)); |
eth_register #(32) RXHASH0 (.DataIn(DataIn), .DataOut(HASH0Out), .Write(HASH0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH0_DEF)); |
eth_register #(32) RXHASH1 (.DataIn(DataIn), .DataOut(HASH1Out), .Write(HASH1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH1_DEF)); |
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// CTRLMODER registers |
wire [31:0] DefaultCtrlModer = `ETH_CTRLMODER_DEF; |
assign CTRLMODEROut[31:3] = 29'h0; |
281,10 → 285,7
assign TX_BD_NUMOut[31:8] = 24'h0; |
eth_register #(8) TX_BD_NUM (.DataIn(DataIn[7:0]), .DataOut(TX_BD_NUMOut[7:0]), .Write(TX_BD_NUM_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_TX_BD_NUM_DEF)); |
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eth_register #(32) MAC_HASH0 (.DataIn(DataIn), .DataOut(MAC_HASH0Out), .Write(MAC_HASH0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH0_DEF)); |
eth_register #(32) MAC_HASH1 (.DataIn(DataIn), .DataOut(MAC_HASH1Out), .Write(MAC_HASH1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH1_DEF)); |
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reg LinkFailRegister; |
wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read; |
reg ResetLinkFailRegister_q1; |
314,7 → 315,7
IPGR1Out or IPGR2Out or PACKETLENOut or COLLCONFOut or CTRLMODEROut or |
MIIMODEROut or MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or |
MIIRX_DATAOut or MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or |
TX_BD_NUMOut or MAC_HASH0Out or MAC_HASH1Out) |
TX_BD_NUMOut or HASH0Out or HASH1Out) |
begin |
if(Read) // read |
begin |
337,8 → 338,8
`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out; |
`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out; |
`ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut; |
`ETH_HASH0_ADR : DataOut<=MAC_HASH0Out; |
`ETH_HASH1_ADR : DataOut<=MAC_HASH1Out; |
`ETH_HASH0_ADR : DataOut<=HASH0Out; |
`ETH_HASH1_ADR : DataOut<=HASH1Out; |
default: DataOut<=32'h0; |
endcase |
end |
405,11 → 406,11
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assign r_MAC[31:0] = MAC_ADDR0Out[31:0]; |
assign r_MAC[47:32] = MAC_ADDR1Out[15:0]; |
assign r_HASH1[31:0] = HASH1Out; |
assign r_HASH0[31:0] = HASH0Out; |
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assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0]; |
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assign r_HASH0 = MAC_HASH0Out; |
assign r_HASH1 = MAC_HASH1Out; |
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// Interrupt generation |
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