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    from Rev 53 to Rev 54
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Rev 53 → Rev 54

/trunk/rtl/verilog/eth_wishbone.v
41,9 → 41,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/02/11 09:18:22 mohor
// Tx status is written back to the BD.
//
// Revision 1.5 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
97,7 → 94,7
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
 
//TX
MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData, StatusIzTxEthMACModula,
TxRetry, TxAbort, TxUnderRun, TxDone, TPauseRq, TxPauseTV, PerPacketCrcEn,
PerPacketPad,
 
112,12 → 109,8
// Interrupts
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ,
// Rx Status
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
ReceivedPacketTooBig, RxLength, LoadRxStatus,
// Tx Status
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
ReceivedPacketTooBig, RxLength, LoadRxStatus
 
);
 
149,7 → 142,7
 
input Reset; // Reset signal
 
// Rx Status signals
// Status signals
input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode
input LatchedCrcError; // CRC error
input RxLateCollision; // Late collision occured while receiving frame
159,16 → 152,10
input [15:0] RxLength; // Length of the incoming frame
input LoadRxStatus; // Rx status was loaded
 
// Tx Status signals
input [3:0] RetryCntLatched; // Latched Retry Counter
input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made)
input LateCollLatched; // Late collision occured
input DeferLatched; // Defer indication (Frame was defered before sucessfully sent)
input CarrierSenseLost; // Carrier Sense was lost during the frame transmission
 
// Tx
input MTxClk; // Transmit clock (from PHY)
input TxUsedData; // Transmit packet used data
input [15:0] StatusIzTxEthMACModula;
input TxRetry; // Transmit packet retry
input TxAbort; // Transmit packet abort
input TxDone; // Transmission ended
211,7 → 198,6
reg [7:0] TxData;
 
reg TxUnderRun;
reg TxUnderRun_wb;
 
reg TxBDRead;
wire TxStatusWrite;
219,10 → 205,9
reg [1:0] TxValidBytesLatched;
 
reg [15:0] TxLength;
reg [15:0] LatchedTxLength;
reg [14:11] TxStatus;
reg [15:0] TxStatus;
 
reg [14:13] RxStatus;
reg [14:13] RxStatusOld;
 
reg TxStartFrm_wb;
reg TxRetry_wb;
270,7 → 255,6
reg [15:0] LatchedRxLength;
 
reg ShiftEnded;
reg RxOverrun;
 
reg BDWrite; // BD Write Enable for access from WISHBONE side
reg BDRead; // BD Read access from WISHBONE side
303,8 → 287,8
 
reg temp_ack;
 
wire [6:0] RxStatusIn;
reg [6:0] RxStatusInLatched;
wire [5:0] RxStatusIn;
reg [5:0] RxStatusInLatched;
 
`ifdef ETH_REGISTERED_OUTPUTS
reg temp_ack2;
323,6 → 307,7
wire [31:0] ram_do;
 
wire StartTxPointerRead;
wire ResetTxPointerRead;
reg TxPointerRead;
reg TxEn_needed;
reg RxEn_needed;
590,10 → 575,10
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStatus <=#Tp 4'h0;
TxStatus <=#Tp 15'h0;
else
if(TxEn & TxEn_q & TxBDRead)
TxStatus <=#Tp ram_do[14:11];
TxStatus <=#Tp ram_do[15:0];
end
 
reg ReadTxDataFromMemory;
629,16 → 614,6
end
end
 
//Latching length from the buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
LatchedTxLength <=#Tp 16'h0;
else
if(TxEn & TxEn_q & TxBDRead)
LatchedTxLength <=#Tp ram_do[31:16];
end
 
assign TxLengthEq0 = TxLength == 0;
assign TxLengthLt4 = TxLength < 4;
 
805,7 → 780,7
 
eth_fifo #(`TX_FIFO_DATA_WIDTH, `TX_FIFO_DEPTH, `TX_FIFO_CNT_WIDTH)
tx_fifo (.data_in(m_wb_dat_i), .data_out(TxData_wb), .clk(WB_CLK_I),
.reset(Reset), .write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb),
.reset(Reset), .write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb),
.clear(TxFifoClear), .full(TxBufferFull), .almost_full(TxBufferAlmostFull),
.almost_empty(TxBufferAlmostEmpty), .empty(TxBufferEmpty));
 
945,16 → 920,53
end
 
 
// Bit 14 is used as a wrap bit. When active it indicates the last buffer descriptor in a row. After
// using this descriptor, first BD will be used again.
 
// TX
// bit 15 od tx je ready
// bit 14 od tx je interrupt (Tx buffer ali tx error bit se postavi v interrupt registru, ko se ta buffer odda)
// bit 13 od tx je wrap
// bit 12 od tx je pad
// bit 11 od tx je crc
// bit 10 od tx je last (crc se doda le ce je bit 11 in hkrati bit 10)
// bit 9 od tx je pause request (control frame)
// Vsi zgornji biti gredo ven, spodnji biti (od 8 do 0) pa so statusni in se vpisejo po koncu oddajanja
// bit 8 od tx je defer indication
// bit 7 od tx je late collision
// bit 6 od tx je retransmittion limit
// bit 5 od tx je underrun
// bit 4 od tx je carrier sense lost
// bit [3:0] od tx je retry count
 
//assign TxBDReady = TxStatus[15]; // already used
assign TxIRQEn = TxStatus[14];
assign WrapTxStatusBit = TxStatus[13];
assign PerPacketPad = TxStatus[12];
assign PerPacketCrcEn = TxStatus[11];
assign WrapTxStatusBit = TxStatus[13]; // ok povezan
assign PerPacketPad = TxStatus[12]; // ok povezan
assign PerPacketCrcEn = TxStatus[11] & TxStatus[10]; // When last is also set // ok povezan
//assign TxPauseRq = TxStatus[9]; // already used Ta gre ven, ker bo stvar izvedena preko registrov
 
 
assign WrapRxStatusBit = RxStatus[13];
 
// RX
// bit 15 od rx je empty
// bit 14 od rx je interrupt (Rx buffer ali rx frame received se postavi v interrupt registru, ko se ta buffer zapre)
// bit 13 od rx je wrap
// bit 12 od rx je reserved
// bit 11 od rx je reserved
// bit 10 od rx je last (crc se doda le ce je bit 11 in hkrati bit 10)
// bit 9 od rx je pause request (control frame)
// Vsi zgornji biti gredo ven, spodnji biti (od 8 do 0) pa so statusni in se vpisejo po koncu oddajanja
// bit 8 od rx je defer indication
// bit 7 od rx je late collision
// bit 6 od rx je retransmittion limit
// bit 5 od rx je underrun
// bit 4 od rx je carrier sense lost
// bit [3:0] od rx je retry count
 
assign WrapRxStatusBit = RxStatusOld[13];
 
 
// Temporary Tx and Rx buffer descriptor address
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum) | // Using first Rx BD
985,12 → 997,10
RxBDAddress <=#Tp TempRxBDAddress;
end
 
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatusOld, 7'h0, RxStatusInLatched}; // tu dopolni, da se bo vpisoval status
assign TxBDDataIn = {32'h004380ef}; // tu dopolni, da se bo vpisoval status
 
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 6'h0, RxStatusInLatched};
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
 
 
// Signals used for various purposes
assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
1119,27 → 1129,13
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxUnderRun_wb <=#Tp 1'b0;
TxUnderRun <=#Tp 1'b0;
else
if(TxAbortPulse)
TxUnderRun_wb <=#Tp 1'b0;
TxUnderRun <=#Tp 1'b0;
else
if(TxBufferEmpty & ReadTxDataFromFifo_wb)
TxUnderRun_wb <=#Tp 1'b1;
end
 
 
// Tx under run
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUnderRun <=#Tp 1'b0;
else
if(TxUnderRun_wb)
TxUnderRun <=#Tp 1'b1;
else
if(BlockingTxStatusWrite)
TxUnderRun <=#Tp 1'b0;
end
 
 
1316,10 → 1312,10
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxStatus <=#Tp 2'h0;
RxStatusOld <=#Tp 2'h0;
else
if(RxEn & RxEn_q & RxBDRead)
RxStatus <=#Tp ram_do[14:13];
RxStatusOld <=#Tp ram_do[14:13];
end
 
 
1704,8 → 1700,9
end
 
 
assign RxStatusIn = {RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
 
assign RxStatusIn = {InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
 
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
1716,54 → 1713,6
end
 
 
// Rx overrun
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxOverrun <=#Tp 1'b0;
else
if(RxStatusWrite)
RxOverrun <=#Tp 1'b0;
else
if(RxBufferFull & WriteRxDataToFifo_wb)
RxOverrun <=#Tp 1'b1;
end
 
// TX
// bit 15 od tx je ready
// bit 14 od tx je interrupt (Tx buffer ali tx error bit se postavi v interrupt registru, ko se ta buffer odda)
// bit 13 od tx je wrap
// bit 12 od tx je pad
// bit 11 od tx je crc
// bit 10 od tx je last (crc se doda le ce je bit 11 in hkrati bit 10)
// bit 9 od tx je pause request (control frame)
// Vsi zgornji biti gredo ven, spodnji biti (od 8 do 0) pa so statusni in se vpisejo po koncu oddajanja
// bit 8 od tx je defer indication done
// bit 7 od tx je late collision done
// bit 6 od tx je retransmittion limit done
// bit 5 od tx je underrun done
// bit 4 od tx je carrier sense lost
// bit [3:0] od tx je retry count done
 
 
// RX
// bit 15 od rx je empty
// bit 14 od rx je interrupt (Rx buffer ali rx frame received se postavi v interrupt registru, ko se ta buffer zapre)
// bit 13 od rx je wrap
// bit 12 od rx je reserved
// bit 11 od rx je reserved
// bit 10 od rx je reserved
// bit 9 od rx je reserved
// bit 8 od rx je reserved
// bit 7 od rx je reserved
// bit 6 od rx je RxOverrun
// bit 5 od rx je InvalidSymbol
// bit 4 od rx je DribbleNibble
// bit 3 od rx je ReceivedPacketTooBig
// bit 2 od rx je ShortFrame
// bit 1 od rx je LatchedCrcError
// bit 0 od rx je RxLateCollision
 
endmodule
 

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