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URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 57 to Rev 58
    Reverse comparison

Rev 57 → Rev 58

/trunk/rtl/verilog/eth_rxethmac.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/02/14 20:48:43 billditt
// Addition of new module eth_addrcheck.v
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
81,7 → 84,7
RxData, RxValid, RxStartFrm, RxEndFrm, CrcHash, CrcHashGood, Broadcast,
Multicast, ByteCnt, ByteCntEq0, ByteCntGreat2, ByteCntMaxFrame,
CrcError, StateIdle, StatePreamble, StateSFD, StateData,
MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort
MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort
);
 
parameter Tp = 1;
179,10 → 182,9
.StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
.DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
.HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
.ByteCntEq1(ByteCntEq1),
.ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
.ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7),.ByteCntGreat2(ByteCntGreat2),
.ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
.ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
.ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
.ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
.ByteCnt(ByteCnt)
);
189,15 → 191,16
 
// Rx Address Check
 
eth_rxaddrcheck rxaddrcheck1(.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData),
.Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro),
.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
.ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
.HASH0(r_HASH0), .HASH1(r_HASH1),
.CrcHash(CrcHash[5:0]), .CrcHashGood(CrcHashGood),.StateData(StateData),
.Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort),
.RxEndFrm(RxEndFrm)
);
eth_rxaddrcheck rxaddrcheck1
(.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData),
.Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro),
.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
.ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
.HASH0(r_HASH0), .HASH1(r_HASH1),
.CrcHash(CrcHash[5:0]), .CrcHashGood(CrcHashGood),.StateData(StateData),
.Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort),
.RxEndFrm(RxEndFrm)
);
 
 
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
212,7 → 215,7
// Connecting module Crc
eth_crc crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
.Crc(Crc), .CrcError(CrcError)
);
);
 
 
 
273,9 → 276,9
else
if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
Broadcast <= #Tp 1'b1;
else
if(RxAbort | RxEndFrm)
Broadcast <= #Tp 1'b0;
else
if(RxAbort | RxEndFrm)
Broadcast <= #Tp 1'b0;
end
end
 
291,8 → 294,8
else
if(StateData[0] & ByteCntEq1 & LatchedByte == 8'h01)
Multicast <= #Tp 1'b1;
else if(RxAbort | RxEndFrm)
Multicast <= #Tp 1'b0;
else if(RxAbort | RxEndFrm)
Multicast <= #Tp 1'b0;
end
end
 

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