OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 64 to Rev 65
    Reverse comparison

Rev 64 → Rev 65

/trunk/rtl/verilog/eth_rxethmac.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2002/02/15 13:44:28 mohor
// RxAbort is an output. No need to have is declared as wire.
//
// Revision 1.6 2002/02/15 11:17:48 mohor
// File format changed.
//
84,9 → 87,8
 
 
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
RxData, RxValid, RxStartFrm, RxEndFrm, CrcHash, CrcHashGood, Broadcast,
Multicast, ByteCnt, ByteCntEq0, ByteCntGreat2, ByteCntMaxFrame,
CrcError, StateIdle, StatePreamble, StateSFD, StateData,
RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort
);
 
112,10 → 114,6
output RxValid;
output RxStartFrm;
output RxEndFrm;
output [8:0] CrcHash;
output CrcHashGood;
output Broadcast;
output Multicast;
output [15:0] ByteCnt;
output ByteCntEq0;
output ByteCntGreat2;
/trunk/rtl/verilog/eth_rxaddrcheck.v
52,12 → 52,12
`include "timescale.v"
 
 
module eth_rxaddrcheck( MRxClk, Reset, RxData, Broadcast ,r_Bro ,r_Pro,
ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
ByteCntEq6, ByteCntEq7, HASH0, HASH1,
CrcHash, CrcHashGood, StateData, RxEndFrm,
Multicast, MAC, RxAbort
);
module eth_rxaddrcheck(MRxClk, Reset, RxData, Broadcast ,r_Bro ,r_Pro,
ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
ByteCntEq6, ByteCntEq7, HASH0, HASH1,
CrcHash, CrcHashGood, StateData, RxEndFrm,
Multicast, MAC, RxAbort
);
 
parameter Tp = 1;
 
92,84 → 92,79
wire ByteCntEq5;
wire RxAddressInvalid;
wire RxCheckEn;
reg [31:0] IntHash;
wire HashBit;
wire [31:0] IntHash;
reg [7:0] ByteHash;
reg MulticastOK;
reg UnicastOK;
reg RxAbort;
reg CrcHashGood_d; // delay HashGood by one cycle
reg HashBit;
assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK);
assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK);
assign BroadcastOK = Broadcast;
assign BroadcastOK = (Broadcast & ~r_Bro ) | r_Pro;
assign RxCheckEn = | StateData;
assign RxCheckEn = | StateData;
// Address Error Reported at end of address cycle
// RxAbort clears after one cycle
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbort <= #Tp 1'b0;
else if( CrcHashGood_d & RxAddressInvalid & RxCheckEn)
RxAbort <= #Tp 1'b1;
else
RxAbort <= #Tp 1'b0;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbort <= #Tp 1'b0;
else if(CrcHashGood_d & RxAddressInvalid & ~r_Pro & RxCheckEn)
RxAbort <= #Tp 1'b1;
else
RxAbort <= #Tp 1'b0;
end
// Hash Address Check, Multicast
// Hash Address Check, Multicast
 
 
// delay CrcHashGood by 1 cycle
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
CrcHashGood_d <= #Tp 1'b0;
else
CrcHashGood_d <= #Tp CrcHashGood;
end
begin
if(Reset)
CrcHashGood_d <= #Tp 1'b0;
else
CrcHashGood_d <= #Tp CrcHashGood;
end
 
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
MulticastOK <= #Tp 1'b0;
else if (RxEndFrm | RxAbort)
MulticastOK <= #Tp 1'b0;
else if(CrcHashGood & Multicast)
MulticastOK <= #Tp HashBit;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
MulticastOK <= #Tp 1'b0;
else if(RxEndFrm | RxAbort)
MulticastOK <= #Tp 1'b0;
else if(CrcHashGood & Multicast)
MulticastOK <= #Tp HashBit;
end
// Address Detection (unicast)
// start with ByteCntEq2 due to delay of addres from RxData
// Address Detection (unicast)
// start with ByteCntEq2 due to delay of addres from RxData
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
UnicastOK <= #Tp 1'b0;
else
if( RxCheckEn & ByteCntEq2)
if(RxCheckEn & ByteCntEq2)
UnicastOK <= #Tp RxData[7:0] == MAC[7:0];
else
if( RxCheckEn & ByteCntEq3)
if(RxCheckEn & ByteCntEq3)
UnicastOK <= #Tp ( RxData[7:0] == MAC[15:8]) & UnicastOK;
else
if( RxCheckEn & ByteCntEq4)
if(RxCheckEn & ByteCntEq4)
UnicastOK <= #Tp ( RxData[7:0] == MAC[23:16]) & UnicastOK;
else
if( RxCheckEn & ByteCntEq5)
if(RxCheckEn & ByteCntEq5)
UnicastOK <= #Tp ( RxData[7:0] == MAC[31:24]) & UnicastOK;
else
if( RxCheckEn & ByteCntEq6)
if(RxCheckEn & ByteCntEq6)
UnicastOK <= #Tp ( RxData[7:0] == MAC[39:32]) & UnicastOK;
else
if( RxCheckEn & ByteCntEq7)
if(RxCheckEn & ByteCntEq7)
UnicastOK <= #Tp ( RxData[7:0] == MAC[47:40]) & UnicastOK;
else
if(RxEndFrm | RxAbort)
176,37 → 171,19
UnicastOK <= #Tp 1'b0;
end
always@(HASH0 or HASH1 or CrcHash[5])
begin
if (CrcHash[5])
IntHash = HASH1;
else
IntHash = HASH0;
end
always@(CrcHash or IntHash)
begin
case(CrcHash[4:3])
2'b00: ByteHash = IntHash[7:0];
2'b01: ByteHash = IntHash[15:8];
2'b10: ByteHash = IntHash[23:16];
2'b11: ByteHash = IntHash[31:24];
endcase
end
always@(CrcHash or ByteHash)
begin
case(CrcHash[2:0])
3'h0: HashBit = ByteHash[0];
3'h1: HashBit = ByteHash[1];
3'h2: HashBit = ByteHash[2];
3'h3: HashBit = ByteHash[3];
3'h4: HashBit = ByteHash[4];
3'h5: HashBit = ByteHash[5];
3'h6: HashBit = ByteHash[6];
3'h7: HashBit = ByteHash[7];
endcase
end
assign IntHash = (CrcHash[5])? HASH1 : HASH0;
always@(CrcHash or IntHash)
begin
case(CrcHash[4:3])
2'b00: ByteHash = IntHash[7:0];
2'b01: ByteHash = IntHash[15:8];
2'b10: ByteHash = IntHash[23:16];
2'b11: ByteHash = IntHash[31:24];
endcase
end
assign HashBit = ByteHash[CrcHash[2:0]];
 
endmodule
 
endmodule
/trunk/rtl/verilog/eth_top.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.16 2002/02/15 13:49:39 mohor
// RxAbort is connected differently.
//
// Revision 1.15 2002/02/15 11:38:26 mohor
// Changes that were lost when updating from 1.11 to 1.14 fixed.
//
470,8 → 473,7
.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(r_Rst),
.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
.RxEndFrm(RxEndFrm), .CrcHash(), .CrcHashGood(),
.Broadcast(), .Multicast(), .ByteCnt(RxByteCnt),
.RxEndFrm(RxEndFrm), .ByteCnt(RxByteCnt),
.ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame),
.CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble),
.StateSFD(RxStateSFD), .StateData(RxStateData),

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.