OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 66 to Rev 67
    Reverse comparison

Rev 66 → Rev 67

/trunk/bench/verilog/tb_eth_top.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10 2002/02/16 07:22:15 mohor
// Testbench fixed, code simplified, unused signals removed.
//
// Revision 1.9 2002/02/14 20:14:38 billditt
// Added separate tests for Multicast, Unicast, Broadcast
//
113,7 → 116,7
wire WB_ERR_O;
reg [1:0] WB_ACK_I;
 
`ifdef WISHBONE_DMA
`ifdef EXTERNAL_DMA
wire [1:0] WB_REQ_O;
wire [1:0] WB_ND_O;
wire WB_RD_O;
154,7 → 157,7
reg [9:0] TxBDIndex;
reg [9:0] RxBDIndex;
 
`ifdef WISHBONE_DMA
`ifdef EXTERNAL_DMA
`else
integer mcd1;
integer mcd2;
171,7 → 174,7
.wb_adr_i(WB_ADR_I[11:2]), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I), .wb_cyc_i(WB_CYC_I),
.wb_stb_i(WB_STB_I), .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O), .wb_ack_i(WB_ACK_I),
`ifdef WISHBONE_DMA
`ifdef EXTERNAL_DMA
.wb_req_o(WB_REQ_O), .wb_nd_o(WB_ND_O), .wb_rd_o(WB_RD_O),
`else
// WISHBONE master
209,7 → 212,7
WB_CYC_I = 1'b0;
WB_STB_I = 1'b0;
 
`ifdef WISHBONE_DMA
`ifdef EXTERNAL_DMA
WB_ACK_I = 2'h0;
`else
m_wb_ack_i = 0;
233,7 → 236,7
// Reset pulse
initial
begin
`ifdef WISHBONE_DMA
`ifdef EXTERNAL_DMA
`else
mcd1 = $fopen("ethernet_tx.log");
mcd2 = $fopen("ethernet_rx.log");
272,7 → 275,7
// #16 forever #250 MRxClk = ~MRxClk;
end
 
`ifdef WISHBONE_DMA
`ifdef EXTERNAL_DMA
initial
begin
wait(StartTB); // Start of testbench
673,7 → 676,7
end
endtask
 
`else // No WISHBONE_DMA
`else // No EXTERNAL_DMA
 
initial
begin
/trunk/rtl/verilog/eth_defines.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12 2002/02/15 10:58:31 mohor
// Changed that were lost with last update put back to the file.
//
// Revision 1.11 2002/02/14 20:19:41 billditt
// Modified for Address Checking,
// addition of eth_addrcheck.v
98,7 → 101,7
//
 
 
//`define WISHBONE_DMA // Using DMA
//`define EXTERNAL_DMA // Using DMA
 
 
// Selection of the used memory
/trunk/rtl/verilog/eth_top.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.17 2002/02/16 07:15:27 mohor
// Testbench fixed, code simplified, unused signals removed.
//
// Revision 1.16 2002/02/15 13:49:39 mohor
// RxAbort is connected differently.
//
128,7 → 131,7
wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
wb_ack_i,
 
`ifdef WISHBONE_DMA
`ifdef EXTERNAL_DMA
wb_req_o, wb_nd_o, wb_rd_o,
`else
// WISHBONE master
170,7 → 173,7
input wb_stb_i; // WISHBONE strobe input
output wb_ack_o; // WISHBONE acknowledge output
 
`ifdef WISHBONE_DMA
`ifdef EXTERNAL_DMA
// DMA
output [1:0] wb_req_o; // DMA request output
output [1:0] wb_nd_o; // DMA force new descriptor output
567,7 → 570,7
 
 
// Connecting WishboneDMA module
`ifdef WISHBONE_DMA
`ifdef EXTERNAL_DMA
eth_wishbonedma wishbone
`else
eth_wishbone wishbone
582,7 → 585,7
 
.Reset(wb_rst_i),
 
`ifdef WISHBONE_DMA
`ifdef EXTERNAL_DMA
.WB_REQ_O(wb_req_o), .WB_ND_O(wb_nd_o), .WB_RD_O(wb_rd_o),
.WB_ACK_I(wb_ack_i),
`else
612,7 → 615,7
.Busy_IRQ(Busy_IRQ), .RxF_IRQ(RxF_IRQ), .RxB_IRQ(RxB_IRQ),
.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
 
`ifdef WISHBONE_DMA
`ifdef EXTERNAL_DMA
`else
.RxAbort(RxAbort),
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.