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URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

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  • This comparison shows the changes necessary to convert path
    /ethmac/trunk/rtl/verilog
    from Rev 354 to Rev 355
    Reverse comparison

Rev 354 → Rev 355

/eth_shiftreg.v
116,12 → 116,14
begin
if(|ByteSelect)
begin
/* verilator lint_off CASEINCOMPLETE */
case (ByteSelect[3:0]) // synopsys parallel_case full_case
4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};
4'h4 : ShiftReg[7:0] <= CtrlData[15:8];
4'h8 : ShiftReg[7:0] <= CtrlData[7:0];
endcase
endcase // case (ByteSelect[3:0])
/* verilator lint_on CASEINCOMPLETE */
end
else
begin
/eth_wishbone.v
555,7 → 555,7
reg RxEn_needed;
 
wire StartRxPointerRead;
reg RxPointerRead;
reg RxPointerRead;
 
// RX shift ending signals
reg ShiftEnded_rck;
749,6 → 749,7
else
begin
// Switching between three stages depends on enable signals
/* verilator lint_off CASEINCOMPLETE */ // JB
case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
5'b100_10, 5'b100_11 :
begin
813,6 → 814,7
BDRead <= (|BDCs) & ~WB_WE_I;
end
endcase
/* verilator lint_on CASEINCOMPLETE */
end
end
 

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