URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/ethmac/trunk/rtl
- from Rev 359 to Rev 360
- ↔ Reverse comparison
Rev 359 → Rev 360
/verilog/eth_wishbone.v
306,6 → 306,10
mbist_ctrl_i // bist chain shift control |
`endif |
|
`ifdef WISHBONE_DEBUG |
, |
dbg_dat0 |
`endif |
|
|
); |
420,6 → 424,11
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control |
`endif |
|
`ifdef WISHBONE_DEBUG |
output [31:0] dbg_dat0; |
`endif |
|
|
reg TxB_IRQ; |
reg TxE_IRQ; |
reg RxB_IRQ; |
2654,7 → 2663,36
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3; |
|
|
|
// Assign the debug output |
`ifdef WISHBONE_DEBUG |
// Top byte, burst progress counters |
assign dbg_dat0[31] = 0; |
assign dbg_dat0[30:28] = rx_burst_cnt; |
assign dbg_dat0[27] = 0; |
assign dbg_dat0[26:24] = tx_burst_cnt; |
// Third byte |
assign dbg_dat0[23] = 0; //rx_ethside_fifo_sel; |
assign dbg_dat0[22] = 0; //rx_wbside_fifo_sel; |
assign dbg_dat0[21] = 0; //rx_fifo0_empty; |
assign dbg_dat0[20] = 0; //rx_fifo1_empty; |
assign dbg_dat0[19] = 0; //overflow_bug_reset; |
assign dbg_dat0[18] = 0; //RxBDOK; |
assign dbg_dat0[17] = 0; //write_rx_data_to_memory_go; |
assign dbg_dat0[16] = 0; //rx_wb_last_writes; |
// Second byte - TxBDAddress - or TX BD address pointer |
assign dbg_dat0[15:8] = { BlockingTxBDRead , TxBDAddress}; |
// Bottom byte - FSM controlling vector |
assign dbg_dat0[7:0] = {MasterWbTX, |
MasterWbRX, |
ReadTxDataFromMemory_2, |
WriteRxDataToMemory, |
MasterAccessFinished, |
cyc_cleared, |
tx_burst, |
rx_burst}; |
`else |
assign dbg_dat0 = 0; |
`endif |
|
|
endmodule |
/verilog/ethmac_defines.v
222,8 → 222,8
`define ETH_HASH1_ADR 8'h13 // 0x4C |
`define ETH_TX_CTRL_ADR 8'h14 // 0x50 |
`define ETH_RX_CTRL_ADR 8'h15 // 0x54 |
`define ETH_DBG_ADR 8'h16 // 0x58 |
|
|
`define ETH_MODER_DEF_0 8'h00 |
`define ETH_MODER_DEF_1 8'hA0 |
`define ETH_MODER_DEF_2 1'h0 |
/verilog/eth_top.v
350,6 → 350,8
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control |
`endif |
|
wire [31:0] wb_dbg_dat0; |
|
wire [7:0] r_ClkDiv; |
wire r_MiiNoPre; |
wire [15:0] r_CtrlData; |
573,6 → 575,7
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq), |
.r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm), |
.StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i), |
.dbg_dat(wb_dbg_dat0), |
.SetPauseTimer(SetPauseTimer) |
|
); |
947,6 → 950,11
.mbist_so_o (mbist_so_o), |
.mbist_ctrl_i (mbist_ctrl_i) |
`endif |
`ifdef WISHBONE_DEBUG |
, |
.dbg_dat0(wb_dbg_dat0) |
`endif |
|
); |
|
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0}; |
/verilog/eth_registers.v
178,6 → 178,7
LinkFail, r_MAC, WCtrlDataStart, RStatStart, |
UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o, |
r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm, |
dbg_dat, |
StartTxDone, TxClk, RxClk, SetPauseTimer |
); |
|
268,6 → 269,8
input RxClk; |
input SetPauseTimer; |
|
input [31:0] dbg_dat; // debug data input |
|
reg irq_txb; |
reg irq_txe; |
reg irq_rxb; |
311,6 → 314,7
wire HASH1_Sel = (Address == `ETH_HASH1_ADR ); |
wire TXCTRL_Sel = (Address == `ETH_TX_CTRL_ADR ); |
wire RXCTRL_Sel = (Address == `ETH_RX_CTRL_ADR ); |
wire DBG_REG_Sel = (Address == `ETH_DBG_ADR ); |
wire TX_BD_NUM_Sel = (Address == `ETH_TX_BD_NUM_ADR ); |
|
|
402,6 → 406,7
wire [31:0] HASH0Out; |
wire [31:0] HASH1Out; |
wire [31:0] TXCTRLOut; |
wire [31:0] DBGOut; |
|
// MODER Register |
eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0) MODER_0 |
871,7 → 876,7
`ETH_HASH0_ADR : DataOut=HASH0Out; |
`ETH_HASH1_ADR : DataOut=HASH1Out; |
`ETH_TX_CTRL_ADR : DataOut=TXCTRLOut; |
|
`ETH_DBG_ADR : DataOut=dbg_dat; |
default: DataOut=32'h0; |
endcase |
end |