URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/ethmac/trunk/sim/rtl_sim/run
- from Rev 335 to Rev 338
- ↔ Reverse comparison
Rev 335 → Rev 338
/run_eth_sim_regr.scr
0,0 → 1,218
#!/bin/csh -f |
|
set arg_num = $#argv; # number of arguments |
|
# current iterration |
set iter = 1; |
# number of tests with DEFINES + test with user defined constants! |
set all_iterations = 3; |
# ATS (Automatic Test System) parameter, which causes displaying 'OK' |
# if all testcases finish OK. |
set ok = 1; |
|
# Process argument |
set arg_waves = 0; |
set arg_regression = 0; |
|
if ($arg_num == 0) then |
echo " Verification without any parameter !" |
else |
if ($arg_num == 1) then |
if (("$1" == "waves") | ("$1" == "-w")) then |
@ arg_waves = 1; |
echo " Verification with parameter : waves !" |
else |
if (("$1" == "regression") | ("$1" == "-r")) then |
@ arg_regression = 1; |
echo " Verification with parameter : regression !" |
else |
echo " Not correct parameter ( $1 )" |
echo " Correct parameters are:" |
echo " 'waves' or '-w'" |
echo " 'regression' or '-r'" |
exit |
endif |
endif |
else |
if ($arg_num == 2) then |
if (("$1" == "waves") | ("$1" == "-w")) then |
@ arg_waves = 1; |
if (("$2" == "regression") | ("$2" == "-r")) then |
@ arg_regression = 1; |
echo " Verification with parameter : waves, regression !" |
else |
echo " Not correct parameter ( $2 )" |
echo " Correct 2. parameter is:" |
echo " 'regression' or '-r'" |
exit |
endif |
else |
if (("$1" == "regression") | ("$1" == "-r")) then |
@ arg_regression = 1; |
if (("$2" == "waves") | ("$2" == "-w")) then |
@ arg_waves = 1; |
echo " Verification with parameter : waves, regression !" |
else |
echo " Not correct parameter ( $2 )" |
echo " Correct 2. parameter is:" |
echo " 'waves' or '-w'" |
exit |
endif |
else |
echo " Not correct parameter ( $1 )" |
echo " Correct parameters are:" |
echo " 'waves' or '-w'" |
echo " 'regression' or '-r'" |
exit |
endif |
endif |
else |
echo " Too many parameters ( $arg_num )" |
echo " Maximum number of parameters is 2:" |
echo " 'waves' or '-w'" |
echo " 'regression' or '-r'" |
exit |
endif |
endif |
endif |
|
echo "" |
echo "<<<" |
echo "<<< Ethernet MAC VERIFICATION " |
echo "<<<" |
|
# ITERATION LOOP |
iteration: |
|
echo "" |
echo "<<<" |
echo "<<< Iteration ${iter}" |
echo "<<<" |
|
if ($arg_regression == 1) then |
if ($iter <= $all_iterations) then |
if ($iter == 1) then |
echo "<<< Defines:" |
echo "\tEthernet with GENERIC RAM" |
echo "-DEFINE REGR" > ../run/defines.args |
endif |
if ($iter == 2) then |
echo "<<< Defines:" |
echo "\tEthernet with XILINX DISTRIBUTED RAM" |
echo "-DEFINE REGR -DEFINE ETH_FIFO_XILINX" > ../run/defines.args |
endif |
if ($iter == 3) then |
echo "<<< Defines:" |
echo "\tEthernet with XILINX BLOCK RAM" |
echo "-DEFINE REGR -DEFINE XILINX_RAMB4" > ../run/defines.args |
endif |
endif |
endif |
|
# Run NC-Verilog compiler |
echo "" |
echo "\t@@@" |
echo "\t@@@ Compiling sources" |
echo "\t@@@" |
|
# creating .args file for ncvlog and adding main parameters |
echo "-cdslib ../bin/cds.lib" > ../run/ncvlog.args |
echo "-hdlvar ../bin/hdl.var" >> ../run/ncvlog.args |
echo "-logfile ../log/ncvlog.log" >> ../run/ncvlog.args |
echo "-update" >> ../run/ncvlog.args |
echo "-messages" >> ../run/ncvlog.args |
echo "-INCDIR ../../../bench/verilog" >> ../run/ncvlog.args |
echo "-INCDIR ../../../rtl/verilog" >> ../run/ncvlog.args |
echo "-DEFINE SIM" >> ../run/ncvlog.args |
# adding defines to .args file |
if ($arg_regression == 1) then |
cat ../run/defines.args >> ../run/ncvlog.args |
endif |
# adding RTL and Sim files to .args file |
cat ../bin/rtl_file_list.lst >> ../run/ncvlog.args |
cat ../bin/sim_file_list.lst >> ../run/ncvlog.args |
# adding device dependent files to .args file |
cat ../bin/xilinx_file_list.lst >> ../run/ncvlog.args |
|
ncvlog -file ../run/ncvlog.args# > /dev/null; |
echo "" |
|
|
# Run the NC-Verilog elaborator (build the design hierarchy) |
echo "" |
echo "\t@@@" |
echo "\t@@@ Building design hierarchy (elaboration)" |
echo "\t@@@" |
ncelab -file ../bin/ncelab_xilinx.args# > /dev/null; |
echo "" |
|
|
# Run the NC-Verilog simulator (simulate the design) |
echo "" |
echo "\t###" |
echo "\t### Running tests (this takes a long time!)" |
echo "\t###" |
|
# creating ncsim.args file for ncsim and adding main parameters |
echo "-cdslib ../bin/cds.lib" > ../run/ncsim.args |
echo "-hdlvar ../bin/hdl.var" >> ../run/ncsim.args |
echo "-logfile ../log/ncsim.log" >> ../run/ncsim.args |
echo "-messages" >> ../run/ncsim.args |
if ($arg_waves == 1) then |
echo "-input ../bin/ncsim_waves.rc" >> ../run/ncsim.args |
else |
echo "-input ../bin/ncsim.rc" >> ../run/ncsim.args |
endif |
echo "worklib.ethernet:fun" >> ../run/ncsim.args |
|
ncsim -file ../run/ncsim.args# > /dev/null |
if ($status != 0) then |
echo "" |
echo "TESTS couldn't start due to Errors!" |
echo "" |
exit |
else |
if ($arg_regression == 1) then |
if ($arg_waves == 1) then |
mv ../out/waves.shm ../out/i${iter}_waves.shm |
endif |
# For ATS - counting all 'FAILED' words |
set FAIL_COUNT = `grep -c "FAILED" ../log/eth_tb.log` |
if ($FAIL_COUNT != 0) then |
# Test didn't pass!!! |
@ ok = 0; |
endif |
# Move 'log' files |
mv ../log/eth_tb.log ../log/i${iter}_eth_tb.log |
mv ../log/eth_tb_phy.log ../log/i${iter}_eth_tb_phy.log |
mv ../log/eth_tb_memory.log ../log/i${iter}_eth_tb_memory.log |
mv ../log/eth_tb_host.log ../log/i${iter}_eth_tb_host.log |
mv ../log/eth_tb_wb_s_mon.log ../log/i${iter}_eth_tb_wb_s_mon.log |
mv ../log/eth_tb_wb_m_mon.log ../log/i${iter}_eth_tb_wb_m_mon.log |
endif |
endif |
echo "" |
|
@ iter += 1; |
|
if (($arg_regression == 1) && ($iter <= $all_iterations)) then |
goto iteration |
else |
# rm ./defines.args |
echo "" |
echo "<<<" |
echo "<<< End of VERIFICATION" |
echo "<<<" |
echo "<<<" |
echo "<<< -------------------------------------------------" |
echo "<<<" |
# For ATS - displaying 'OK' when tests pass successfuly |
echo " " |
echo "Simulation finished:" |
if ($ok == 1) then |
echo "OK" |
else |
echo "FAILED" |
endif |
endif |
|
run_eth_sim_regr.scr
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: clean
===================================================================
--- clean (nonexistent)
+++ clean (revision 338)
@@ -0,0 +1,4 @@
+rm ../bin/INCA_libs/worklib/*
+rm ../bin/INCA_libs/worklib/.*
+rm ../log/*.log
+rm -rf ../out/*.shm
clean
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: top_groups.do
===================================================================
--- top_groups.do (nonexistent)
+++ top_groups.do (revision 338)
@@ -0,0 +1,292 @@
+// Signalscan Version 6.7p1
+
+
+define noactivityindicator
+define analog waveform lines
+define add variable default overlay off
+define waveform window analogheight 1
+define terminal automatic
+define buttons control \
+ 1 opensimmulationfile \
+ 2 executedofile \
+ 3 designbrowser \
+ 4 waveform \
+ 5 source \
+ 6 breakpoints \
+ 7 definesourcessearchpath \
+ 8 exit \
+ 9 createbreakpoint \
+ 10 creategroup \
+ 11 createmarker \
+ 12 closesimmulationfile \
+ 13 renamesimmulationfile \
+ 14 replacesimulationfiledata \
+ 15 listopensimmulationfiles \
+ 16 savedofile
+define buttons waveform \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 zoomin \
+ 7 zoomout \
+ 8 zoomoutfull \
+ 9 expand \
+ 10 createmarker \
+ 11 designbrowser:1 \
+ 12 variableradixbinary \
+ 13 variableradixoctal \
+ 14 variableradixdecimal \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define buttons designbrowser \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 cdupscope \
+ 7 getallvariables \
+ 8 getdeepallvariables \
+ 9 addvariables \
+ 10 addvarsandclosewindow \
+ 11 closewindow \
+ 12 scopefiltermodule \
+ 13 scopefiltertask \
+ 14 scopefilterfunction \
+ 15 scopefilterblock \
+ 16 scopefilterprimitive
+define buttons event \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 move \
+ 7 closewindow \
+ 8 duplicate \
+ 9 defineasrisingedge \
+ 10 defineasfallingedge \
+ 11 defineasanyedge \
+ 12 variableradixbinary \
+ 13 variableradixoctal \
+ 14 variableradixdecimal \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define buttons source \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 createbreakpoint \
+ 7 creategroup \
+ 8 createmarker \
+ 9 createevent \
+ 10 createregisterpage \
+ 11 closewindow \
+ 12 opensimmulationfile \
+ 13 closesimmulationfile \
+ 14 renamesimmulationfile \
+ 15 replacesimulationfiledata \
+ 16 listopensimmulationfiles
+define buttons register \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 createregisterpage \
+ 7 closewindow \
+ 8 continuefor \
+ 9 continueuntil \
+ 10 continueforever \
+ 11 stop \
+ 12 previous \
+ 13 next \
+ 14 variableradixbinary \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define show related transactions
+define exit prompt
+define event search direction forward
+define variable nofullhierarchy
+define variable nofilenames
+define variable nofullpathfilenames
+include bookmark with filenames
+include scope history without filenames
+define waveform window listpane 4.96
+define waveform window namepane 15.18
+define multivalueindication
+define pattern curpos dot
+define pattern cursor1 dot
+define pattern cursor2 dot
+define pattern marker dot
+define print designer "Miha Dolenc"
+define print border
+define print color blackonwhite
+define print command "/usr/ucb/lpr -P%P"
+define print printer lp
+define print range visible
+define print variable visible
+define rise fall time low threshold percentage 10
+define rise fall time high threshold percentage 90
+define rise fall time low value 0
+define rise fall time high value 3.3
+define sendmail command "/usr/lib/sendmail"
+define sequence time width 30.00
+define snap
+
+define source noprompt
+define time units default
+define userdefinedbussymbol
+define user guide directory "/usr/local/designacc/signalscan-6.7p1/doc/html"
+define waveform window grid off
+define waveform window waveheight 14
+define waveform window wavespace 6
+define web browser command netscape
+define zoom outfull on initial add off
+add group \
+ A \
+
+add group \
+ "WISHBONE common" \
+ tb_ethernet.eth_top.wb_clk_i \
+ tb_ethernet.eth_top.wb_rst_i \
+ tb_ethernet.eth_top.wb_dat_i[31:0]'h \
+ tb_ethernet.eth_top.wb_dat_o[31:0]'h \
+ tb_ethernet.eth_top.wb_err_o \
+
+add group \
+ "WISHBONE slave signals" \
+ tb_ethernet.eth_top.wb_adr_i[11:2]'h \
+ tb_ethernet.eth_top.wb_sel_i[3:0]'h \
+ tb_ethernet.eth_top.wb_we_i \
+ tb_ethernet.eth_top.wb_cyc_i \
+ tb_ethernet.eth_top.wb_stb_i \
+ tb_ethernet.eth_top.wb_ack_o \
+
+add group \
+ "WISHBONE master signals" \
+ tb_ethernet.eth_top.m_wb_adr_o[31:0]'h \
+ tb_ethernet.eth_top.m_wb_sel_o[3:0]'h \
+ tb_ethernet.eth_top.m_wb_we_o \
+ tb_ethernet.eth_top.m_wb_dat_i[31:0]'h \
+ tb_ethernet.eth_top.m_wb_dat_o[31:0]'h \
+ tb_ethernet.eth_top.m_wb_cyc_o \
+ tb_ethernet.eth_top.m_wb_stb_o \
+ tb_ethernet.eth_top.m_wb_ack_i \
+ tb_ethernet.eth_top.m_wb_err_i \
+
+add group \
+ "MAC common" \
+ tb_ethernet.eth_top.mcoll_pad_i \
+ tb_ethernet.eth_top.mcrs_pad_i \
+
+add group \
+ "MAC TX" \
+ tb_ethernet.eth_top.mtx_clk_pad_i \
+ tb_ethernet.eth_top.mtxd_pad_o[3:0]'h \
+ tb_ethernet.eth_top.mtxen_pad_o \
+ tb_ethernet.eth_top.mtxerr_pad_o \
+
+add group \
+ "MAC RX" \
+ tb_ethernet.eth_top.mrx_clk_pad_i \
+ tb_ethernet.eth_top.mrxd_pad_i[3:0]'h \
+ tb_ethernet.eth_top.mrxdv_pad_i \
+ tb_ethernet.eth_top.mrxerr_pad_i \
+
+add group \
+ "MAC MIIM interface" \
+ tb_ethernet.eth_top.mdc_pad_o \
+ tb_ethernet.eth_top.md_padoe_o \
+ tb_ethernet.eth_top.md_pad_o \
+ tb_ethernet.eth_top.md_pad_i \
+ tb_ethernet.eth_top.miim1.Busy \
+ tb_ethernet.eth_top.miim1.LinkFail \
+ tb_ethernet.eth_top.miim1.Nvalid \
+ tb_ethernet.eth_top.miim1.CtrlData[15:0]'h \
+ tb_ethernet.eth_top.miim1.UpdateMIIRX_DATAReg \
+ tb_ethernet.eth_top.miim1.Prsd[15:0]'h \
+ tb_ethernet.eth_top.miim1.Divider[7:0]'h \
+
+add group \
+ "Test signals" \
+ tb_ethernet.test_name[799:0]'a \
+ tb_ethernet.eth_top.ethreg1.MIISTATUSOut[31:0]'h \
+ tb_ethernet.eth_top.miim1.InProgress \
+ tb_ethernet.eth_top.miim1.InProgress_q1 \
+ tb_ethernet.eth_top.miim1.InProgress_q2 \
+ tb_ethernet.eth_top.miim1.InProgress_q3 \
+ tb_ethernet.eth_top.miim1.shftrg.ShiftReg[7:0]'h \
+ tb_ethernet.eth_phy.status_bit6_0[6:0]'h \
+ tb_ethernet.eth_phy.control_bit8_0[8:0]'h \
+ tb_ethernet.eth_phy.control_bit9 \
+ tb_ethernet.eth_phy.control_bit14_10[14:10]'h \
+ tb_ethernet.eth_phy.control_bit15 \
+ tb_ethernet.eth_phy.eth_speed \
+ tb_ethernet.eth_phy.m_rst_n_i \
+ tb_ethernet.eth_phy.mcoll_o \
+ tb_ethernet.eth_phy.mcrs_o \
+ tb_ethernet.eth_phy.md_get_phy_address \
+ tb_ethernet.eth_phy.md_get_reg_address \
+ tb_ethernet.eth_phy.md_get_reg_data_in \
+ tb_ethernet.eth_phy.md_put_reg_data_in \
+ tb_ethernet.eth_phy.md_put_reg_data_out \
+ tb_ethernet.eth_phy.reg_data_in[15:0]'h \
+ tb_ethernet.eth_phy.reg_data_out[15:0]'h \
+ tb_ethernet.eth_phy.register_bus_in[15:0]'h \
+ tb_ethernet.eth_phy.register_bus_out[15:0]'h \
+ tb_ethernet.eth_phy.reg_address[4:0]'h \
+ tb_ethernet.eth_phy.md_io_output \
+ tb_ethernet.eth_phy.md_io_enable \
+ tb_ethernet.eth_phy.md_io \
+ tb_ethernet.Mdc_O \
+ tb_ethernet.Mdi_I \
+ tb_ethernet.Mdio_IO \
+ tb_ethernet.Mdo_O \
+ tb_ethernet.Mdo_OE \
+ tb_ethernet.eth_phy.md_io_enable \
+ tb_ethernet.eth_phy.md_io_output \
+ tb_ethernet.eth_phy.md_io_rd_wr \
+ tb_ethernet.eth_phy.md_io_reg \
+ tb_ethernet.eth_phy.m_rst_n_i \
+ tb_ethernet.eth_phy.md_transfer_cnt'd \
+ tb_ethernet.eth_phy.md_transfer_cnt_reset \
+ tb_ethernet.eth_phy.mdc_i \
+ tb_ethernet.eth_phy.mrx_clk_o \
+ tb_ethernet.eth_phy.mrxd_o[3:0]'h \
+ tb_ethernet.eth_phy.mrxdv_o \
+ tb_ethernet.eth_phy.mrxerr_o \
+ tb_ethernet.eth_phy.mtx_clk_o \
+ tb_ethernet.eth_phy.mtxd_i[3:0]'h \
+ tb_ethernet.eth_phy.mtxen_i \
+ tb_ethernet.eth_phy.mtxerr_i \
+ tb_ethernet.eth_phy.phy_address[4:0]'h \
+ tb_ethernet.eth_phy.phy_id1[15:0]'h \
+ tb_ethernet.eth_phy.phy_id2[15:0]'h \
+ tb_ethernet.eth_phy.phy_log[31:0]'h \
+ tb_ethernet.eth_phy.reg_address[4:0]'h \
+ tb_ethernet.eth_phy.register_bus_in[15:0]'h \
+ tb_ethernet.eth_phy.register_bus_out[15:0]'h \
+ tb_ethernet.eth_phy.registers_addr_data_test_operation \
+ tb_ethernet.eth_phy.rx_link_down_halfperiod \
+ ( \
+ minmax 0 93 \
+ ) \
+ tb_ethernet.eth_phy.self_clear_d0 \
+ tb_ethernet.eth_phy.self_clear_d1 \
+ tb_ethernet.eth_phy.self_clear_d2 \
+ tb_ethernet.eth_phy.self_clear_d3 \
+ tb_ethernet.eth_phy.status_bit6_0[6:0]'h \
+ tb_ethernet.eth_phy.status_bit7 \
+ tb_ethernet.eth_phy.status_bit8 \
+ tb_ethernet.eth_phy.status_bit15_9[15:9]'h \
+
+
+deselect all
+open window designbrowser 1 geometry 56 117 855 550
+open window waveform 1 geometry 10 59 1592 1094
+zoom at 4981823.979(0)ns 0.00025639 0.00000000
top_groups.do
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property