OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /ethmac
    from Rev 347 to Rev 348
    Reverse comparison

Rev 347 → Rev 348

/trunk/bench/verilog/tb_ethernet.v
438,6 → 438,10
$fdisplay(wb_m_mon_log_file_desc, " Only ERRONEOUS conditions are logged !");
$fdisplay(wb_m_mon_log_file_desc, " ");
 
`ifdef VCD
$dumpfile("../build/sim/ethmac.vcd");
$dumpvars(0);
`endif
// Reset pulse
wb_rst = 1'b1;
#423 wb_rst = 1'b0;
/trunk/scripts/Makefile
1,6 → 1,9
ifeq ($(VCD), 1)
ICARUS_OPTIONS += -DVCD
endif
rtl-tests:
mkdir -p ../build/sim
mkdir -p ../log
iverilog -stb_ethernet -cicarus.scr -o ../build/sim/ethmac.elf
iverilog -stb_ethernet -cicarus.scr $(ICARUS_OPTIONS) -o ../build/sim/ethmac.elf
vvp ../build/sim/ethmac.elf
 
/trunk/README.txt
49,8 → 49,10
Go to the scripts directory and write "make rtl-tests"
All logs will be saved in the log directory
 
VCD dumps are coming soon
To activate VCD dumps, run with "make rtl-tests VCD=1". The VCD is saved
in build/sim/ethmac.vcd
 
 
RUNNING the simulation/Testbench in ModelSIM:
 
Open ModelSIM project: ethernet/sim/rtl_sim/modelsim_sim/bin/ethernet.mpf

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.