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URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

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  • This comparison shows the changes necessary to convert path
    /ft816float/trunk/rtl/verilog2
    from Rev 33 to Rev 34
    Reverse comparison

Rev 33 → Rev 34

/fpDiv.v
1,6 → 1,6
// ============================================================================
// __
// \\__/ o\ (C) 2006-2019 Robert Finch, Waterloo
// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
7,7 → 7,7
//
// fpDiv.v
// - floating point divider
// - parameterized width
// - parameterized FPWIDth
// - IEEE 754 representation
//
//
33,7 → 33,7
// ============================================================================
 
`include "fpConfig.sv"
`include "fp_defines.v"
`include "fpDefines.v"
//`define GOLDSCHMIDT 1'b1
 
module fpDiv(rst, clk, clk4x, ce, ld, op, a, b, o, done, sign_exe, overflow, underflow);
46,7 → 46,7
FPWID==84 ? 9 :
FPWID==80 ? 9 :
FPWID==64 ? 13 :
FPWID==52 ? 9 :
FPWID==52 ? 13 :
FPWID==48 ? 10 :
FPWID==44 ? 9 :
FPWID==42 ? 11 :
134,16 → 134,21
`ifndef GOLDSCHMIDT
fpdivr16 #(FMSB+FADD) u2 (.clk(clk), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
//fpdivr2 #(FMSB+FADD) u2 (.clk4x(clk4x), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
wire [(FMSB+FADD)*2-1:0] divo1 = divo[(FMSB+FADD)*2-1:0] << (lzcnt-2);
reg [(FMSB+FADD)*2-1:0] divo1;
always @(posedge clk)
if (ce) divo1 = divo[(FMSB+FADD)*2-1:0] << (lzcnt-2);
`else
DivGoldschmidt #(.WID(FMSB+6),.WHOLE(1),.POINTS(FMSB+5))
DivGoldschmidt #(.FPWID(FMSB+6),.WHOLE(1),.POINTS(FMSB+5))
u2 (.rst(rst), .clk(clk), .ld(ld), .a({fracta,4'b0}), .b({fractb,4'b0}), .q(divo), .done(done1), .lzcnt(lzcnt));
wire [(FMSB+6)*2+1:0] divo1 =
lzcnt > 8'd5 ? divo << (lzcnt-8'd6) :
divo >> (8'd6-lzcnt);
;
reg [(FMSB+6)*2+1:0] divo1;
always @(posedge clk)
if (ce) divo1 =
lzcnt > 8'd5 ? divo << (lzcnt-8'd6) :
divo >> (8'd6-lzcnt);
;
`endif
delay1 #(1) u3 (.clk(clk), .ce(ce), .i(done1), .o(done));
delay1 #(1) u3 (.clk(clk), .ce(ce), .i(done1), .o(done2));
delay2 #(1) u4 (.clk(clk), .ce(ce), .i(done1), .o(done));
 
 
// determine when a NaN is output
161,7 → 166,7
underflow <= 1'd0;
end
else if (ce) begin
if (done1) begin
if (done2) begin
casez({qNaNOut|aNan|bNan,bInf,bz,over,under})
5'b1????: xo <= infXp; // NaN exponent value
5'b01???: xo <= 1'd0; // divide by inf
172,8 → 177,8
endcase
 
casez({aNan,bNan,qNaNOut,bInf,bz,over,aInf&bInf,az&bz})
8'b1???????: mo <= {1'b1,a[FMSB:0],{FMSB+1{1'b0}}};
8'b01??????: mo <= {1'b1,b[FMSB:0],{FMSB+1{1'b0}}};
8'b1???????: mo <= {1'b1,1'b1,a[FMSB-1:0],{FMSB+1{1'b0}}};
8'b01??????: mo <= {1'b1,1'b1,b[FMSB-1:0],{FMSB+1{1'b0}}};
8'b001?????: mo <= {1'b1,qNaN[FMSB:0]|{aInf,1'b0}|{az,bz},{FMSB+1{1'b0}}};
8'b0001????: mo <= 1'd0; // div by inf
8'b00001???: mo <= 1'd0; // div by zero
222,11 → 227,11
 
fpDiv #(FPWID) u1 (rst, clk, clk4x, ce, ld, op, a, b, o1, done1, sign_exe1, overflow1, underflow1);
fpNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under_i(underflow1), .i(o1), .o(fpn0) );
fpRound #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
fpRound #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
delay2 #(1) u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
delay2 #(1) u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
delay2 #(1) u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
vtdl #(1) u8(.clk(clk), .ce(ce), .a(4'd13), .d(done1), .q(done));
delay2 #(1) u8(.clk(clk), .ce(ce), .i(done1), .o(done));
endmodule
 
/fpSqrt.v
163,6 → 163,6
fpNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
fpRound #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
delay2 #(1) u8(.clk(clk), .ce(ce), .i(done1), .o(done));
vtdl #(1) u8(.clk(clk), .ce(ce), .a(4'd10), .d(done1), .q(done));
endmodule
 
/fpdivr16.v
1,6 → 1,6
// ============================================================================
// __
// \\__/ o\ (C) 2006-2019 Robert Finch, Waterloo
// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
73,6 → 73,16
r4 = b3 ? {r3,q[WID*2-4]} - b : {r3,q[WID*2-4]};
 
reg [2:0] state = 0;
always @(posedge clk)
begin
if (ld) state <= 3'd1;
case(state)
3'd0: ;
3'd1: if (cnt[8]) state <= 3'd2;
3'd2: state <= 3'd0;
default: state <= 3'd0;
endcase
end
 
always @(posedge clk)
begin
100,15 → 110,12
rxx <= r4;
cnt <= cnt - 3'd1;
end
else
state <= 3'd2;
3'd2:
begin
r <= r4;
done <= 1'b1;
state <= 1'd0;
end
default: state <= 1'd0;
default: ;
endcase
if (ld) begin
lzcnt <= 0;
116,7 → 123,6
cnt <= {1'b0,maxcnt};
q <= {(a << REM),{WID{1'b0}}};
rxx <= {WID{1'b0}};
state <= 3'd1;
end
end
 

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