URL
https://opencores.org/ocsvn/ft816float/ft816float/trunk
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/ft816float/trunk/rtl/verilog2
- from Rev 50 to Rev 51
- ↔ Reverse comparison
Rev 50 → Rev 51
/DFPAddsub.sv
42,7 → 42,7
input op; |
input [127:0] a; |
input [127:0] b; |
output [219:0] o; |
output [243:0] o; |
|
parameter TRUE = 1'b1; |
parameter FALSE = 1'b0; |
54,7 → 54,7
wire ainf, binf; |
wire aNan, bNan; |
wire [15:0] xa, xb; |
wire [95:0] siga, sigb; |
wire [107:0] siga, sigb; |
|
wire [15:0] xabdif4; |
BCDSub4 ubcds1( |
66,10 → 66,10
.c8() |
); |
|
wire [99:0] oss10; |
wire [111:0] oss10; |
wire oss10c; |
|
BCDAddN #(.N(25)) ubcdan1 |
BCDAddN #(.N(28)) ubcdan1 |
( |
.ci(1'b0), |
.a(oaa10), |
78,10 → 78,10
.co(oss10c) |
); |
|
wire [99:0] odd10; |
wire [111:0] odd10; |
wire odd10c; |
|
BCDSubN #(.N(25)) ubcdsn1 |
BCDSubN #(.N(28)) ubcdsn1 |
( |
.ci(1'b0), |
.a(oaa10), |
122,7 → 122,7
reg [15:0] xa2, xb2; |
reg az2, bz2; |
reg xa_gt_xb2; |
reg [95:0] siga2, sigb2; |
reg [107:0] siga2, sigb2; |
reg sigeq, siga_gt_sigb; |
reg xa_gt_xb2; |
reg expeq; |
178,7 → 178,7
reg op3; |
wire sa3, sb3; |
wire [2:0] rm3; |
reg [95:0] mfs3; |
reg [107:0] mfs3; |
|
always @(posedge clk) |
if (ce) resZero3 <= (realOp2 & expeq & sigeq) || // subtract, same magnitude |
266,10 → 266,10
// less) then all of the bits will be shifted out to zero. There is no need to |
// keep track of a difference more than 24. |
reg [11:0] xdif6; |
wire [95:0] mfs6; |
wire [107:0] mfs6; |
always @(posedge clk) |
if (ce) xdif6 <= xdiff5 > 16'h0024 ? 8'h24 : xdiff5[7:0]; |
delay #(.WID(96), .DEP(3)) udly6a (.clk(clk), .ce(ce), .i(mfs3), .o(mfs6)); |
delay #(.WID(108), .DEP(3)) udly6a (.clk(clk), .ce(ce), .i(mfs3), .o(mfs6)); |
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
// Clock #7 |
281,7 → 281,7
reg sticky6; |
wire sticky7; |
wire [7:0] xdif7; |
wire [95:0] mfs7; |
wire [107:0] mfs7; |
wire [7:0] xdif6a = {xdif6[7:4] * 10 + xdif6[3:0],2'b00}; // Convert base then *4 |
integer n; |
always @* begin |
294,13 → 294,13
// register inputs to shifter and shift |
delay1 #(1) d16(.clk(clk), .ce(ce), .i(sticky6), .o(sticky7) ); |
delay1 #(8) d15(.clk(clk), .ce(ce), .i(xdif6a), .o(xdif7) ); |
delay1 #(96) d14(.clk(clk), .ce(ce), .i(mfs6), .o(mfs7) ); |
delay1 #(108) d14(.clk(clk), .ce(ce), .i(mfs6), .o(mfs7) ); |
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
// Clock #8 |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
reg [99:0] md8; |
wire [95:0] siga8, sigb8; |
reg [111:0] md8; |
wire [107:0] siga8, sigb8; |
wire xa_gt_xb8; |
wire a_gt_b8; |
always @(posedge clk) |
309,8 → 309,8
// sync control signals |
delay #(.WID(1), .DEP(4)) udly8a (.clk(clk), .ce(ce), .i(xa_gt_xb4), .o(xa_gt_xb8)); |
delay #(.WID(1), .DEP(5)) udly8b (.clk(clk), .ce(ce), .i(a_gt_b3), .o(a_gt_b8)); |
delay #(.WID(96), .DEP(6)) udly8d (.clk(clk), .ce(ce), .i(siga2), .o(siga8)); |
delay #(.WID(96), .DEP(6)) udly8e (.clk(clk), .ce(ce), .i(sigb2), .o(sigb8)); |
delay #(.WID(108), .DEP(6)) udly8d (.clk(clk), .ce(ce), .i(siga2), .o(siga8)); |
delay #(.WID(108), .DEP(6)) udly8e (.clk(clk), .ce(ce), .i(sigb2), .o(sigb8)); |
delay #(.WID(1), .DEP(5)) udly8j (.clk(clk), .ce(ce), .i(op3), .o(op8)); |
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
318,7 → 318,7
// Sort operands and perform add/subtract |
// addition can generate an extra bit, subtract can't go negative |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
reg [99:0] oa9, ob9; |
reg [111:0] oa9, ob9; |
reg a_gt_b9; |
always @(posedge clk) |
if (ce) oa9 <= xa_gt_xb8 ? {siga8,4'b0} : md8; |
330,8 → 330,8
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
// Clock #10 |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
reg [99:0] oaa10; |
reg [99:0] obb10; |
reg [111:0] oaa10; |
reg [111:0] obb10; |
wire realOp10; |
reg [15:0] xo10; |
|
345,9 → 345,9
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
// Clock #11 |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
reg [99:0] mab11; |
reg [111:0] mab11; |
reg mab11c; |
wire [95:0] siga11, sigb11; |
wire [107:0] siga11, sigb11; |
wire abInf11; |
wire aNan11, bNan11; |
reg xoinf11; |
362,8 → 362,8
delay #(.WID(1), .DEP(10)) udly11c (.clk(clk), .ce(ce), .i(aNan), .o(aNan11)); |
delay #(.WID(1), .DEP(10)) udly11d (.clk(clk), .ce(ce), .i(bNan), .o(bNan11)); |
delay #(.WID(1), .DEP(3)) udly11e (.clk(clk), .ce(ce), .i(op8), .o(op11)); |
delay #(.WID(96), .DEP(3)) udly11f (.clk(clk), .ce(ce), .i(siga8), .o(siga11)); |
delay #(.WID(96), .DEP(3)) udly11g (.clk(clk), .ce(ce), .i(sigb8), .o(sigb11)); |
delay #(.WID(108), .DEP(3)) udly11f (.clk(clk), .ce(ce), .i(siga8), .o(siga11)); |
delay #(.WID(108), .DEP(3)) udly11g (.clk(clk), .ce(ce), .i(sigb8), .o(sigb11)); |
|
always @(posedge clk) |
if (ce) xoinf11 <= xo10==16'h9999; |
371,7 → 371,7
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
// Clock #12 |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
reg [199:0] mo12; // mantissa output |
reg [223:0] mo12; // mantissa output |
reg [3:0] st12; |
wire sxo11; |
wire so11; |
391,13 → 391,13
casez({abInf11,aNan11,bNan11,xoinf11}) |
4'b1???: // inf +/- inf - generate QNaN on subtract, inf on add |
if (op11) |
mo12 <= {4'h9,196'd0}; |
mo12 <= {4'h9,220'd0}; |
else |
mo12 <= {50{4'h9}}; |
4'b01??: mo12 <= {4'b0,siga11[95:0],100'd0}; |
4'b001?: mo12 <= {4'b0,sigb11[95:0],100'd0}; |
4'b0001: mo12 <= 200'd0; |
default: mo12 <= {3'b0,mab11c,mab11,96'd0}; // mab has an extra lead bit and four trailing bits |
mo12 <= {56{4'h9}}; |
4'b01??: mo12 <= {4'b0,siga11[107:0],112'd0}; |
4'b001?: mo12 <= {4'b0,sigb11[107:0],112'd0}; |
4'b0001: mo12 <= 224'd0; |
default: mo12 <= {3'b0,mab11c,mab11,108'd0}; // mab has an extra lead bit and four trailing bits |
endcase |
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
406,12 → 406,12
wire so; // sign output |
wire [3:0] st; |
wire [15:0] xo; // de normalized exponent output |
wire [199:0] mo; // mantissa output |
wire [223:0] mo; // mantissa output |
|
delay #(.WID(4), .DEP(1)) u13c (.clk(clk), .ce(ce), .i(st12), .o(st[3:0]) ); |
delay #(.WID(1), .DEP(9)) udly13a (.clk(clk), .ce(ce), .i(so4), .o(so)); |
delay #(.WID(16), .DEP(3)) udly13b (.clk(clk), .ce(ce), .i(xo10), .o(xo)); |
delay #(.WID(200), .DEP(1)) u13d (.clk(clk), .ce(ce), .i(mo12), .o(mo) ); |
delay #(.WID(224), .DEP(1)) u13d (.clk(clk), .ce(ce), .i(mo12), .o(mo) ); |
|
assign o = {st,xo,mo}; |
|
427,8 → 427,8
input [127:0] b; // operand b |
output [127:0] o; // output |
|
wire [219:0] o1; |
wire [119:0] fpn0; |
wire [243:0] o1; |
wire [131:0] fpn0; |
|
DFPAddsub u1 (clk, ce, rm, op, a, b, o1); |
DFPNormalize u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) ); |
/DFPDecompose.sv
46,12 → 46,12
output inf; |
output nan; |
|
assign nan = i[115]; |
assign sgn = i[114]; |
assign inf = i[113]; |
assign sx = i[112]; |
assign exp = i[111:96]; |
assign sig = i[95:0]; |
assign nan = i[127]; |
assign sgn = i[126]; |
assign inf = i[125]; |
assign sx = i[124]; |
assign exp = i[123:108]; |
assign sig = i[107:0]; |
assign xz = ~|exp; |
assign vz = ~|{exp,sig}; |
|
65,7 → 65,7
output reg sgn; |
output reg sx; |
output reg [15:0] exp; |
output reg [95:0] sig; |
output reg [107:0] sig; |
output reg xz; |
output reg vz; |
output reg inf; |
73,12 → 73,12
|
always @(posedge clk) |
if (ce) begin |
nan <= i[115]; |
sgn <= i[114]; |
inf <= i[113]; |
sx <= i[112]; |
exp <= i[111:96]; |
sig <= i[95:0]; |
nan <= i[127]; |
sgn <= i[126]; |
inf <= i[125]; |
sx <= i[124]; |
exp <= i[123:108]; |
sig <= i[107:0]; |
xz <= ~|exp; |
vz <= ~|{exp,sig}; |
end |
/DFPNormalize.sv
43,8 → 43,8
module DFPNormalize(clk, ce, i, o, under_i, under_o, inexact_o); |
input clk; |
input ce; |
input [219:0] i; // expanded format input |
output [119:0] o; // normalized output + guard, sticky and round bits, + 1 whole digit |
input [243:0] i; // expanded format input |
output [131:0] o; // normalized output + guard, sticky and round bits, + 1 whole digit |
input under_i; |
output under_o; |
output inexact_o; |
60,15 → 60,15
reg inf0; |
|
always @* |
xo0 <= i[215:200]; |
xo0 <= i[239:224]; |
always @* |
so0 <= i[218]; // sign doesn't change |
so0 <= i[242]; // sign doesn't change |
always @* |
sx0 <= i[216]; |
sx0 <= i[240]; |
always @* |
nan0 <= i[219]; |
nan0 <= i[243]; |
always @* |
inf0 <= i[217] || xo0==16'h9999 && i[196]; |
inf0 <= i[241] || xo0==16'h9999 && i[220]; |
|
// ---------------------------------------------------------------------------- |
// Clock #1 |
75,8 → 75,8
// - Capture exponent information |
// ---------------------------------------------------------------------------- |
reg xInf1a, xInf1b, xInf1c; |
wire [219:0] i1; |
delay #(.WID(220),.DEP(1)) u11 (.clk(clk), .ce(ce), .i(i), .o(i1)); |
wire [243:0] i1; |
delay #(.WID(244),.DEP(1)) u11 (.clk(clk), .ce(ce), .i(i), .o(i1)); |
|
always @(posedge clk) |
if (ce) xInf1a <= xo0==16'h9999 & !under_i; |
101,7 → 101,7
delay #(.WID(1),.DEP(2)) u24 (.clk(clk), .ce(ce), .i(under_i), .o(under2)); |
|
always @(posedge clk) |
if (ce) incExpByOne2 <= !xInf1a & i1[196]; |
if (ce) incExpByOne2 <= !xInf1a & i1[220]; |
|
// ---------------------------------------------------------------------------- |
// Clock #3 |
110,11 → 110,11
// ---------------------------------------------------------------------------- |
|
wire incExpByOne3; |
wire [219:0] i3; |
wire [243:0] i3; |
reg [15:0] xo3; |
reg zeroMan3; |
delay #(.WID(1),.DEP(1)) u32 (.clk(clk), .ce(ce), .i(incExpByOne2), .o(incExpByOne3)); |
delay #(.WID(220),.DEP(3)) u33 (.clk(clk), .ce(ce), .i(i[219:0]), .o(i3)); |
delay #(.WID(244),.DEP(3)) u33 (.clk(clk), .ce(ce), .i(i[243:0]), .o(i3)); |
|
wire [15:0] xo2a; |
BCDAddN #(.N(4)) ubcdan1 |
140,7 → 140,7
// - create sticky bit |
// ---------------------------------------------------------------------------- |
|
reg [103:0] mo4; |
reg [115:0] mo4; |
reg inexact4; |
|
always @(posedge clk) |
147,8 → 147,8
if(ce) |
casez({zeroMan3,incExpByOne3}) |
2'b1?: mo4 <= 1'd0; |
2'b01: mo4 <= {i3[199:100],3'b0,|i3[99:0]}; |
default: mo4 <= {i3[195:96],3'b0,|i3[95:0]}; |
2'b01: mo4 <= {i3[223:112],3'b0,|i3[111:0]}; |
default: mo4 <= {i3[219:108],3'b0,|i3[107:0]}; |
endcase |
|
always @(posedge clk) |
155,8 → 155,8
if(ce) |
casez({zeroMan3,incExpByOne3}) |
2'b1?: inexact4 <= 1'd0; |
2'b01: inexact4 <= |i3[99:0]; |
default: inexact4 <= |i3[95:0]; |
2'b01: inexact4 <= |i3[111:0]; |
default: inexact4 <= |i3[107:0]; |
endcase |
|
// ---------------------------------------------------------------------------- |
211,7 → 211,7
begin |
got_one = 1'b0; |
lzc = 8'h00; |
for (n = 103; n >= 0; n = n - 4) begin |
for (n = 115; n >= 0; n = n - 4) begin |
if (!got_one) begin |
if (mo4[n]|mo4[n-1]|mo4[n-2]|mo4[n-3]) |
got_one = 1'b1; |
225,7 → 225,7
`else |
always @(posedge clk) |
if (ce) |
casez(mo4[99:92]) |
casez(mo4[111:103]) |
8'h00000000: leadingZeros5 <= 8'd2; |
8'h0000????: leadingZeros5 <= 8'd1; |
default: leadingZeros5 <= 8'd0; |
249,11 → 249,11
wire rightOrLeft6; // 0=left,1=right |
wire xInf6; |
wire [15:0] xo6; |
wire [103:0] mo6; |
wire [115:0] mo6; |
wire zeroMan6; |
vtdl #(1) u61 (.clk(clk), .ce(ce), .a(4'd5), .d(under_i), .q(rightOrLeft6) ); |
delay #(.WID(16),.DEP(1)) u62 (.clk(clk), .ce(ce), .i(xo5), .o(xo6)); |
delay #(.WID(104),.DEP(2)) u63 (.clk(clk), .ce(ce), .i(mo4), .o(mo6) ); |
delay #(.WID(116),.DEP(2)) u63 (.clk(clk), .ce(ce), .i(mo4), .o(mo6) ); |
delay #(.WID(1),.DEP(1)) u64 (.clk(clk), .ce(ce), .i(xInf5), .o(xInf6) ); |
delay #(.WID(1),.DEP(3)) u65 (.clk(clk), .ce(ce), .i(zeroMan3), .o(zeroMan6)); |
delay #(.WID(1),.DEP(5)) u66 (.clk(clk), .ce(ce), .i(sx0), .o(sx5) ); |
275,7 → 275,7
|
reg [15:0] xo7; |
wire rightOrLeft7; |
reg [103:0] mo7l, mo7r; |
reg [115:0] mo7l, mo7r; |
reg St6,St7; |
delay #(.WID(1),.DEP(1)) u71 (.clk(clk), .ce(ce), .i(rightOrLeft6), .o(rightOrLeft7)); |
|
308,7 → 308,7
always @* |
begin |
St6 = 1'b0; |
for (n = 0; n < 104; n = n + 1) |
for (n = 0; n < 116; n = n + 1) |
if (n <= rshiftAmt6 + 1) St6 = St6|mo6[n]; |
end |
always @(posedge clk) |
321,7 → 321,7
|
wire so,sxo,nano,info; |
wire [15:0] xo; |
reg [103:0] mo; |
reg [115:0] mo; |
vtdl #(1) u81 (.clk(clk), .ce(ce), .a(4'd7), .d(so0), .q(so) ); |
delay #(.WID(16),.DEP(1)) u82 (.clk(clk), .ce(ce), .i(xo7), .o(xo)); |
vtdl #(.WID(1)) u83 (.clk(clk), .ce(ce), .a(4'd3), .d(inexact4), .q(inexact_o)); |
333,7 → 333,7
always @(posedge clk) |
if (ce) mo <= rightOrLeft7 ? mo7r|{St7,4'b0} : mo7l; |
|
assign o = {nano,so,info,sxo,xo,mo[103:4]}; |
assign o = {nano,so,info,sxo,xo,mo[115:4]}; |
|
endmodule |
|
/DFPRound.sv
51,7 → 51,7
input clk; |
input ce; |
input [2:0] rm; // rounding mode |
input [119:0] i; // intermediate format input |
input [131:0] i; // intermediate format input |
output [127:0] o; // rounded output |
|
parameter ROUND_CEILING = 3'd0; |
64,12 → 64,12
// variables |
wire [3:0] so; |
wire [15:0] xo; |
reg [95:0] mo; |
reg [107:0] mo; |
reg [15:0] xo1; |
reg [95:0] mo1; |
wire xInf = i[115:100]==16'h9999; |
wire so0 = i[118]; |
assign o = {12'hDF0,so,xo,mo}; |
reg [107:0] mo1; |
wire xInf = i[127:112]==16'h9999; |
wire so0 = i[130]; |
assign o = {so,xo,mo}; |
|
wire [3:0] l = i[7:4]; |
wire [3:0] r = i[3:0]; |
82,9 → 82,9
//------------------------------------------------------------ |
|
always @`PIPE_ADV |
if (ce) xo1 <= i[115:100]; |
if (ce) xo1 <= i[127:112]; |
always @`PIPE_ADV |
if (ce) mo1 <= i[99:4]; |
if (ce) mo1 <= i[111:4]; |
|
// Compute the round bit |
// Infinities and NaNs are not rounded! |
109,20 → 109,20
// note: exponent increments if there is a carry (can only increment to infinity) |
//------------------------------------------------------------ |
|
wire [111:0] rounded1; |
wire [123:0] rounded1; |
wire co1; |
|
BCDAddN #(.N(29)) ubcdan1 |
BCDAddN #(.N(31)) ubcdan1 |
( |
.ci(1'b0), |
.a({xo1,mo1}), |
.b({111'd0,rnd}), |
.b({123'd0,rnd}), |
.o(rounded1), |
.co(co1) |
); |
|
|
reg [111:0] rounded2; |
reg [123:0] rounded2; |
reg carry2; |
reg rnd2; |
reg dn2; |
135,7 → 135,7
if (ce) rnd2 <= rnd; |
always @`PIPE_ADV |
if (ce) dn2 <= !(|xo1); |
assign xo2 = rounded2[111:96]; |
assign xo2 = rounded2[123:108]; |
|
//------------------------------------------------------------ |
// Clock #3 |
142,10 → 142,10
// - shift mantissa if required. |
//------------------------------------------------------------ |
`ifdef MIN_LATENCY |
assign so = i[119:116]; |
assign so = i[131:128]; |
assign xo = xo2; |
`else |
delay3 #(4) u21 (.clk(clk), .ce(ce), .i(i[119:116]), .o(so)); |
delay3 #(4) u21 (.clk(clk), .ce(ce), .i(i[131:128]), .o(so)); |
delay1 #(16) u22 (.clk(clk), .ce(ce), .i(xo2), .o(xo)); |
`endif |
|
152,13 → 152,13
always @`PIPE_ADV |
if (ce) |
casez({rnd2,xo2==16'h9999,carry2,dn2}) |
4'b0??0: mo <= mo1[95:0]; // not rounding, not denormalized |
4'b0??1: mo <= mo1[95:0]; // not rounding, denormalized |
4'b1000: mo <= rounded2[95: 0]; // exponent didn't change, number was normalized |
4'b1001: mo <= rounded2[95: 0]; // exponent didn't change, but number was denormalized |
4'b1010: mo <= {4'h1,rounded2[95: 4]}; // exponent incremented (new MSD generated), number was normalized |
4'b1011: mo <= rounded2[95:0]; // exponent incremented (new MSB generated), number was denormalized, number became normalized |
4'b11??: mo <= 96'd0; // number became infinite, no need to check carry etc., rnd would be zero if input was NaN or infinite |
4'b0??0: mo <= mo1[107:0]; // not rounding, not denormalized |
4'b0??1: mo <= mo1[107:0]; // not rounding, denormalized |
4'b1000: mo <= rounded2[107: 0]; // exponent didn't change, number was normalized |
4'b1001: mo <= rounded2[107: 0]; // exponent didn't change, but number was denormalized |
4'b1010: mo <= {4'h1,rounded2[107: 4]}; // exponent incremented (new MSD generated), number was normalized |
4'b1011: mo <= rounded2[107:0]; // exponent incremented (new MSB generated), number was denormalized, number became normalized |
4'b11??: mo <= 108'd0; // number became infinite, no need to check carry etc., rnd would be zero if input was NaN or infinite |
endcase |
|
endmodule |