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Rev 35 → Rev 36

/posit_test_bench/intToPosit_tb.v
0,0 → 1,63
`timescale 1ns / 1ps
module intToPosit_tb_v;
 
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
 
parameter N=32;
parameter E=8;
parameter Bs=log2(N);
parameter es = 4;
 
reg clk;
reg [5:0] cnt;
 
wire [N-1:0] out;
 
reg [N-1:0] a;
 
// Instantiate the Unit Under Test (UUT)
intToPosit #(.PSTWID(N), .es(es)) u2 (.i(a), .o(out));
 
//FP_to_posit #(.N(32), .E(8), .es(es)) u3 (in, out3);
//Posit_to_FP #(.N(32), .E(8), .es(es)) u5 (out, out3);
 
 
initial begin
a = $urandom(1);
// Initialize Inputs
clk = 1;
cnt = 0;
// Wait 100 ns for global reset to finish
#325150
$fclose(outfile);
$finish;
end
always #5 clk=~clk;
always @(posedge clk) begin
a = $urandom();
cnt = cnt + 1;
case (cnt)
1: a = 8192;
2: a = 10;
3: a = -1;
4: a = -10;
default: a = $urandom();
endcase
end
 
integer outfile;
initial outfile = $fopen("d:/cores5/Gambit/v5/rtl/cpu/fpu/test_bench/intToPosit_tvo32.txt", "wb");
always @(negedge clk) begin
$fwrite(outfile, "%d\t%h\n",a,out);
end
 
endmodule
 
/posit_test_bench/positAddsub_tb.v
0,0 → 1,113
`timescale 1ns / 1ps
module positAddsub_tb_v;
 
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
 
parameter N=52;
parameter E=8;
parameter Bs=log2(N);
parameter es = 4;
 
reg [N-1:0] in;
reg clk;
reg [5:0] cnt;
 
wire [N-1:0] out, out2, out3;
 
reg [N-1:0] a1, b1;
wire [N-1:0] a, b;
wire [N-1:0] psum, fsum, fa, fb, ad, bd, psumd, out2d, psum1;
 
// Instantiate the Unit Under Test (UUT)
 
intToPosit #(.PSTWID(N), .es(es)) u1a (.i(a1), .o(a));
intToPosit #(.PSTWID(N), .es(es)) u1b (.i(b1), .o(b));
positToFp #(.FPWID(N), .PSTWID(N), .es(es)) u2
(
.i(a),
.o(fa)
);
 
positToFp #(.FPWID(N), .PSTWID(N), .es(es)) u3
(
.i(b),
.o(fb)
);
 
positAddsub #(.PSTWID(N), .es(es)) uadd1 (1'b0,a,b,psum);
fpAddsub #(.FPWID(N)) uadd2 (clk,1'b1,3'd0,1'b0,fa,fb,fsum);
posit_add #(.N(N),.es(es)) uadd3 (a, b, 1'b1, psum1);
 
positToFp #(.FPWID(N), .PSTWID(N), .es(es)) u4
(
.i(psum),
.o(out2)
);
 
 
delay2 #(N) ud1 (.i(a), .o(ad));
delay2 #(N) ud2 (.i(a), .o(bd));
delay2 #(N) ud3 (.i(psum), .o(psumd));
delay2 #(N) ud4 (.i(out2), .o(out2d));
 
 
//FP_to_posit #(.N(32), .E(8), .es(es)) u3 (in, out3);
//Posit_to_FP #(.N(32), .E(8), .es(es)) u5 (out, out3);
 
 
initial begin
a1 = $urandom(1);
b1 = $urandom(2);
cnt = 0;
// Initialize Inputs
clk = 1;
// Wait 100 ns for global reset to finish
#101 in = 32'h0080ffff;
#325150
$fclose(outfile);
$finish;
end
always #5 clk=~clk;
always @(posedge clk) begin
cnt = cnt + 1;
case(cnt)
0:
begin
a1 = 0;
b1 = 0;
end
1:
begin
a1 = 0;
b1 = 10;
end
2:
begin
a1 = 10;
b1 = 10;
end
default:
begin
a1 = $urandom();
b1 = $urandom();
end
endcase
end
 
integer outfile;
initial outfile = $fopen("d:/cores5/Gambit/v5/rtl/cpu/fpu/test_bench/positAddsub_tvo32.txt", "wb");
always @(negedge clk) begin
$fwrite(outfile, "%h\t%h\t%h\t%h\n",a,b,psum,psum1);
end
 
endmodule
 
/posit_test_bench/positToFp_tb.sv
0,0 → 1,55
`timescale 1ns / 1ps
module positToFp_tb;
 
function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
 
parameter N=32;
parameter E=8;
parameter Bs=log2(N);
parameter es = 3;
 
reg [N-1:0] in;
reg clk;
 
wire [N-1:0] out;
 
// Instantiate the Unit Under Test (UUT)
positToFp #(.FPWID(N), .PSTWID(N), .es(es)) u1 (
.i(in),
.o(out)
);
 
 
initial begin
// Initialize Inputs
clk = 1;
// Wait 100 ns for global reset to finish
#101 in = 65535;
 
#655360
 
$fclose(outfile);
$finish;
end
always #5 clk=~clk;
always @(posedge clk) begin
if (in < 32'hffffffff)
in <= in + 65535;
end
 
integer outfile;
initial outfile = $fopen("d:/cores5/Gambit/v5/rtl/cpu/fpu/test_bench/positToFp_tvo32.txt", "wb");
always @(negedge clk) begin
$fwrite(outfile, "%h\t%h\n",in,out);
end
 
endmodule
 
/rtl/positVerilog/fpToPosit.sv
0,0 → 1,114
// ============================================================================
// __
// \\__/ o\ (C) 2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// fpToPosit.v
// - floating point to posit number convertor
// - can issue every clock cycle
// - parameterized width
// - IEEE 754 representation
//
// Parts of this code originated from FP_to_Posit.v by Manish Kumar Jaiswal
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
 
`include "positConfig.sv"
`include "fpConfig.sv"
`include "fpTypes.sv"
 
module fpToPosit(i, o);
parameter FPWID = 32;
`include "fpSize.sv"
`include "positSize.sv"
input [FPWID-1:0] i;
output reg [FPWID-1:0] o;
 
parameter BIAS = {1'b0,{EMSB{1'b1}}};
localparam N = FPWID;
localparam E = EMSB+1;
localparam Bs = $clog2(FPWID-1);
 
// operands sign,exponent,significand
wire sa;
wire [EMSB:0] xa;
wire [FMSB:0] ma;
wire [FMSB+1:0] fracta;
wire adn;
wire az;
wire xainf;
wire aInf;
wire aNan;
 
fpDecomp #(FPWID) u1 (.i(i), .sgn(sa), .exp(xa), .man(ma), .fract(fracta), .xz(adn), .vz(az), .xinf(xaInf), .inf(aInf), .nan(aNan) );
assign sgno = sa;
wire [$clog2(FMSB+1):0] lzcnt;
generate begin : gCntlz
case(FPWID)
16: begin cntlz16 u2 ({fracta,5'h1f},lzcnt); end //1-5-10
20: begin cntlz16 u2 ({fracta,2'h3},lzcnt); end //1-6-13
32: begin cntlz32 u2 ({fracta,8'hFF},lzcnt); end // 1-8-23
40: begin cntlz32 u2 ({fracta,2'h3},lzcnt); end // 1-10-29
52: begin cntlz48 u2 ({fracta,7'h7F},lzcnt); end // 1-11-40
64: begin cntlz64 u2 ({fracta,11'h7FF},lzcnt); end // 1-11-52
80: begin cntlz80 u2 ({fracta,15'h7FFF},lzcnt); end // 1-15-64
default:
always @*
begin
$display("fpToPosit: Unsupported size");
$finish;
end
endcase
end
endgenerate
 
wire [N-1:0] sig_tmp = {fracta,{E{1'b0}}} << lzcnt;
 
// Convert exponent to twos complement from BIAS offset
wire [E:0] exp = xa - BIAS - lzcnt;
wire sxp = exp[E]; // get exponent sign
wire [E:0] absexp = sxp ? -exp : exp; // get absolute value
wire [es-1:0] e_o = (sxp & |absexp[es-1:0]) ? exp[es-1:0] : absexp[es-1:0];
wire [E-es-1:0] r_o = (~sxp || (sxp & |absexp[es-1:0])) ? {{Bs{1'b0}},absexp[E-1:es]} + 1'b1 : {{Bs{1'b0}},absexp[E-1:es]};
// Exponent and Significand Packing
wire [2*N-1:0] tmp = {{N{~sxp}},sxp,e_o,sig_tmp[N-2:es]};
 
// Including Regime bits in Exponent-Significand Packing
wire [Bs-1:0] diff_b;
 
generate begin : gDiffb
if (E-es > Bs)
assign diff_b = |r_o[E-es-1:Bs] ? {{(Bs-2){1'b1}},2'b01} : r_o[Bs-1:0];
else
assign diff_b = r_o;
end
endgenerate
 
wire [2*N-1:0] tmp1 = tmp >> diff_b;
wire [N-1:0] tmp1s = sa ? -tmp1[N-1:0] : tmp1[N-1:0];
 
always @*
casez({az,aInf,aNan,~sig_tmp[N-1]})
4'b1???: o = {FPWID{1'b0}};
4'b01??: o = {1'b1,{FPWID-1{1'b0}}};
4'b001?: o = {1'b1,{FPWID-1{1'b0}}};
4'b0001: o = {1'b1,{FPWID-1{1'b0}}};
default: o = {sa,tmp1s[N-1:1]};
endcase
 
endmodule
/rtl/positVerilog/intToPosit.sv
0,0 → 1,90
// ============================================================================
// __
// \\__/ o\ (C) 2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// intToPosit.sv
// - integer to posit number converter
// - parameterized width
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
 
`include "positConfig.sv"
 
module intToPosit(i, o);
`include "positSize.sv"
localparam rs = $clog2(PSTWID-1);
localparam lzs = $clog2(PSTWID-2);
input [PSTWID-1:0] i;
output [PSTWID-1:0] o;
 
wire [PSTWID*2-1+es+3-2:0] tmp, tmp1;
wire [PSTWID-2:0] ii = i[PSTWID-1] ? -i : i;
 
wire [lzs:0] lzcnt;
wire [PSTWID-1:0] rnd_ulp, tmp2, tmp2_rnd_ulp;
 
integer n;
positCntlz #(.PSTWID(PSTWID)) u1 (.i(ii[PSTWID-2:0]), .o(lzcnt));
 
wire sgn = i[PSTWID-1];
wire [rs:0] rgm = (PSTWID - (lzcnt + 2)) >> es;
wire [PSTWID-3:0] sig = ii << lzcnt; // left align significand, chop off leading one
generate begin : gExpandedPosit
// The number is represented as 1.x so for an integer it
// always needs to be left shifted.
// Add three trailers for guard, round and sticky.
if (es > 0) begin
// exp = lzcnt mod (2**es)
// remember es is constant so there are no shifts really
wire [es-1:0] exp = (PSTWID - (lzcnt + 2)) & {es{1'b1}};
assign tmp = {{{PSTWID-1{1'b1}},1'b0},exp,sig,3'b0};
end
else
assign tmp = {{{PSTWID-1{1'b1}},1'b0},sig,3'b0};
end
endgenerate
// Compute regime shift amount = number of bits to represent regime
// Need one extra bit for the terminator, and one extra '1' bit.
wire [rs:0] rgm_sh = rgm + 2'd2;
assign tmp1 = tmp >> rgm_sh;
wire L = tmp[rgm_sh-0+es];
wire G = tmp[rgm_sh-1+es];
wire R = tmp[rgm_sh-2+es];
reg S;
wire ulp;
always @*
begin
S = 0;
for (n = 0; n < PSTWID; n = n + 1) begin
if (n < rgm_sh - 2 + es)
S = S | tmp[n];
end
end
 
// Extract the bits representing the number, note leave off sign bit
assign tmp2 = tmp1[PSTWID-3+es+3:es+2];
// Round
assign ulp = ((G & (R | S)) | (L & G & ~(R | S)));
assign rnd_ulp = {{PSTWID-1{1'b0}},ulp};
assign tmp2_rnd_ulp = tmp2 + rnd_ulp;
// Final output
assign o = i=={PSTWID{1'b0}} ? {PSTWID{1'b0}} : sgn ? -tmp2_rnd_ulp : tmp2_rnd_ulp;
 
endmodule
/rtl/positVerilog/positAddsub.sv
0,0 → 1,192
// ============================================================================
// __
// \\__/ o\ (C) 2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// positAddsub.v
// - posit number adder/subtracter
// - parameterized width
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
 
`include "positConfig.sv"
 
module positAddsub(op, a, b, o);
`include "positSize.sv"
localparam rs = $clog2(PSTWID-1)-1;
input op;
input [PSTWID-1:0] a;
input [PSTWID-1:0] b;
output reg [PSTWID-1:0] o;
 
wire sa, sb;
reg so;
wire rop;
wire [rs:0] rgma, rgmb, rgm1, rgm2, argm1, argm2;
wire rgsa, rgsb, rgs1, rgs2;
wire [rs+es+1:0] diff;
wire [es-1:0] expa, expb, exp1, exp2;
wire [PSTWID-es-1:0] siga, sigb, sig1, sig2;
wire zera, zerb;
wire infa, infb;
wire [PSTWID-1:0] aa, bb;
wire inf = infa|infb;
wire zero = zera & zerb;
 
positDecompose #(PSTWID,es) u1 (
.i(a),
.sgn(sa),
.rgs(rgsa),
.rgm(rgma),
.exp(expa),
.sig(siga),
.zer(zera),
.inf(infa)
);
 
positDecompose #(PSTWID,es) u2 (
.i(b),
.sgn(sb),
.rgs(rgsb),
.rgm(rgmb),
.exp(expb),
.sig(sigb),
.zer(zerb),
.inf(infb)
);
 
assign aa = sa ? -a : a;
assign bb = sb ? -b : b;
 
wire aa_gt_bb = aa >= bb;
// Determine op really wanted
assign rop = sa ^ sb ^ op;
// Sort operand components
assign rgs1 = aa_gt_bb ? rgsa : rgsb;
assign rgs2 = aa_gt_bb ? rgsb : rgsa;
assign rgm1 = aa_gt_bb ? rgma : rgmb;
assign rgm2 = aa_gt_bb ? rgmb : rgma;
assign exp1 = aa_gt_bb ? expa : expb;
assign exp2 = aa_gt_bb ? expb : expa;
assign sig1 = aa_gt_bb ? siga : sigb;
assign sig2 = aa_gt_bb ? sigb : siga;
 
assign argm1 = rgs1 ? rgm1 : -rgm1;
assign argm2 = rgs2 ? rgm2 : -rgm2;
 
assign diff = {argm1,exp1} - {argm2,exp2};
wire [rs-1:0] exp_diff = (|diff[es+rs:rs]) ? {rs{1'b1}} : diff[rs-1:0];
wire [PSTWID*2-1:0] sig2s = {sig2,{PSTWID{1'b0}}} >> exp_diff;
wire [PSTWID*2-1:0] sig1s = {sig1,{PSTWID{1'b0}}};
wire [PSTWID*2:0] sig_sd = rop ? sig1s - sig2s : sig1s + sig2s;
wire [1:0] sigov = sig_sd[PSTWID*2:PSTWID*2-1];
 
wire [$clog2(PSTWID-1):0] lzcnt;
wire [PSTWID-1:0] sigi = {|sigov,sig_sd[PSTWID*2-2:PSTWID]};
generate begin : gClz
case(PSTWID)
16: cntlz16 u1 (.i({sigi}), .o(lzcnt));
20: cntlz24 u1 (.i({sigi,4'hF}), .o(lzcnt));
32: cntlz32 u1 (.i({sigi}), .o(lzcnt));
40: cntlz48 u1 (.i({sigi,8'hFF}), .o(lzcnt));
52: cntlz64 u1 (.i({sigi,12'hFFF}), .o(lzcnt));
64: cntlz64 u1 (.i({sigi}), .o(lzcnt));
80: cntlz80 u1 (.i({sigi}), .o(lzcnt));
default: ;
endcase
end
endgenerate
 
//positCntlz #(.PSTWID(PSTWID)) u3 (.i({|sigov,sig_sd[PSTWID-2:0]}), .o(lzcnt));
wire [PSTWID*2-1:0] sig_ls = sig_sd[PSTWID*2-1:0] << lzcnt;
 
wire [rs:0] absrgm1 = rgs1 ? rgm1 : -rgm1; // rgs1 = 1 = positive
wire [es+rs+1:0] rxtmp;
wire [es+rs+1:0] rxtmp1;
wire srxtmp1;
wire [es+rs:0] abs_rxtmp;
wire [(es==0 ? 0 : es-1):0] expo;
wire [rs:0] rgmo;
generate begin : gEsz
if (es > 0) begin
assign rxtmp = {absrgm1,exp1} - {{es+1{1'b0}},lzcnt-es};
assign rxtmp1 = rxtmp + sigov[1]; // add in overflow if any
assign srxtmp1 = rxtmp1[es+rs+1];
assign abs_rxtmp = srxtmp1 ? -rxtmp1 : rxtmp1;
 
assign expo = (srxtmp1 & |abs_rxtmp[es-1:0]) ? rxtmp1[es-1:0] : abs_rxtmp[es-1:0];
assign rgmo = (~srxtmp1 || (srxtmp1 & |abs_rxtmp[es-1:0])) ? abs_rxtmp[es+rs:es] + 1'b1 : abs_rxtmp[es+rs:es];
end
else begin
assign rxtmp = absrgm1 - {{1{1'b0}},lzcnt};
assign rxtmp1 = rxtmp + sigov[1]; // add in overflow if any
assign srxtmp1 = rxtmp1[rs+1];
assign abs_rxtmp = srxtmp1 ? -rxtmp1 : rxtmp1;
assign expo = 1'b0;
assign rgmo = (~srxtmp1) ? abs_rxtmp[rs:0] + 1'b1 : abs_rxtmp[rs:0];
end
end
endgenerate
 
// Exponent and Significand Packing
reg [2*PSTWID-1+3:0] tmp;
always @*
case(es)
0: tmp = { {PSTWID{~srxtmp1}}, srxtmp1, sig_ls[PSTWID*2-2:PSTWID-2], |sig_ls[PSTWID-3:0]};
1: tmp = { {PSTWID{~srxtmp1}}, srxtmp1, expo, sig_ls[PSTWID*2-2:PSTWID-1], |sig_ls[PSTWID-2:0]};
2: tmp = { {PSTWID{~srxtmp1}}, srxtmp1, expo, sig_ls[PSTWID*2-2:PSTWID], |sig_ls[PSTWID-1:0]};
default: tmp = { {PSTWID{~srxtmp1}}, srxtmp1, expo, sig_ls[PSTWID*2-2:PSTWID+es-2], |sig_ls[PSTWID-1+es-2:0]};
endcase
 
wire [3*PSTWID-1+3:0] tmp1 = {tmp,{PSTWID{1'b0}}} >> rgmo;
 
// Rounding
// Gaurd, Round, and Sticky
wire L = tmp1[PSTWID+4], G = tmp1[PSTWID+3], R = tmp1[PSTWID+2], St = |tmp1[PSTWID+1:0],
ulp = ((G & (R | St)) | (L & G & ~(R | St)));
wire [PSTWID-1:0] rnd_ulp = {{PSTWID-1{1'b0}},ulp};
 
wire [PSTWID:0] tmp1_rnd_ulp = tmp1[2*PSTWID-1+3:PSTWID+3] + rnd_ulp;
wire [PSTWID-1:0] tmp1_rnd = (rgmo < PSTWID-es-2) ? tmp1_rnd_ulp[PSTWID-1:0] : tmp1[2*PSTWID-1+3:PSTWID+3];
 
// Compute output sign
always @*
casez ({zero,sa,op,sb})
4'b0000: so = 1'b0; // + + + = +
4'b0001: so = !aa_gt_bb; // + + - = sign of larger
4'b0010: so = !aa_gt_bb; // + - + = sign of larger
4'b0011: so = 1'b0; // + - - = +
4'b0100: so = aa_gt_bb; // - + + = sign of larger
4'b0101: so = 1'b1; // - + - = -
4'b0110: so = 1'b1; // - - + = -
4'b0111: so = aa_gt_bb; // - - - = sign of larger
4'b1???: so = 1'b0;
endcase
 
wire [PSTWID-1:0] abs_tmp = so ? -tmp1_rnd : tmp1_rnd;
 
always @*
casez({zero,inf,sig_ls[PSTWID]})
3'b1??: o = {PSTWID{1'b0}};
3'b01?: o = {1'b1,{PSTWID-1{1'b0}}};
3'b001: o = {PSTWID{1'b0}};
default: o = {so, abs_tmp[PSTWID-1:1]};
endcase
 
endmodule
/rtl/positVerilog/positCntlo.sv
0,0 → 1,45
`include "positConfig.sv"
// ============================================================================
// __
// \\__/ o\ (C) 2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// positCntlo.sv
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
module positCntlo(i, o);
parameter PSTWID = `PSTWID;
input [PSTWID-2:0] i;
output [$clog2(PSTWID-2):0] o;
 
generate begin : gClz
case(PSTWID)
16: cntlo16 u1 (.i({i,1'b1}), .o(o));
20: cntlo24 u1 (.i({i,1'b1,4'hF}), .o(o));
32: cntlo32 u1 (.i({i,1'b1}), .o(o));
40: cntlo48 u1 (.i({i,1'b1,8'hFF}), .o(o));
52: cntlo64 u1 (.i({i,1'b1,12'hFFF}), .o(o));
64: cntlo64 u1 (.i({i,1'b1}), .o(o));
80: cntlo80 u1 (.i({i,1'b1}), .o(o));
default: ;
endcase
end
endgenerate
 
endmodule
/rtl/positVerilog/positCntlz.sv
0,0 → 1,45
`include "positConfig.sv"
// ============================================================================
// __
// \\__/ o\ (C) 2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// positCntlz.sv
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
module positCntlz(i, o);
parameter PSTWID = `PSTWID;
input [PSTWID-2:0] i;
output [$clog2(PSTWID-2):0] o;
 
generate begin : gClz
case(PSTWID)
16: cntlz16 u1 (.i({i,1'b1}), .o(o));
20: cntlz24 u1 (.i({i,1'b1,4'hF}), .o(o));
32: cntlz32 u1 (.i({i,1'b1}), .o(o));
40: cntlz48 u1 (.i({i,1'b1,8'hFF}), .o(o));
52: cntlz64 u1 (.i({i,1'b1,12'hFFF}), .o(o));
64: cntlz64 u1 (.i({i,1'b1}), .o(o));
80: cntlz80 u1 (.i({i,1'b1}), .o(o));
default: ;
endcase
end
endgenerate
 
endmodule
/rtl/positVerilog/positConfig.sv
0,0 → 1,30
// ============================================================================
// __
// \\__/ o\ (C) 2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// positConfig.sv
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
`ifndef POSIT_CONFIG_SV
`define POSIT_CONFIG_SV 1
 
`define PSTWID 32
 
`endif
/rtl/positVerilog/positDecompose.sv
0,0 → 1,96
`include "positConfig.sv"
// ============================================================================
// __
// \\__/ o\ (C) 2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// positDecompose.sv
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
`include "positConfig.sv"
 
// Decompose a posit number.
module positDecompose(i, sgn, rgs, rgm, exp, sig, zer, inf);
`include "positSize.sv"
input [PSTWID-1:0] i;
output sgn; // sign of number
output rgs; // sign of regime
output [$clog2(PSTWID)-1:0] rgm; // regime (absolute value)
output [es-1:0] exp; // exponent
output [PSTWID-es-1:0] sig; // significand
output zer; // number is zero
output inf; // number is infinite
 
wire [$clog2(PSTWID-2):0] lzcnt;
wire [$clog2(PSTWID-2):0] locnt;
 
 
assign sgn = i[PSTWID-1];
assign inf = ~|i[PSTWID-2:0] & i[PSTWID-1];
assign zer = ~|i;
wire [PSTWID-1:0] ii = sgn ? -i : i;
assign rgs = ii[PSTWID-2];
 
positCntlz #(PSTWID) u1 (.i(ii[PSTWID-2:0]), .o(lzcnt));
positCntlo #(PSTWID) u2 (.i(ii[PSTWID-2:0]), .o(locnt));
 
assign rgm = rgs ? locnt - 1 : lzcnt;
wire [$clog2(PSTWID)-1:0] shamt = rgs ? locnt + 2'd1 : lzcnt + 2'd1;
wire [PSTWID-1:0] tmp = ii << shamt;
assign exp = |es ? tmp[PSTWID-2:PSTWID-1-es] : 0;
assign sig = {~zer,tmp[PSTWID-2-es:0]};
 
endmodule
 
// Decompose posit number and register outputs.
module positDecomposeReg(clk, ce, i, sgn, rgs, rgm, exp, sig, zer, inf);
`include "positSize.sv"
input clk;
input ce;
input [PSTWID-1:0] i;
output reg sgn;
output reg rgs;
output reg [$clog2(PSTWID)-1:0] rgm;
output reg [es-1:0] exp;
output reg [PSTWID-es-1:0] sig;
output reg zer;
output reg inf;
 
wire isgn;
wire irgs;
wire [$clog2(PSTWID)-1:0] irgm;
wire [es-1:0] iexp;
wire [PSTWID-es-1:0] isig;
wire izer;
wire iinf;
 
positDecompose #(PSTWID) u1 (i, isgn, irgs, irgm, iexp, isig, iinf);
 
always @(posedge clk)
if (ce) begin
sgn = isgn;
rgs = irgs;
rgm = irgm;
exp = iexp;
sig = isig;
inf = iinf;
end
 
endmodule
 
/rtl/positVerilog/positSize.sv
0,0 → 1,12
parameter PSTWID = `PSTWID;
parameter es =
PSTWID >= 80 ? 4 :
PSTWID >= 64 ? 3 :
PSTWID >= 52 ? 3 :
PSTWID >= 40 ? 3 :
PSTWID >= 32 ? 2 :
PSTWID >= 24 ? 2 :
PSTWID >= 16 ? 1 :
PSTWID >= 8 ? 1 :
0 ;
 
/rtl/positVerilog/positToFp.sv
0,0 → 1,75
// ============================================================================
// __
// \\__/ o\ (C) 2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// positToFp.v
// - posit number to floating point convertor
// - can issue every clock cycle
// - parameterized width
// - IEEE 754 representation
//
// Parts of this code originated from Posit_to_FP.v by Manish Kumar Jaiswal
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
 
`include "positConfig.sv"
`include "fpConfig.sv"
`include "fpTypes.sv"
 
module positToFp(i, o);
parameter FPWID = 32;
`include "fpSize.sv"
`include "positSize.sv"
input [FPWID-1:0] i;
output reg [FPWID-1:0] o;
 
parameter BIAS = {1'b0,{EMSB{1'b1}}};
localparam N = FPWID;
localparam E = EMSB+1;
localparam M = FMSB+1;
localparam Bs = $clog2(FPWID-1);
localparam EO = E > es+Bs ? E : es+Bs;
 
wire sgn;
wire rgs;
wire [Bs-1:0] rgm;
wire [es-1:0] exp;
wire [N-es-1:0] sig;
wire zer;
wire inf;
 
positDecompose #(.PSTWID(PSTWID), .es(es)) u1 (.i(i), .sgn(sgn), .rgs(rgs), .rgm(rgm), .exp(exp), .sig(sig), .zer(zer), .inf(inf));
 
wire [N-1:0] m = {sig,{es{1'b0}}};
wire [EO+1:0] e;
assign e = {(rgs ? {{EO-es-Bs+1{1'b0}},rgm} : -{{EO-es-Bs+1{1'b0}},rgm}),exp} + BIAS;
wire exv = |e[EO:E];
wire exinf = &e[E-1:0];
 
always @*
casez({zer,inf|exv|exinf}) // exponent all ones or exponent overflow?
// convert to +0.0 zero-in zero-out (the sign will always be plus)
2'b1?: o = {sgn,{FPWID-1{1'b0}}};
// Infinity in or exponent overflow in conversion = infinity out
2'b01: o = {sgn,{E-1{1'b1}},{M{1'b0}}};
// Other numbers
default: o = {sgn,e[E-1:0],m[N-2:E]};
endcase
 
endmodule
/rtl/positVerilog/positTypes.sv
0,0 → 1,2
 
typedef logic [FPWID-1:0] tPosit;

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