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/rtl/verilog2/DFPAddsub128.sv
0,0 → 1,432
// ============================================================================
// __
// \\__/ o\ (C) 2020-2021 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DFPAddsub.sv
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
 
import DFPPkg::*;
 
module DFPAddsub128(clk, ce, rm, op, a, b, o);
input clk;
input ce;
input [2:0] rm;
input op;
input DFP128 a;
input DFP128 b;
output DFP128UD o;
localparam N=34; // number of BCD digits
 
parameter TRUE = 1'b1;
parameter FALSE = 1'b0;
 
DFP128U au;
DFP128U bu;
wire sa, sb;
wire sxa, sxb;
wire adn, bdn;
wire xainf, xbinf;
wire ainf, binf;
wire aNan, bNan;
wire [13:0] xa, xb;
wire [N*4-1:0] siga, sigb;
 
DFPUnpack128 u00 (a, au);
DFPUnpack128 u01 (b, bu);
 
wire [(N+1)*4-1:0] oss10;
wire oss10c;
 
BCDAddN #(.N(N+1)) ubcdan1
(
.ci(1'b0),
.a(oaa10),
.b(obb10),
.o(oss10),
.co(oss10c)
);
 
wire [(N+1)*4-1:0] odd10;
wire odd10c;
 
BCDSubN #(.N(N+1)) ubcdsn1
(
.ci(1'b0),
.a(oaa10),
.b(obb10),
.o(odd10),
.co(odd10c)
);
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Clock #1
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
reg op1;
reg az, bz;
always @(posedge clk)
op1 <= op;
always @(posedge clk)
az <= au.sig==136'd0 && au.exp==14'd0;
always @(posedge clk)
bz <= bu.sig==136'd0 && bu.exp==14'd0;
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Clock #2
//
// Figure out which operation is really needed an add or subtract ?
// If the signs are the same, use the orignal op,
// otherwise flip the operation
// a + b = add,+
// a + -b = sub, so of larger
// -a + b = sub, so of larger
// -a + -b = add,-
// a - b = sub, so of larger
// a - -b = add,+
// -a - b = add,-
// -a - -b = sub, so of larger
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
reg realOp2;
reg op2;
reg [15:0] xa2, xb2;
reg az2, bz2;
reg xa_gt_xb2;
reg [N*4-1:0] siga2, sigb2;
reg sigeq, siga_gt_sigb;
reg xa_gt_xb2;
reg expeq;
reg sxo2;
 
always @(posedge clk)
if (ce) realOp2 = op1 ^ au.sign ^ bu.sign;
always @(posedge clk)
if (ce) op2 <= op1;
always @(posedge clk)
if (ce) xa2 <= au.exp;
always @(posedge clk)
if (ce) xb2 <= bu.exp;
always @(posedge clk)
if (ce) siga2 <= au.sig;
always @(posedge clk)
if (ce) sigb2 <= bu.sig;
always @(posedge clk)
if (ce) az2 <= az;
always @(posedge clk)
if (ce) bz2 <= bz;
always @(posedge clk)
if (ce)
xa_gt_xb2 <= au.exp > bu.exp;
 
always @(posedge clk)
if (ce) sigeq <= au.sig==bu.sig;
always @(posedge clk)
if (ce) siga_gt_sigb <= au.sig > bu.sig;
always @(posedge clk)
if (ce) expeq <= au.exp==bu.exp;
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Clock #3
//
// Find out if the result will be zero.
// Determine which fraction to denormalize
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
//
reg [13:0] xa3, xb3;
reg resZero3;
wire xaInf3, xbInf3;
reg xa_gt_xb3;
reg a_gt_b3;
reg op3;
wire sa3, sb3;
wire [2:0] rm3;
reg [N*4-1:0] mfs3;
 
always @(posedge clk)
if (ce) resZero3 <= (realOp2 & expeq & sigeq) || // subtract, same magnitude
(az2 & bz2); // both a,b zero
always @(posedge clk)
if (ce) xa3 <= xa2;
always @(posedge clk)
if (ce) xb3 <= xb2;
always @(posedge clk)
if (ce) xa_gt_xb3 <= xa_gt_xb2;
always @(posedge clk)
if (ce) a_gt_b3 <= xa_gt_xb2 | (expeq & siga_gt_sigb);
always @(posedge clk)
if (ce) op3 <= op2;
always @(posedge clk)
if (ce) mfs3 = xa_gt_xb2 ? sigb2 : siga2;
 
delay #(.WID(1), .DEP(2)) udly3c (.clk(clk), .ce(ce), .i(au.sign), .o(sa3));
delay #(.WID(1), .DEP(2)) udly3d (.clk(clk), .ce(ce), .i(bu.sign), .o(sb3));
delay #(.WID(3), .DEP(3)) udly3e (.clk(clk), .ce(ce), .i(rm), .o(rm3));
delay #(.WID(1), .DEP(2)) udly3f (.clk(clk), .ce(ce), .i(aInf), .o(aInf3));
delay #(.WID(1), .DEP(2)) udly3g (.clk(clk), .ce(ce), .i(bInf), .o(bInf3));
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Clock #4
//
// Compute output exponent
//
// The output exponent is the larger of the two exponents,
// unless a subtract operation is in progress and the two
// numbers are equal, in which case the exponent should be
// zero.
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 
reg [13:0] xa4, xb4;
reg [13:0] xo4;
reg xa_gt_xb4;
 
always @(posedge clk)
if (ce) xa4 <= xa3;
always @(posedge clk)
if (ce) xb4 <= xb3;
always @(posedge clk)
if (ce) xo4 <= resZero3 ? 14'd0 : xa_gt_xb3 ? xa3 : xb3;
always @(posedge clk)
if (ce) xa_gt_xb4 <= xa_gt_xb3;
 
// Compute output sign
reg so4;
always @*
case ({resZero3,sa3,op3,sb3}) // synopsys full_case parallel_case
4'b0000: so4 <= 0; // + + + = +
4'b0001: so4 <= !a_gt_b3; // + + - = sign of larger
4'b0010: so4 <= !a_gt_b3; // + - + = sign of larger
4'b0011: so4 <= 0; // + - - = +
4'b0100: so4 <= a_gt_b3; // - + + = sign of larger
4'b0101: so4 <= 1; // - + - = -
4'b0110: so4 <= 1; // - - + = -
4'b0111: so4 <= a_gt_b3; // - - - = sign of larger
4'b1000: so4 <= 0; // A + B, sign = +
4'b1001: so4 <= (rm3==3'd3); // A + -B, sign = + unless rounding down
4'b1010: so4 <= (rm3==3'd3); // A - B, sign = + unless rounding down
4'b1011: so4 <= 0; // A - -B, sign = +
4'b1100: so4 <= (rm3==3'd3); // -A - -B, sign = + unless rounding down
4'b1101: so4 <= 1; // -A + -B, sign = -
4'b1110: so4 <= 1; // -A - +B, sign = -
4'b1111: so4 <= (rm3==3'd3); // A - B, sign = + unless rounding down
endcase
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Clock #5
//
// Compute the difference in exponents, provides shift amount
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
reg [13:0] xdiff5;
always @(posedge clk)
if (ce) xdiff5 <= xa_gt_xb4 ? xa4 - xb4 : xb4 - xa4;
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Clock #6
//
// Compute the difference in exponents, provides shift amount
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// If the difference in the exponent is 24 or greater (assuming 24 nybble dfp or
// less) then all of the bits will be shifted out to zero. There is no need to
// keep track of a difference more than 24.
reg [6:0] xdif6;
wire [N*4-1:0] mfs6;
always @(posedge clk)
if (ce) xdif6 <= xdiff5 > N ? N : xdiff5[6:0];
delay #(.WID(N*4), .DEP(3)) udly6a (.clk(clk), .ce(ce), .i(mfs3), .o(mfs6));
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Clock #7
//
// Determine the sticky bit. The sticky bit is the bitwise or of all the bits
// being shifted out the right side. The sticky bit is computed here to
// reduce the number of regs required.
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
reg sticky6;
wire sticky7;
wire [7:0] xdif7;
wire [N*4-1:0] mfs7;
wire [8:0] xdif6a = {xdif6,2'b00}; // *4
integer n;
always @* begin
sticky6 = 1'b0;
for (n = 0; n < N*4; n = n + 4)
if (n <= xdif6a)
sticky6 = sticky6| mfs6[n]|mfs6[n+1]|mfs6[n+2]|mfs6[n+3]; // non-zero nybble
end
 
// register inputs to shifter and shift
delay1 #(1) d16(.clk(clk), .ce(ce), .i(sticky6), .o(sticky7) );
delay1 #(9) d15(.clk(clk), .ce(ce), .i(xdif6a), .o(xdif7) );
delay1 #(N*4) d14(.clk(clk), .ce(ce), .i(mfs6), .o(mfs7) );
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Clock #8
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
reg [(N+1)*4-1:0] md8;
wire [N*4-1:0] siga8, sigb8;
wire xa_gt_xb8;
wire a_gt_b8;
always @(posedge clk)
if (ce) md8 <= ({mfs7,4'b0} >> xdif7)|sticky7; // xdif7 is a multiple of four
 
// sync control signals
delay #(.WID(1), .DEP(4)) udly8a (.clk(clk), .ce(ce), .i(xa_gt_xb4), .o(xa_gt_xb8));
delay #(.WID(1), .DEP(5)) udly8b (.clk(clk), .ce(ce), .i(a_gt_b3), .o(a_gt_b8));
delay #(.WID(N*4), .DEP(6)) udly8d (.clk(clk), .ce(ce), .i(siga2), .o(siga8));
delay #(.WID(N*4), .DEP(6)) udly8e (.clk(clk), .ce(ce), .i(sigb2), .o(sigb8));
delay #(.WID(1), .DEP(5)) udly8j (.clk(clk), .ce(ce), .i(op3), .o(op8));
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Clock #9
// Sort operands and perform add/subtract
// addition can generate an extra bit, subtract can't go negative
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
reg [(N+1)*4-1:0] oa9, ob9;
reg a_gt_b9;
always @(posedge clk)
if (ce) oa9 <= xa_gt_xb8 ? {siga8,4'b0} : md8;
always @(posedge clk)
if (ce) ob9 <= xa_gt_xb8 ? md8 : {sigb8,4'b0};
always @(posedge clk)
if (ce) a_gt_b9 <= a_gt_b8;
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Clock #10
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
reg [(N+1)*4-1:0] oaa10;
reg [(N+1)*4-1:0] obb10;
wire realOp10;
reg [13:0] xo10;
 
always @(posedge clk)
if (ce) oaa10 <= a_gt_b9 ? oa9 : ob9;
always @(posedge clk)
if (ce) obb10 <= a_gt_b9 ? ob9 : oa9;
delay #(.WID(1), .DEP(8)) udly10a (.clk(clk), .ce(ce), .i(realOp2), .o(realOp10));
delay #(.WID(14), .DEP(6)) udly10b (.clk(clk), .ce(ce), .i(xo4), .o(xo10));
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Clock #11
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
reg [(N+1)*4-1:0] mab11;
reg mab11c;
wire [N*4-1:0] siga11, sigb11;
wire abInf11;
wire aNan11, bNan11;
reg xoinf11;
wire op11;
 
always @(posedge clk)
if (ce) mab11 <= realOp10 ? odd10 : oss10;
always @(posedge clk)
if (ce) mab11c <= realOp10 ? odd10c : oss10c;
 
delay #(.WID(1), .DEP(8)) udly11a (.clk(clk), .ce(ce), .i(aInf3&bInf3), .o(abInf11));
delay #(.WID(1), .DEP(10)) udly11c (.clk(clk), .ce(ce), .i(aNan), .o(aNan11));
delay #(.WID(1), .DEP(10)) udly11d (.clk(clk), .ce(ce), .i(bNan), .o(bNan11));
delay #(.WID(1), .DEP(3)) udly11e (.clk(clk), .ce(ce), .i(op8), .o(op11));
delay #(.WID(N*4), .DEP(3)) udly11f (.clk(clk), .ce(ce), .i(siga8), .o(siga11));
delay #(.WID(N*4), .DEP(3)) udly11g (.clk(clk), .ce(ce), .i(sigb8), .o(sigb11));
 
always @(posedge clk)
if (ce) xoinf11 <= xo10==14'h3FFF;
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Clock #12
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
reg [(N+1)*4*2-1:0] mo12; // mantissa output
reg nan12;
reg qnan12;
reg infinity12;
wire sxo11;
wire so11;
delay #(.WID(1), .DEP(9)) udly12a (.clk(clk), .ce(ce), .i(sxo2), .o(sxo11));
delay #(.WID(1), .DEP(7)) udly12b (.clk(clk), .ce(ce), .i(so4), .o(so11));
 
always @(posedge clk)
if (ce)
nan12 <= aNan11|bNan11;
 
always @(posedge clk)
if (ce) begin
infinity12 <= 1'b0;
qnan12 <= 1'b0;
casez({abInf11,aNan11,bNan11,xoinf11})
4'b1???: // inf +/- inf - generate QNaN on subtract, inf on add
if (op11) begin
mo12 <= {4'h9,{(N+1)*4*2-4{1'd0}}};
qnan12 <= 1'b1;
end
else begin
mo12 <= {(N+1)*2{4'h9}};
infinity12 <= 1'b1;
end
4'b01??: mo12 <= {4'b0,siga11[107:0],{(N+1)*4{1'd0}}};
4'b001?: mo12 <= {4'b0,sigb11[107:0],{(N+1)*4{1'd0}}};
4'b0001: begin mo12 <= {(N+1)*4*2{1'd0}}; infinity12 <= 1'b1; end
default: mo12 <= {3'b0,mab11c,mab11,{N*4{1'd0}}}; // mab has an extra lead bit and four trailing bits
endcase
end
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Clock #13
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
wire so; // sign output
wire [15:0] xo; // de normalized exponent output
wire [(N+1)*4*2-1:0] mo; // mantissa output
 
delay #(.WID(1), .DEP(1)) u13c (.clk(clk), .ce(ce), .i(nan12), .o(o.nan) );
delay #(.WID(1), .DEP(1)) u13d (.clk(clk), .ce(ce), .i(qnan12), .o(o.qnan) );
delay #(.WID(1), .DEP(1)) u13e (.clk(clk), .ce(ce), .i(infinity12), .o(o.infinity) );
delay #(.WID(1), .DEP(9)) udly13a (.clk(clk), .ce(ce), .i(so4), .o(o.sign));
delay #(.WID(14), .DEP(3)) udly13b (.clk(clk), .ce(ce), .i(xo10), .o(o.exp));
delay #(.WID((N+1)*4*2), .DEP(1)) u13f (.clk(clk), .ce(ce), .i(mo12), .o(o.sig));
delay #(.WID(1), .DEP(1)) udly13g (.clk(clk), .ce(ce), .i(1'b0), .o(o.snan));
 
endmodule
 
 
module DFPAddsub128nr(clk, ce, rm, op, a, b, o);
input clk; // system clock
input ce; // core clock enable
input [2:0] rm; // rounding mode
input op; // operation 0 = add, 1 = subtract
input DFP128 a; // operand a
input DFP128 b; // operand b
output DFP128 o; // output
 
wire DFP128UD o1;
wire DFP128UN fpn0;
 
DFPAddsub128 u1 (clk, ce, rm, op, a, b, o1);
DFPNormalize128 u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
DFPRound128 u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
 
endmodule
/rtl/verilog2/DFPNormalize.sv
227,8 → 227,8
always @(posedge clk)
if (ce)
casez(mo4[(N+1)*4-1:(N-1)*4-1])
8'h00000000: leadingZeros5 <= 8'd2;
8'h0000????: leadingZeros5 <= 8'd1;
8'b00000000: leadingZeros5 <= 8'd2;
8'b0000????: leadingZeros5 <= 8'd1;
default: leadingZeros5 <= 8'd0;
endcase
`endif
/rtl/verilog2/DFPNormalize128.sv
0,0 → 1,331
// ============================================================================
// __
// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DFPNormalize128.sv
// - decimal floating point normalization unit
// - eight cycle latency
// - parameterized width
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// This unit takes a floating point number in an intermediate
// format and normalizes it. No normalization occurs
// for NaN's or infinities. The unit has a two cycle latency.
//
// The mantissa is assumed to start with two whole bits on
// the left. The remaining bits are fractional.
//
// The width of the incoming format is reduced via a generation
// of sticky bit in place of the low order fractional bits.
//
// On an underflowed input, the incoming exponent is assumed
// to be negative. A right shift is needed.
// ============================================================================
 
import DFPPkg::*;
 
module DFPNormalize128(clk, ce, i, o, under_i, under_o, inexact_o);
parameter N=34;
input clk;
input ce;
input DFP128UD i; // expanded format input
output DFP128UN o; // normalized output + guard, sticky and round bits, + 1 whole digit
input under_i;
output under_o;
output inexact_o;
 
integer n;
// ----------------------------------------------------------------------------
// No Clock required
// ----------------------------------------------------------------------------
reg [13:0] xo0;
reg so0;
reg sx0;
reg nan0, qnan0, snan0;
reg inf0;
 
always @*
xo0 <= i.exp;
always @*
so0 <= i.sign; // sign doesn't change
always @*
nan0 <= i.nan;
always @*
qnan0 <= i.qnan;
always @*
snan0 <= i.snan;
always @*
inf0 <= i.infinity;
 
// ----------------------------------------------------------------------------
// Clock #1
// - Capture exponent information
// ----------------------------------------------------------------------------
reg xInf1a, xInf1b, xInf1c;
DFP128UD i1;
always @(posedge clk)
if (ce)
i1 <= i;
 
always @(posedge clk)
if (ce) xInf1a <= xo0==14'h2FFF & !under_i;
always @(posedge clk)
if (ce) xInf1b <= xo0==14'h2FFE & !under_i;
always @(posedge clk)
if (ce) xInf1c <= xo0==14'h2FFF;
 
// ----------------------------------------------------------------------------
// Clock #2
// - determine exponent increment
// Since the there are *three* whole digits in the incoming format
// the number of whole digits needs to be reduced. If the MSB is
// set, then increment the exponent and no shift is needed.
// ----------------------------------------------------------------------------
wire xInf2c, xInf2b;
wire [13:0] xo2;
reg incExpByOne2;
delay #(.WID(1),.DEP(1)) u21 (.clk(clk), .ce(ce), .i(xInf1c), .o(xInf2c));
delay #(.WID(1),.DEP(1)) u22 (.clk(clk), .ce(ce), .i(xInf1b), .o(xInf2b));
delay #(.WID(14),.DEP(2)) u23 (.clk(clk), .ce(ce), .i(xo0), .o(xo2));
delay #(.WID(1),.DEP(2)) u24 (.clk(clk), .ce(ce), .i(under_i), .o(under2));
 
always @(posedge clk)
if (ce) incExpByOne2 <= !xInf1a & |i1.sig[279:276];
 
// ----------------------------------------------------------------------------
// Clock #3
// - increment exponent
// - detect a zero mantissa
// ----------------------------------------------------------------------------
 
wire incExpByOne3;
DFP128UD i3;
reg [13:0] xo3;
reg zeroMan3;
delay #(.WID(1),.DEP(1)) u32 (.clk(clk), .ce(ce), .i(incExpByOne2), .o(incExpByOne3));
delay #(.WID($bits(i3)),.DEP(3)) u33 (.clk(clk), .ce(ce), .i(i), .o(i3));
 
wire [13:0] xo2a = xo2 + 1'd1;
 
always @(posedge clk)
if (ce) xo3 <= (incExpByOne2 ? xo2a : xo2);
 
always @(posedge clk)
if(ce) zeroMan3 <= 1'b0;
 
// ----------------------------------------------------------------------------
// Clock #4
// - Shift mantissa left
// - If infinity is reached then set the mantissa to zero
// shift mantissa left to reduce to a single whole digit
// - create sticky bit
// ----------------------------------------------------------------------------
 
reg [(N+2)*4-1:0] mo4;
reg inexact4;
 
always @(posedge clk)
if(ce)
casez({zeroMan3,incExpByOne3})
2'b1?: mo4 <= 1'd0;
2'b01: mo4 <= {i3[(N+1)*4*2-1:(N+1)*4],3'b0,|i3[(N+1)*4-1:0]};
default: mo4 <= {i3[(N+1)*4*2-1-4:N*4],3'b0,|i3[N*4-1:0]};
endcase
 
always @(posedge clk)
if(ce)
casez({zeroMan3,incExpByOne3})
2'b1?: inexact4 <= 1'd0;
2'b01: inexact4 <= |i3[(N+1)*4-1:0];
default: inexact4 <= |i3[N*4-1:0];
endcase
 
// ----------------------------------------------------------------------------
// Clock edge #5
// - count leading zeros
// ----------------------------------------------------------------------------
reg [7:0] leadingZeros5;
wire [13:0] xo5;
wire xInf5;
delay #(.WID(14),.DEP(2)) u51 (.clk(clk), .ce(ce), .i(xo3), .o(xo5));
delay #(.WID(1),.DEP(3)) u52 (.clk(clk), .ce(ce), .i(xInf2c), .o(xInf5) );
 
/* Lookup table based leading zero count modules give slightly better
performance but cases must be coded.
generate
begin
if (FPWID <= 32) begin
cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo4,4'b0}), .o(leadingZeros5) );
assign leadingZeros5[7:6] = 2'b00;
end
else if (FPWID<=64) begin
assign leadingZeros5[7] = 1'b0;
cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo4,7'h0}), .o(leadingZeros5) );
end
else if (FPWID<=80) begin
assign leadingZeros5[7] = 1'b0;
cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo4,11'b0}), .o(leadingZeros5) );
end
else if (FPWID<=84) begin
assign leadingZeros5[7] = 1'b0;
cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,23'b0}), .o(leadingZeros5) );
end
else if (FPWID<=96) begin
assign leadingZeros5[7] = 1'b0;
cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,11'b0}), .o(leadingZeros5) );
end
else if (FPWID<=128)
cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo4,11'b0}), .o(leadingZeros5) );
end
endgenerate
*/
 
// Sideways add.
// Normally there would be only one to two leading zeros. It is tempting then
// to check for only one or two. But, denormalized numbers might have more
// leading zeros. If denormals were not supported this could be made smaller
// and faster.
`ifdef SUPPORT_DENORMALS
reg [7:0] lzc;
reg got_one;
always @*
begin
got_one = 1'b0;
lzc = 8'h00;
for (n = (N+2)*4-1; n >= 0; n = n - 4) begin
if (!got_one) begin
if (mo4[n]|mo4[n-1]|mo4[n-2]|mo4[n-3])
got_one = 1'b1;
else
lzc = lzc + 1'b1;
end
end
end
always @(posedge clk)
if (ce) leadingZeros5 <= lzc;
`else
wire [7:0] lead2 = mo4[(N+2)*4-1:N*4];
always @(posedge clk)
if (ce)
casez(lead2)
8'b00000000: leadingZeros5 <= 8'd2;
8'b0000????: leadingZeros5 <= 8'd1;
default: leadingZeros5 <= 8'd0;
endcase
`endif
 
 
// ----------------------------------------------------------------------------
// Clock edge #6
// - Compute how much we want to decrement exponent by
// - compute amount to shift left and right
// - at infinity the exponent can't be incremented, so we can't shift right
// otherwise it was an underflow situation so the exponent was negative
// shift amount needs to be negated for shift register
// If the exponent underflowed, then the shift direction must be to the
// right regardless of mantissa bits; the number is denormalized.
// Otherwise the shift direction must be to the left.
// ----------------------------------------------------------------------------
reg [7:0] lshiftAmt6;
reg [7:0] rshiftAmt6;
wire rightOrLeft6; // 0=left,1=right
wire xInf6;
wire [13:0] xo6;
wire [(N+2)*4-1:0] mo6;
wire zeroMan6;
vtdl #(1) u61 (.clk(clk), .ce(ce), .a(4'd5), .d(under_i), .q(rightOrLeft6) );
delay #(.WID(14),.DEP(1)) u62 (.clk(clk), .ce(ce), .i(xo5), .o(xo6));
delay #(.WID((N+2)*4),.DEP(2)) u63 (.clk(clk), .ce(ce), .i(mo4), .o(mo6) );
delay #(.WID(1),.DEP(1)) u64 (.clk(clk), .ce(ce), .i(xInf5), .o(xInf6) );
delay #(.WID(1),.DEP(3)) u65 (.clk(clk), .ce(ce), .i(zeroMan3), .o(zeroMan6));
delay #(.WID(1),.DEP(5)) u66 (.clk(clk), .ce(ce), .i(sx0), .o(sx5) );
 
always @(posedge clk)
if (ce) lshiftAmt6 <= {leadingZeros5 > xo5 ? xo5 : leadingZeros5,2'b0};
 
always @(posedge clk)
if (ce) rshiftAmt6 <= {xInf5 ? 1'd0 : $signed(xo5) > 14'd0 ? 8'd0 : ~xo5+2'd1,2'b00}; // xo2 is negative !
 
// ----------------------------------------------------------------------------
// Clock edge #7
// - figure exponent
// - shift mantissa
// - figure sticky bit
// ----------------------------------------------------------------------------
 
reg [15:0] xo7;
wire rightOrLeft7;
reg [(N+2)*4-1:0] mo7l, mo7r;
reg St6,St7;
delay #(.WID(1),.DEP(1)) u71 (.clk(clk), .ce(ce), .i(rightOrLeft6), .o(rightOrLeft7));
 
wire [13:0] xo7d = xo6 - lshiftAmt6;
 
always @(posedge clk)
if (ce)
xo7 <= zeroMan6 ? xo6 :
xInf6 ? xo6 : // an infinite exponent is either a NaN or infinity; no need to change
rightOrLeft6 ? 1'd0 : // on a right shift, the exponent was negative, it's being made to zero
xo7d; // on a left shift, the exponent can't be decremented below zero
 
always @(posedge clk)
if (ce) mo7r <= mo6 >> rshiftAmt6;
always @(posedge clk)
if (ce) mo7l <= mo6 << lshiftAmt6;
 
// The sticky bit is set if the bits shifted out on a right shift are set.
always @*
begin
St6 = 1'b0;
for (n = 0; n < (N+2)*4; n = n + 1)
if (n <= rshiftAmt6 + 1) St6 = St6|mo6[n];
end
always @(posedge clk)
if (ce) St7 <= St6;
 
// ----------------------------------------------------------------------------
// Clock edge #8
// - select mantissa
// ----------------------------------------------------------------------------
 
wire so,sxo,nano,info,qnano,snano;
wire [13:0] xo;
reg [(N+2)*4-1:0] mo;
vtdl #(1) u81 (.clk(clk), .ce(ce), .a(4'd7), .d(so0), .q(so) );
delay #(.WID(14),.DEP(1)) u82 (.clk(clk), .ce(ce), .i(xo7), .o(xo));
vtdl #(.WID(1)) u83 (.clk(clk), .ce(ce), .a(4'd3), .d(inexact4), .q(inexact_o));
delay #(.WID(1),.DEP(1)) u84 (.clk(clk), .ce(ce), .i(rightOrLeft7), .o(under_o));
vtdl #(1) u86 (.clk(clk), .ce(ce), .a(4'd7), .d(nan0), .q(nano) );
vtdl #(1) u87 (.clk(clk), .ce(ce), .a(4'd7), .d(qnan0), .q(qnano) );
vtdl #(1) u88 (.clk(clk), .ce(ce), .a(4'd7), .d(snan0), .q(snano) );
vtdl #(1) u89 (.clk(clk), .ce(ce), .a(4'd7), .d(inf0), .q(info) );
 
always @(posedge clk)
if (ce) mo <= rightOrLeft7 ? mo7r|{St7,4'b0} : mo7l;
 
assign o.nan = nano;
assign o.qnan = qnano;
assign o.snan = snano;
assign o.infinity = info;
assign o.sign = so;
assign o.exp = xo;
assign o.sig = mo[(N+2)*4-1:4];
 
endmodule
/rtl/verilog2/DFPPack.sv
0,0 → 1,100
// ============================================================================
// __
// \\__/ o\ (C) 2020-2021 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DPDPack.sv
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
 
import DFPPkg::*;
 
module DFPPack128(i, o);
input DFP128U i;
output DFP128 o;
 
wire [109:0] enc_sig;
DPDEncodeN #(.N(11)) u1 (i.sig[131:0], enc_sig);
 
always @*
begin
// sign
o.sign <= i.sign;
// combo
if (i.qnan|i.snan)
o.combo <= 5'b11111;
else if (i.infinity)
o.combo <= 5'b11110;
else
o.combo <= i.sig[135:132] > 4'h7 ? {2'b11,i.exp[13:12],i.sig[132]} : {i.exp[13:12],i.sig[134:132]};
// exponent continuation
if (i.qnan)
o.expc <= {1'b0,i.exp[10:0]};
else if (i.snan)
o.expc <= {1'b1,i.exp[10:0]};
else
o.expc <= i.exp[11:0];
// significand continuation
o.sigc <= enc_sig;
end
 
endmodule
 
module DFPPack64(i, o);
input DFP64U i;
output DFP64 o;
 
wire [49:0] enc_sig;
DPDEncodeN #(.N(5)) u1 (i.sig[59:0], enc_sig);
 
always @*
begin
// sign
o.sign <= i.sign;
// combo
if (i.qnan|i.snan)
o.combo <= 5'b11111;
else if (i.infinity)
o.combo <= 5'b11110;
else
o.combo <= i.sig[63:60] > 4'h7 ? {2'b11,i.exp[9:8],i.sig[60]} : {i.exp[9:8],i.sig[62:60]};
// exponent continuation
if (i.qnan)
o.expc <= {1'b0,i.exp[6:0]};
else if (i.snan)
o.expc <= {1'b1,i.exp[6:0]};
else
o.expc <= i.exp[7:0];
// significand continuation
o.sigc <= enc_sig;
end
 
endmodule
/rtl/verilog2/DFPPkg.sv
0,0 → 1,143
// ============================================================================
// __
// \\__/ o\ (C) 2020-2021 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DFPPkg.sv
// - decimal floating point package
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// This unit takes a floating point number in an intermediate
// format and normalizes it. No normalization occurs
// for NaN's or infinities. The unit has a two cycle latency.
//
// The mantissa is assumed to start with two whole bits on
// the left. The remaining bits are fractional.
//
// The width of the incoming format is reduced via a generation
// of sticky bit in place of the low order fractional bits.
//
// On an underflowed input, the incoming exponent is assumed
// to be negative. A right shift is needed.
// ============================================================================
 
package DFPPkg;
 
`define SUPPORT_DENORMALS 1'b1
 
typedef struct packed
{
logic sign;
logic [4:0] combo;
logic [14:0] expc; // exponent continuation field
logic [139:0] sigc; // significand continuation field
} DFP160;
 
// Packed 128 bit (storage) format
typedef struct packed
{
logic sign;
logic [4:0] combo;
logic [11:0] expc; // exponent continuation field
logic [109:0] sigc; // significand continuation field
} DFP128;
 
typedef logic [13:0] DFP128EXP;
typedef logic [135:0] DFP128SIG;
 
// Unpacked 128 bit format
typedef struct packed
{
logic nan;
logic qnan;
logic snan;
logic infinity;
logic sign;
logic [13:0] exp;
logic [135:0] sig; // significand 34 digits
} DFP128U;
 
// Normalizer output to rounding, one extra digit
typedef struct packed
{
logic nan;
logic qnan;
logic snan;
logic infinity;
logic sign;
logic [13:0] exp;
logic [139:0] sig; // significand 35 digits
} DFP128UN;
 
// 128-bit Double width significand, normalizer input
typedef struct packed
{
logic nan;
logic qnan;
logic snan;
logic infinity;
logic sign;
logic [13:0] exp;
logic [279:0] sig; // significand 68+ 1 lead, 1-trail digit
} DFP128UD;
 
typedef logic [9:0] DFP64EXP;
typedef logic [63:0] DFP64SIG;
 
typedef struct packed
{
logic sign;
logic [4:0] combo;
logic [7:0] expc; // exponent continuation field
logic [49:0] sigc; // significand continuation field
} DFP64;
 
typedef struct packed
{
logic nan;
logic qnan;
logic snan;
logic infinity;
logic sign;
logic [9:0] exp;
logic [63:0] sig; // significand 16 digits
} DFP64U;
 
typedef struct packed
{
logic nan;
logic qnan;
logic snan;
logic infinity;
logic sign;
logic [9:0] exp;
logic [67:0] sig; // significand 17 digits
} DFP64UN;
 
typedef struct packed
{
logic nan;
logic qnan;
logic snan;
logic infinity;
logic sign;
logic [9:0] exp;
logic [127:0] sig; // significand 32 digits
} DFP64UD;
 
endpackage
/rtl/verilog2/DFPRound128.sv
0,0 → 1,183
// ============================================================================
// __
// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DFPRound128.sv
// - decimal floating point rounding unit
// - parameterized width
//
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
 
import DFPPkg::*;
 
`ifdef MIN_LATENCY
`define PIPE_ADV *
`else
`define PIPE_ADV (posedge clk)
`endif
 
module DFPRound128(clk, ce, rm, i, o);
parameter N=34;
input clk;
input ce;
input [2:0] rm; // rounding mode
input DFP128UN i; // intermediate format input
output DFP128U o; // rounded output
 
parameter ROUND_CEILING = 3'd0;
parameter ROUND_FLOOR = 3'd1;
parameter ROUND_HALF_UP = 3'd2;
parameter ROUND_HALF_EVEN = 3'd3;
parameter ROUND_DOWN = 3'd4;
 
//------------------------------------------------------------
// variables
wire nano, qnano, snano;
wire infinity;
wire so;
wire [13:0] xo;
reg [N*4-1:0] mo;
reg [13:0] xo1;
reg [N*4-1:0] mo1;
wire xInf = i.exp==14'h3FFF;
wire so0 = i.sign;
assign o = {so,xo,mo};
 
assign o.nan = nano;
assign o.qnan = qnano;
assign o.snan = snano;
assign o.infinity = infinity;
assign o.sign = so;
assign o.exp = xo;
assign o.sig = mo;
 
wire [3:0] l = i.sig[7:4];
wire [3:0] r = i.sig[3:0];
 
reg rnd;
 
//------------------------------------------------------------
// Clock #1
// - determine round amount (add 1 or 0)
//------------------------------------------------------------
 
always @`PIPE_ADV
if (ce) xo1 <= i.exp;
always @`PIPE_ADV
if (ce) mo1 <= i.sig[(N+1)*4-1:4];
 
// Compute the round bit
// Infinities and NaNs are not rounded!
always @`PIPE_ADV
if (ce)
if (i.nan | i.infinity)
rnd = 1'b0;
else
case (rm)
ROUND_CEILING: rnd <= (r == 4'd0 || i.sign==1'b1) ? 1'b0 : 1'b1;
ROUND_FLOOR: rnd <= (r == 4'd0 || i.sign==1'b0) ? 1'b0 : 1'b1;
ROUND_HALF_UP: rnd <= r >= 4'h5;
ROUND_HALF_EVEN: rnd <= r==4'h5 ? l[0] : r > 4'h5 ? 1'b1 : 1'b0;
ROUND_DOWN: rnd <= 1'b0;
default: rnd <= 1'b0;
endcase
 
//------------------------------------------------------------
// Clock #2
// round the number, check for carry
// note: inf. exponent checked above (if the exponent was infinite already, then no rounding occurs as rnd = 0)
// note: exponent increments if there is a carry (can only increment to infinity)
//------------------------------------------------------------
 
wire [N*4-1:0] rounded1;
wire cobcd;
 
BCDAddN #(.N(N)) ubcdan1
(
.ci(1'b0),
.a(mo1),
.b({{N*4-1{1'd0}},rnd}),
.o(rounded1),
.co(cobcd)
);
 
reg [N*4-1:0] rounded2;
reg rnd2;
reg dn2;
reg [14:0] xo2;
always @`PIPE_ADV
if (ce) rounded2 <= rounded1;
always @`PIPE_ADV
if (ce) rnd2 <= rnd;
always @`PIPE_ADV
if (ce) dn2 <= !(|xo1);
always @`PIPE_ADV
if (ce) xo2 <= xo1 + cobcd;
 
//------------------------------------------------------------
// Clock #3
// - shift mantissa if required.
//------------------------------------------------------------
wire infinity2;
`ifdef MIN_LATENCY
assign nano = i.nan;
assign qnano = i.qnan;
assign snano = i.snan;
assign infinity = i.infinity | (rnd2 && xo2[13:0]==14'h3FFF);
assign so = i.sign;
assign xo = xo2[13:0];
`else
delay3 #(1) u21 (.clk(clk), .ce(ce), .i(i.nan), .o(nano));
delay3 #(1) u22 (.clk(clk), .ce(ce), .i(i.qnan), .o(qnano));
delay3 #(1) u23 (.clk(clk), .ce(ce), .i(i.snan), .o(snano));
delay2 #(1) u24 (.clk(clk), .ce(ce), .i(i.infinity), .o(infinity2));
delay3 #(1) u25 (.clk(clk), .ce(ce), .i(i.sign), .o(so));
delay1 #(14) u26 (.clk(clk), .ce(ce), .i(xo2[13:0]), .o(xo));
delay1 #(1) u27 (.clk(clk), .ce(ce), .i(infinity2 | (rnd2 && xo2[13:0]==14'h3FFF)), .o(infinity));
`endif
 
wire carry2 = xo2[14];
 
always @`PIPE_ADV
if (ce)
casez({rnd2,xo2[13:0]==14'h3FFF,carry2,dn2})
4'b0??0: mo <= mo1[N*4-1:0]; // not rounding, not denormalized
4'b0??1: mo <= mo1[N*4-1:0]; // not rounding, denormalized
4'b1000: mo <= rounded2[N*4-1: 0]; // exponent didn't change, number was normalized
4'b1001: mo <= rounded2[N*4-1: 0]; // exponent didn't change, but number was denormalized
4'b1010: mo <= {4'h1,rounded2[N*4-1: 4]}; // exponent incremented (new MSD generated), number was normalized
4'b1011: mo <= rounded2[N*4-1:0]; // exponent incremented (new MSB generated), number was denormalized, number became normalized
4'b11??: mo <= {N*4{1'd0}}; // number became infinite, no need to check carry etc., rnd would be zero if input was NaN or infinite
endcase
 
endmodule
/rtl/verilog2/DFPUnpack.sv
0,0 → 1,67
// ============================================================================
// __
// \\__/ o\ (C) 2020-2021 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DPDUnpack.sv
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
 
import DFPPkg::*;
 
module DFPUnpack128(i, o);
input DFP128 i;
output DFP128U o;
 
assign o.sign = i.sign;
assign o.exp = {i.combo[4:3]==2'b11 ? i.combo[2:1] : i.combo[4:3],i.expc};
assign o.nan = i.combo==5'b11111;
assign o.qnan = i.combo==5'b11111 && i.expc[11]==1'b0;
assign o.snan = i.combo==5'b11111 && i.expc[11]==1'b1;
assign o.infinity = i.combo==5'b11110;
DPDDecodeN #(.N(11)) u1 (i.sigc, o.sig[131:0]);
assign o.sig[135:132] = i.combo[4:3]==2'b11 ? {3'b100,i.combo[0]} : {1'b0,i.combo[2:0]};
endmodule
 
module DFPUnpack64(i, o);
input DFP64 i;
output DFP64U o;
 
assign o.sign = i.sign;
assign o.exp = {i.combo[4:3]==2'b11 ? i.combo[2:1] : i.combo[4:3],i.expc};
assign o.nan = i.combo==5'b11111;
assign o.qnan = i.combo==5'b11111 && i.expc[7]==1'b0;
assign o.snan = i.combo==5'b11111 && i.expc[7]==1'b1;
assign o.infinity = i.combo==5'b11110;
DPDDecodeN #(.N(5)) u1 (i.sigc, o.sig[59:0]);
assign o.sig[63:60] = i.combo[4:3]==2'b11 ? {3'b100,i.combo[0]} : {1'b0,i.combo[2:0]};
 
endmodule
/rtl/verilog2/DPDDecode.sv
0,0 → 1,84
// ============================================================================
// __
// \\__/ o\ (C) 2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DPDDecode.sv
//
// An encoding described in:
// Densely Packed Decimal Encoding, by Mike Cowlishaw, in
 
 
//
// See: http://speleotrove.com/decimal/DPDecimal.html
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
 
module DPDDecode(i, o);
input [9:0] i;
output [11:0] o;
 
wire a,b,c,d,e,f,g,h,ii,j,k,m;
wire y,x,w,v,u,t,s,r,q,p;
 
assign {p,q,r,s,t,u,v,w,x,y} = i;
 
assign a = (v & w) & (~s | t | ~x);
assign b = p & (~v | ~w | (s & ~t & x));
assign c = q & (~v | ~w | (s & ~t & x));
assign d = r;
assign e = v & ((~w & x) | (~t & x) | (s & x));
assign f = (s & (~v | ~x)) | (p & ~s & t & v & w & x);
assign g = (t & (~v | ~x)) | (q & ~s & t & w);
assign h = u;
assign ii = v & ((~w & ~x) | (w & x & (s | t)));
assign j = (~v & w) | (s & v & ~w & x) | (p & w & (~x | (~s & ~t)));
assign k = (~v & x) | (t & ~w & x) | (q & v & w & (~x | (~s & ~t)));
assign m = y;
 
assign o = {a,b,c,d,e,f,g,h,ii,j,k,m};
endmodule
 
module DPDDecodeN(i, o);
parameter N=11;
input [N*10-1:0] i;
output [N*12-1:0] o;
 
genvar g;
 
generate begin : gDPD
for (g = 0; g < N; g = g + 1)
DPDDecode u1 (i[g*10+9:g*10], o[g*12+11:g*12]);
end
endgenerate
 
endmodule
/rtl/verilog2/DPDEncode.sv
0,0 → 1,81
// ============================================================================
// __
// \\__/ o\ (C) 2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DPDEncode.sv
//
// An encoding described in:
// Densely Packed Decimal Encoding, by Mike Cowlishaw, in
 
 
//
// See: http://speleotrove.com/decimal/DPDecimal.html
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
 
module DPDEncode(i, o);
input [11:0] i;
output [9:0] o;
 
wire a,b,c,d,e,f,g,h,ii,j,k,m;
wire p,q,r,s,t,u,v,w,x,y;
 
assign {a,b,c,d,e,f,g,h,ii,j,k,m} = i;
 
assign p = b | (a & j) | (a & f & ii);
assign q = c | (a & k) | (a & g & ii);
assign r = d;
assign s = (f & (~a | ~ii)) | (~a & e & j) | (e & ii);
assign t = g | (~a & e &k) | (a & ii);
assign u = h;
assign v = a | e | ii;
assign w = a | (e & ii) | (~e & j);
assign x = e | (a & ii) | (~a & k);
assign y = m;
 
assign o = {p,q,r,s,t,u,v,w,x,y};
 
endmodule
 
module DPDEncodeN(i, o);
parameter N=11;
input [N*12-1:0] i;
output [N*10-1:0] o;
 
genvar g;
generate begin : gDPDEncodeN
for (g = 0; g < N; g = g + 1)
DPDEncode u1 (i[g*12+11:g*12],o[g*10+9:g*10]);
end
endgenerate
 
endmodule

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