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Rev 53 → Rev 54

/trunk/rtl/verilog2/BCDMath.v
36,6 → 36,30
//
// ============================================================================
//
// Could use the following approach for add/sub but it ends up being larger
// than using an adjustment lookup table.
 
module BCDAddNyb(ci,a,b,o,c);
input ci; // carry input
input [3:0] a;
input [3:0] b;
output [3:0] o;
output c;
 
wire c0;
 
reg [4:0] hsN0;
always @*
begin
hsN0 = a[3:0] + b[3:0] + ci;
if (hsN0 > 5'd9)
hsN0 = hsN0 + 3'd6;
end
assign o = hsN0[3:0];
assign c = hsN0[4];
 
endmodule
 
module BCDAdd(ci,a,b,o,c);
input ci; // carry input
input [7:0] a;
/trunk/rtl/verilog2/DFPDivide.sv
0,0 → 1,265
// ============================================================================
// __
// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DFPDivide.sv
// - decimal floating point divider
// - parameterized width
//
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Floating Point Divider
//
//Properties:
//+-inf * +-inf = -+inf (this is handled by exOver)
//+-inf * 0 = QNaN
//+-0 / +-0 = QNaN
// ============================================================================
 
import fp::*;
 
module DFPDivide(rst, clk, ce, ld, op, a, b, o, done, sign_exe, overflow, underflow);
// FADD is a constant that makes the divider width a multiple of four and includes eight extra bits.
input rst;
input clk;
input ce;
input ld;
input op;
input [127:0] a, b;
output [243:0] o;
output reg done;
output sign_exe;
output overflow;
output underflow;
 
// registered outputs
reg sign_exe=0;
reg inf=0;
reg overflow=0;
reg underflow=0;
 
reg so, sxo;
reg [3:0] st;
reg [15:0] xo;
reg [223:0] mo;
assign o = {st,xo,mo};
 
// constants
wire [15:0] infXp = 16'h9999; // infinite / NaN - all ones
// The following is the value for an exponent of zero, with the offset
// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
// The following is a template for a quiet nan. (MSB=1)
wire [107:0] qNaN = {4'h1,{104{1'b0}}};
 
// variables
wire [231:0] divo;
 
// Operands
wire sa, sb; // sign bit
wire sxa, sxb;
wire [15:0] xa, xb; // exponent bits
wire [107:0] siga, sigb;
wire a_dn, b_dn; // a/b is denormalized
wire az, bz;
wire aInf, bInf;
wire aNan,bNan;
wire done1;
wire signed [7:0] lzcnt;
 
// -----------------------------------------------------------
// Clock #1
// - decode the input operands
// - derive basic information
// - calculate fraction
// -----------------------------------------------------------
reg ld1;
DFPDecomposeReg u1a (.clk(clk), .ce(ce), .i(a), .sgn(sa), .sx(sxa), .exp(xa), .sig(siga), .xz(a_dn), .vz(az), .inf(aInf), .nan(aNan) );
DFPDecomposeReg u1b (.clk(clk), .ce(ce), .i(b), .sgn(sb), .sx(sxb), .exp(xb), .sig(sigb), .xz(b_dn), .vz(bz), .inf(bInf), .nan(bNan) );
delay #(.WID(1), .DEP(1)) udly1 (.clk(clk), .ce(ce), .i(ld), .o(ld1));
 
// -----------------------------------------------------------
// Clock #2 to N
// - calculate fraction
// -----------------------------------------------------------
wire done3a,done3;
// Perform divide
dfdiv #(108+8) u2 (.clk(clk), .ld(ld1), .a({siga,8'b0}), .b({sigb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
wire [7:0] lzcnt_bin = lzcnt[3:0] + (lzcnt[7:4] * 10);
wire [231:0] divo1 = divo[231:0] << ({lzcnt_bin,2'b0}+(FPWID+44));
delay #(.WID(1), .DEP(3)) u3 (.clk(clk), .ce(ce), .i(done1), .o(done3a));
assign done3 = done1&done3a;
 
// -----------------------------------------------------------
// Clock #N+1
// - calculate exponent
// - calculate fraction
// - determine when a NaN is output
// -----------------------------------------------------------
// Compute the exponent.
// - correct the exponent for denormalized operands
// - adjust the difference by the bias (add 127)
// - also factor in the different decimal position for division
reg [15:0] ex2, ex1, ex2a, ex2b; // sum of exponents
reg qNaNOut;
reg under1, under;
reg over1, over;
wire [15:0] xapxb, xamxb, xbmxa;
wire xapxbc, xamxbc, xbmxac;
reg sxo0;
 
BCDAddN #(.N(4)) u5 (.ci(1'b0), .a(xa), .b(xb), .o(xapxb), .co(xapxbc) );
BCDSubN #(.N(4)) u6 (.ci(1'b0), .a(xa), .b(xb), .o(xamxb), .co(xamxbc) );
BCDSubN #(.N(4)) u7 (.ci(1'b0), .a(xb), .b(xa), .o(xbmxa), .co(xbmxac) );
BCDSubN #(.N(5)) u10 (.ci(1'b0), .a(20'h10000), .b(ex2a), .o(ex2b), .co() );
 
always @*
case ({sxa,sxb})
2'b11: begin ex2a <= xbmxa; sxo0 <= ~xbmxac; over1 <= 1'b0; under1 <= 1'b0; end
2'b10: begin ex2a <= xapxb; sxo0 <= 1'b1; over1 <= xapxbc; under1 <= 1'b0; end
2'b01: begin ex2a <= xapxb; sxo0 <= 1'b0; over1 <= 1'b0; under1 <= xapxbc; end
2'b00: begin ex2a <= xamxb; sxo0 <= ~xamxbc; over1 <= 1'b0; under1 <= 1'b0; end
endcase
 
always @*
if (~sxo0 && ~(sa^sb))
ex2 <= ex2b;
else
ex2 <= ex2a;
 
wire [15:0] ex1a, ex1b, ex1d;
reg [15:0] ex1c;
wire sxoa, sxob, sxoc;
 
BCDAddN #(.N(4)) u8 (.ci(1'b0), .a(ex2), .b({8'h00,lzcnt}), .o(ex1a), .co(sxoa) );
BCDSubN #(.N(4)) u9 (.ci(1'b0), .a(ex2), .b({8'h00,lzcnt}), .o(ex1b), .co(sxob) );
BCDSubN #(.N(5)) u11 (.ci(1'b0), .a(20'h10000), .b(ex1c), .o(ex1d), .co() );
 
always @(posedge clk)
case(sxo0)
2'd1: begin ex1c <= ex1b; sxo <= ~sxob; over <= over1; under <= under1; end
2'd0: begin ex1c <= ex1a; sxo <= 1'b0; over <= over1; under <= under1|sxob; end
endcase
 
always @*
if (sxo0 & sxob) // There was a borrow on a subtract, making the number negative
ex1 <= ex1d;
else
ex1 <= ex1c;
 
 
always @(posedge clk)
if (ce) qNaNOut <= (az&bz)|(aInf&bInf);
 
// -----------------------------------------------------------
// Clock #N+3
// -----------------------------------------------------------
always @(posedge clk)
// Simulation likes to see these values reset to zero on reset. Otherwise the
// values propagate in sim as X's.
if (rst) begin
xo <= 1'd0;
mo <= 1'd0;
so <= 1'd0;
sign_exe <= 1'd0;
overflow <= 1'd0;
underflow <= 1'd0;
done <= 1'b1;
end
else if (ce) begin
done <= 1'b0;
if (done3&done1) begin
done <= 1'b1;
 
casez({qNaNOut|aNan|bNan,bInf,bz,over,under})
5'b1????: xo <= infXp; // NaN exponent value
5'b01???: xo <= 1'd0; // divide by inf
5'b001??: xo <= infXp; // divide by zero
5'b0001?: xo <= infXp; // overflow
5'b00001: xo <= 1'd0; // underflow
default: xo <= ex1; // normal or underflow: passthru neg. exp. for normalization
endcase
 
casez({aNan,bNan,qNaNOut,bInf,bz,over,aInf&bInf,az&bz})
8'b1???????: begin mo <= {4'h1,a[107:0],{111{1'b0}}}; st[3] <= 1'b1; end
8'b01??????: begin mo <= {4'h1,b[107:0],{111{1'b0}}}; st[3] <= 1'b1; end
8'b001?????: begin mo <= {4'h1,qNaN[107:0]|{aInf,1'b0}|{az,bz},{1111{1'b0}}}; st[3] <= 1'b1; end
8'b0001????: begin mo <= 224'd0; st[3] <= 1'b0; end // div by inf
8'b00001???: begin mo <= 224'd0; st[3] <= 1'b0; end // div by zero
8'b000001??: begin mo <= 224'd0; st[3] <= 1'b0; end // Inf exponent
8'b0000001?: begin mo <= {4'h1,qNaN|`QINFDIV,{111{1'b0}}}; st[3] <= 1'b1; end // infinity / infinity
8'b00000001: begin mo <= {4'h1,qNaN|`QZEROZERO,{111{1'b0}}}; st[3] <= 1'b1; end // zero / zero
default: begin mo <= divo1[231:8]; st[3] <= 1'b0; end // plain div
endcase
 
st[0] <= sxo;
st[1] <= aInf;
st[2] <= ~(sa ^ sb);
so <= ~(sa ^ sb);
sign_exe <= sa & sb;
overflow <= over;
underflow <= under;
end
end
 
endmodule
 
module DFPDividenr(rst, clk, ce, ld, op, a, b, o, rm, done, sign_exe, inf, overflow, underflow);
input rst;
input clk;
input ce;
input ld;
input op;
input [127:0] a, b;
output [127:0] o;
input [2:0] rm;
output sign_exe;
output done;
output inf;
output overflow;
output underflow;
 
wire [243:0] o1;
wire sign_exe1, inf1, overflow1, underflow1;
wire [131:0] fpn0;
wire done1, done1a;
 
DFPDivide #(FPWID) u1 (rst, clk, ce, ld, op, a, b, o1, done1, sign_exe1, overflow1, underflow1);
DFPNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under_i(underflow1), .i(o1), .o(fpn0) );
DFPRound #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
delay2 #(1) u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
delay2 #(1) u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
delay2 #(1) u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
delay #(.WID(1),.DEP(11)) u8(.clk(clk), .ce(ce), .i(done1), .o(done1a));
assign done = done1&done1a;
 
endmodule
 
/trunk/rtl/verilog2/DFPMultiply.sv
58,9 → 58,12
 
import fp::*;
 
module DFPMultiply(clk, ce, a, b, o, sign_exe, inf, overflow, underflow);
//`define DFPMUL_PARALLEL 1'b1
 
module DFPMultiply(clk, ce, ld, a, b, o, sign_exe, inf, overflow, underflow, done);
input clk;
input ce;
input ld;
input [127:0] a, b;
output [243:0] o;
output sign_exe;
67,6 → 70,7
output inf;
output overflow;
output underflow;
output done;
parameter DELAY =
(FPWID == 128 ? 17 :
FPWID == 80 ? 17 :
113,8 → 117,9
// -----------------------------------------------------------
 
reg under, over;
reg [15:0] sum_ex;
reg [15:0] sum_ex, sum_ex1;
reg sx0;
wire done1;
 
DFPDecompose u1a (.i(a), .sgn(sa), .sx(sxa), .exp(xa), .sig(siga), .xz(a_dn), .vz(az), .inf(aInf), .nan(aNan) );
DFPDecompose u1b (.i(b), .sgn(sb), .sx(sxb), .exp(xb), .sig(sigb), .xz(b_dn), .vz(bz), .inf(bInf), .nan(bNan) );
126,17 → 131,41
BCDAddN #(.N(4)) u1c (.ci(1'b0), .a(xa), .b(xb), .o(xapxb), .co(xapxbc));
BCDSubN #(.N(4)) u1d (.ci(1'b0), .a(xa), .b(xb), .o(xamxb), .co(xamxbc));
BCDSubN #(.N(4)) u1e (.ci(1'b0), .a(xb), .b(xa), .o(xbmxa), .co(xbmxac));
BCDSubN #(.N(5)) u1h (.ci(1'b0), .a(20'h10000), .b(sum_ex1), .o(sum_ex2), .co());
 
always @*
case({sxa,sxb})
2'b11: begin sum_ex <= xapxb; over <= xapxbc; under <= 1'b0; sx0 <= sxa; end
2'b01: begin sum_ex <= xbmxa; over <= 1'b0; under <= 1'b0; sx0 <= ~xbmxac; end
2'b10: begin sum_ex <= xamxb; over <= 1'b0; under <= 1'b0; sx0 <= ~xamxbc; end
2'b00: begin sum_ex <= xapxb; over <= 1'b0; under <= xapxbc; sx0 <= sxa; end
2'b11: begin sum_ex1 <= xapxb; over <= xapxbc; under <= 1'b0; sx0 <= sxa; end
2'b01: begin sum_ex1 <= xbmxa; over <= 1'b0; under <= 1'b0; sx0 <= ~xbmxac; end
2'b10: begin sum_ex1 <= xamxb; over <= 1'b0; under <= 1'b0; sx0 <= ~xamxbc; end
2'b00: begin sum_ex1 <= xapxb; over <= 1'b0; under <= xapxbc; sx0 <= sxa; end
endcase
 
// Take nine's complement if exponent sign changed.
always @*
if ((sxa^sxb)) begin
if ((sxa & xamxbc) || (sxb & xbmxac))
sum_ex <= sum_ex2;
else
sum_ex <= sum_ex1;
end
else
sum_ex <= sum_ex1;
 
wire [255:0] sigoo;
`ifdef DFPMUL_PARALLEL
BCDMul32 u1f (.a({20'h0,siga}),.b({20'h0,sigb}),.o(sigoo));
`else
dfmul u1g
(
.clk(clk),
.ld(ld),
.a(siga),
.b(sigb),
.p(sigoo),
.done(done1)
);
`endif
 
always @(posedge clk)
if (ce) sig1 <= sigoo[215:0];
166,6 → 195,7
 
wire so1, sx1;
reg [3:0] st;
wire done1a;
 
delay #(.WID(1),.DEP(1)) u8 (.clk(clk), .ce(ce), .i(~(sa ^ sb)), .o(so1) );// two clock delay!
delay #(.WID(1),.DEP(1)) u9 (.clk(clk), .ce(ce), .i(sx0), .o(sx1) );// two clock delay!
206,8 → 236,10
delay1 u11 (.clk(clk), .ce(ce), .i(over1), .o(overflow) );
delay1 u12 (.clk(clk), .ce(ce), .i(over1), .o(inf) );
delay1 u13 (.clk(clk), .ce(ce), .i(under1), .o(underflow) );
delay #(.WID(1),.DEP(3)) u18 (.clk(clk), .ce(ce), .i(done1), .o(done1a) );
 
assign o = {st,xo1,mo1,8'h00};
assign done = done1&done1a;
 
endmodule
 
214,9 → 246,10
 
// Multiplier with normalization and rounding.
 
module DFPMultiplynr(clk, ce, a, b, o, rm, sign_exe, inf, overflow, underflow);
module DFPMultiplynr(clk, ce, ld, a, b, o, rm, sign_exe, inf, overflow, underflow, done);
input clk;
input ce;
input ld;
input [127:0] a, b;
output [127:0] o;
input [2:0] rm;
224,12 → 257,14
output inf;
output overflow;
output underflow;
output done;
 
wire done1, done1a;
wire [243:0] o1;
wire sign_exe1, inf1, overflow1, underflow1;
wire [131:0] fpn0;
 
DFPMultiply u1 (clk, ce, a, b, o1, sign_exe1, inf1, overflow1, underflow1);
DFPMultiply u1 (clk, ce, ld, a, b, o1, sign_exe1, inf1, overflow1, underflow1, done1);
DFPNormalize u2(.clk(clk), .ce(ce), .under_i(underflow1), .i(o1), .o(fpn0) );
DFPRound u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
delay2 #(1) u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
236,4 → 271,7
delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
delay2 #(1) u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
delay2 #(1) u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
delay #(.WID(1),.DEP(11)) u10 (.clk(clk), .ce(ce), .i(done1), .o(done1a) );
assign done = done1 & done1a;
 
endmodule
/trunk/rtl/verilog2/dfdiv.v
0,0 → 1,181
// ============================================================================
// __
// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// dfdiv.v
// Decimal Float divider primitive
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
 
module dfdiv(clk, ld, a, b, q, r, done, lzcnt);
parameter FPWID = 108;
parameter RADIX = 10;
localparam FPWID1 = FPWID;//((FPWID+2)/3)*3; // make FPWIDth a multiple of three
localparam DMSB = FPWID1-1;
input clk;
input ld;
input [FPWID-1:0] a;
input [FPWID-1:0] b;
output reg [FPWID*2-1:0] q;
output reg [FPWID-1:0] r;
output reg done;
output reg [7:0] lzcnt; // Leading zero digit count as a BCD number
 
 
reg [1:0] st;
parameter PREP = 2'd0;
parameter SUBN = 2'd1;
parameter DONE = 2'd2;
 
reg [3:0] cnt; // iteration count
reg [5:0] dcnt; // digit count
reg [9:0] clkcnt;
reg [FPWID*2-1:0] qi = 0;
reg [FPWID+4-1:0] ri = 0;
reg [FPWID-1:0] bi = 0;
wire [FPWID+4-1:0] dif;
reg gotnz; // got a non-zero digit
 
BCDSubN #(.N((FPWID+4)/4)) u1
(
.ci(1'b0),
.a(ri),
.b({4'd0,bi}),
.o(dif),
.co(co)
);
 
always @(posedge clk)
begin
case(st)
SUBN:
begin
clkcnt <= clkcnt + 1'd1;
if (co) begin
ri <= {ri,qi[FPWID*2-1:FPWID*2-4]};
qi <= {qi[FPWID*2-5:0],cnt};
cnt <= 4'd0;
dcnt <= dcnt - 1'd1;
if (dcnt==6'd0)
st <= DONE;
if (dcnt <= FPWID/4) begin
if (|cnt)
gotnz <= 1'b1;
else if (!gotnz) begin
if (lzcnt[3:0]==4'd9)
lzcnt <= lzcnt + 4'd7;
else
lzcnt <= lzcnt + 1'd1;
end
end
end
else begin
if (clkcnt > 600) begin
ri <= {ri,qi[FPWID*2-1:FPWID*2-4]};
qi <= {qi[FPWID*2-5:0],cnt};
cnt <= 4'd0;
dcnt <= dcnt - 1'd1;
if (dcnt==6'd0)
st <= DONE;
if (dcnt <= FPWID/4) begin
if (|cnt)
gotnz <= 1'b1;
else if (!gotnz) begin
if (lzcnt[3:0]==4'd9)
lzcnt <= lzcnt + 4'd7;
else
lzcnt <= lzcnt + 1'd1;
end
end
end
else begin
ri <= dif;
cnt <= cnt + 1'd1;
end
end
end
DONE:
begin
q <= qi;
r <= ri;
done <= 1'b1;
end
default:
st <= SUBN;
endcase
if (ld) begin
clkcnt <= 10'd0;
cnt <= 4'd0;
dcnt <= (FPWID*2)/4;
qi <= {a,{FPWID{1'd0}}};
ri <= {FPWID{1'd0}};
bi <= b;
st <= SUBN;
gotnz <= 1'b0;
lzcnt <= 8'd0;
done <= 1'b0;
end
end
 
endmodule
 
module dfdiv_tb();
 
reg clk;
reg ld;
reg [107:0] a, b;
wire [215:0] q;
wire [107:0] r;
wire [7:0] lzcnt;
 
initial begin
clk = 1'b0;
ld = 1'b0;
a = 108'h099_00000000_00000000_00000000;
b = 108'h560_00000000_00000000_00000000;
#20 ld = 1'b1;
#40 ld = 1'b0;
end
 
always #5 clk = ~clk;
 
dfdiv #(108) u1 (
.clk(clk),
.ld(ld),
.a(a),
.b(b),
.q(q),
.r(r),
.done(done),
.lzcnt(lzcnt)
);
endmodule
/trunk/rtl/verilog2/dfmul.sv
0,0 → 1,142
// ============================================================================
// __
// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// dfmul.v
// Decimal Float multiplier primitive
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
 
module dfmul(clk, ld, a, b, p, done);
parameter FPWID = 108;
parameter RADIX = 10;
localparam FPWID1 = FPWID;//((FPWID+2)/3)*3; // make FPWIDth a multiple of three
localparam DMSB = FPWID1-1;
input clk;
input ld;
input [FPWID-1:0] a;
input [FPWID-1:0] b;
output reg [FPWID*2-1:0] p;
output reg done;
 
 
reg [1:0] st;
parameter PREP = 2'd0;
parameter ADDN = 2'd1;
parameter DONE = 2'd2;
 
reg [3:0] cnt; // iteration count
reg [5:0] dcnt; // digit count
reg [9:0] clkcnt;
reg [FPWID*2-1:0] pi = 0;
reg [FPWID-1:0] ai = 0;
reg [FPWID*2-1:0] bi = 0;
wire [FPWID*2-1:0] sum;
 
BCDAddN #(.N((FPWID*2)/4)) u1
(
.ci(1'b0),
.a(pi),
.b(bi),
.o(sum),
.co()
);
 
always @(posedge clk)
begin
case(st)
ADDN:
begin
clkcnt <= clkcnt + 1'd1;
if (ai[FPWID-1:FPWID-4]!=4'h0) begin
pi <= sum;
ai[FPWID-1:FPWID-4] <= ai[FPWID-1:FPWID-4] - 1'd1;
cnt <= cnt + 1'd1;
end
else begin
ai <= {ai,4'h0};
bi <= {4'h0,bi[FPWID*2-1:4]};
pi <= pi;
dcnt <= dcnt - 1'd1;
if (dcnt==6'd0)
st <= DONE;
end
end
DONE:
begin
p <= pi;
done <= 1'b1;
end
default:
st <= ADDN;
endcase
if (ld) begin
clkcnt <= 10'd0;
cnt <= 4'd0;
dcnt <= (FPWID*2)/4;
pi <= {FPWID*2{1'b0}};
ai <= a;
bi <= {4'h0,b,{FPWID-4{1'b0}}};
st <= ADDN;
done <= 1'b0;
end
end
 
endmodule
 
module dfmul_tb();
 
reg clk;
reg ld;
reg [107:0] a, b;
wire [215:0] p;
 
initial begin
clk = 1'b0;
ld = 1'b0;
a = 108'h099_00000000_00000000_00000000;
b = 108'h560_00000000_00000000_00000000;
#20 ld = 1'b1;
#40 ld = 1'b0;
end
 
always #5 clk = ~clk;
 
dfmul #(108) u1 (
.clk(clk),
.ld(ld),
.a(a),
.b(b),
.p(p),
.done(done)
);
endmodule
/trunk/test_bench/DFPDivide_tb.v
0,0 → 1,172
`timescale 1ns / 1ps
// ============================================================================
// __
// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DFPDivider_tb.v
// - decimal floating point divider test bench
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
// Floating Point Multiplier / Divider
//
// This multiplier/divider handles denormalized numbers.
// The output format is of an internal expanded representation
// in preparation to be fed into a normalization unit, then
// rounding. Basically, it's the same as the regular format
// except the mantissa is doubled in size, the leading two
// bits of which are assumed to be whole bits.
//
//
// ============================================================================
 
module DFPDivide_tb();
reg rst;
reg clk;
reg [15:0] adr;
reg [127:0] a,b;
wire [127:0] o;
reg [127:0] ad,bd;
wire [127:0] od;
reg [3:0] rm;
wire done;
 
integer n;
reg [127:0] a1, b1;
reg [39:0] sum_cc;
 
wire [63:0] doubleA = {a[31], a[30], {3{~a[30]}}, a[29:23], a[22:0], {29{1'b0}}};
wire [63:0] doubleB = {b[31], b[30], {3{~b[30]}}, b[29:23], b[22:0], {29{1'b0}}};
 
integer outfile;
 
initial begin
rst = 1'b0;
clk = 1'b0;
adr = 0;
a = $urandom(1);
b = 1;
#20 rst = 1;
#50 rst = 0;
#5000000 $fclose(outfile);
#10 $finish;
end
 
always #5
clk = ~clk;
 
genvar g;
generate begin : gRand
for (g = 0; g < 128; g = g + 4) begin
always @(posedge clk) begin
a1[g+3:g] <= $urandom() % 10;
b1[g+3:g] <= $urandom() % 10;
end
end
end
endgenerate
 
reg [9:0] count;
always @(posedge clk)
if (rst) begin
adr <= 0;
count <= 0;
sum_cc = 0;
end
else
begin
if (adr==0) begin
outfile = $fopen("d:/cores2020/rtf64/v2/rtl/verilog/cpu/fpu/test_bench/DFPDivide_tvo.txt", "wb");
$fwrite(outfile, "rm ------ A ------ ------- B ------ - DUT Quotient - - SIM Quotient -\n");
sum_cc = 0;
end
count <= count + 1;
if (count > 700)
count <= 1'd1;
if (count==2) begin
a[127:0] <= a1;
b[127:0] <= b1;
a[127:124] <= 4'h5;
b[127:124] <= 4'h5;
rm <= adr[15:13];
//ad <= memd[adr][63: 0];
//bd <= memd[adr][127:64];
end
if (adr==1 && count==2) begin
a <= 127'h50000700000000000000000000000000;
b <= 127'h50000200000000000000000000000000;
end
if (adr==1 && count==2) begin
a <= 127'h50000100000000000000000000000000;
b <= 127'h50000300000000000000000000000000;
end
if (adr==2 && count==2) begin
a <= 127'h50000900000000000000000000000000;
b <= 127'h50000200000000000000000000000000;
end
if (adr==3 && count==2) begin
a <= 127'h50000000000000000000000000000000;
b <= 127'h50000000000000000000000000000000;
end
if (adr==4 && count==2) begin
a <= 127'h50001100000000000000000000000000;
b <= 127'h50001100000000000000000000000000;
end
if (adr==4 && count==2) begin
a <= 127'h50000100000000000000000000000000;
b <= 127'h50000300000000000000000000000000;
end
if (count > 700) begin
sum_cc = sum_cc + u6.u1.u2.clkcnt;
$fwrite(outfile, "%h\t%h\t%h\t%h\t%d\t%f\n", rm, a, b, o, u6.u1.u2.clkcnt, $itor(sum_cc) / $itor(adr));
adr <= adr + 1;
end
end
 
//fpMulnr #(64) u1 (clk, 1'b1, a, b, o, rm);//, sign_exe, inf, overflow, underflow);
DFPDividenr u6 (
.rst(rst),
.clk(clk),
.ce(1'b1),
.ld(count==3),
.op(1'b0),
.a(a),
.b(b),
.o(o),
.rm(rm),
.done(done),
.sign_exe(),
.inf(),
.overflow(),
.underflow()
);
 
endmodule
/trunk/test_bench/DFPMultiply_tb.v
0,0 → 1,136
`timescale 1ns / 1ps
// ============================================================================
// __
// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DFPMultiply_tb.v
// - decimal floating point multiplier test bench
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Floating Point Multiplier / Divider
//
// This multiplier/divider handles denormalized numbers.
// The output format is of an internal expanded representation
// in preparation to be fed into a normalization unit, then
// rounding. Basically, it's the same as the regular format
// except the mantissa is doubled in size, the leading two
// bits of which are assumed to be whole bits.
//
//
// ============================================================================
 
module DFPMultiply_tb();
reg rst;
reg clk;
reg [15:0] adr;
reg [127:0] a,b;
wire [127:0] o;
reg [127:0] ad,bd;
wire [127:0] od;
reg [3:0] rm;
 
integer n;
reg [127:0] a1, b1;
wire [63:0] doubleA = {a[31], a[30], {3{~a[30]}}, a[29:23], a[22:0], {29{1'b0}}};
wire [63:0] doubleB = {b[31], b[30], {3{~b[30]}}, b[29:23], b[22:0], {29{1'b0}}};
wire done;
reg ld;
 
integer outfile;
 
initial begin
rst = 1'b0;
clk = 1'b0;
adr = 0;
a = $urandom(1);
#20 rst = 1;
#50 rst = 0;
#1000000 $fclose(outfile);
#10 $finish;
end
 
always #5
clk = ~clk;
 
genvar g;
generate begin : gRand
for (g = 0; g < 128; g = g + 4) begin
always @(posedge clk) begin
a1[g+3:g] <= $urandom() % 10;
b1[g+3:g] <= $urandom() % 10;
end
end
end
endgenerate
 
reg [9:0] count;
always @(posedge clk)
if (rst) begin
adr <= 0;
count <= 0;
end
else
begin
ld <= 1'b0;
if (adr==0) begin
outfile = $fopen("d:/cores2020/rtf64/v2/rtl/verilog/cpu/fpu/test_bench/DFPMultiply_tvo.txt", "wb");
$fwrite(outfile, "rm ------ A ------ ------- B ------ - DUT Product - - SIM Product -\n");
end
count <= count + 1;
if (count > 600)
count <= 1'd1;
if (count==2) begin
a[127:0] <= a1;
b[127:0] <= b1;
a[127:124] <= 4'h5;
b[127:124] <= 4'h5;
ld <= 1'b1;
rm <= adr[15:13];
//ad <= memd[adr][63: 0];
//bd <= memd[adr][127:64];
end
if (adr==1 && count==2) begin
a <= 127'h50000700000000000000000000000000;
b <= 127'h50000200000000000000000000000000;
end
if (adr==1 && count==2) begin
a <= 127'h40001333333333333333333333333333;
b <= 127'h50000300000000000000000000000000;
end
if (adr==2 && count==2) begin
a <= 127'h50000900000000000000000000000000;
b <= 127'h50000200000000000000000000000000;
end
if (adr==3 && count==2) begin
a <= 127'h50000000000000000000000000000000;
b <= 127'h50000000000000000000000000000000;
end
if (adr==4 && count==2) begin
a <= 127'h50001100000000000000000000000000;
b <= 127'h50001100000000000000000000000000;
end
if (count==600) begin
$fwrite(outfile, "%h\t%h\t%h\t%h\n", rm, a, b, o);
adr <= adr + 1;
end
end
 
//fpMulnr #(64) u1 (clk, 1'b1, a, b, o, rm);//, sign_exe, inf, overflow, underflow);
DFPMultiplynr u6 (clk, 1'b1, ld, a, b, o, rm, done);//, sign_exe, inf, overflow, underflow);
 
endmodule

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