OpenCores
URL https://opencores.org/ocsvn/gpio/gpio/trunk

Subversion Repositories gpio

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 33 to Rev 34
    ↔ Reverse comparison
  •

Rev 33 → Rev 34

/trunk/rtl/verilog/gpio_defines.v
44,6 → 44,18
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2003/10/02 18:54:35 simons
// GPIO signals muxed with other peripherals, higland_board fixed.
//
// Revision 1.1.1.1 2003/06/24 09:09:23 simons
// This files were moved here from toplevel folder.
//
// Revision 1.1.1.1 2003/06/11 18:51:13 simons
// Initial import.
//
// Revision 1.5 2002/11/11 21:36:28 lampret
// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC].
//
// Revision 1.4 2002/05/06 18:25:31 lampret
// negedge flops are enabled by default.
//
79,8 → 91,9
//
// Default is 16.
//
`define GPIO_IOS 16
`define GPIO_IOS 31
 
 
//
// Undefine this one if you don't want to remove GPIO block from your design
// but you also don't need it. When it is undefined, all GPIO ports still
161,8 → 174,20
//
// By default it is defined.
//
`define GPIO_STRICT_32BIT_ACCESS
//`define GPIO_STRICT_32BIT_ACCESS
//
`ifndef GPIO_STRICT_32BIT_ACCESS
// added by gorand :
// if GPIO_STRICT_32BIT_ACCESS is not defined,
// depending on number of gpio I/O lines, the following are defined :
// if the number of I/O lines is in range 1-8, GPIO_WB_BYTES1 is defined,
// if the number of I/O lines is in range 9-16, GPIO_WB_BYTES2 is defined,
// if the number of I/O lines is in range 17-24, GPIO_WB_BYTES3 is defined,
// if the number of I/O lines is in range 25-32, GPIO_WB_BYTES4 is defined,
 
`define GPIO_WB_BYTES4
`endif
 
//
// WISHBONE address bits used for full decoding of GPIO registers.
//
/trunk/rtl/verilog/gpio_top.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.13 2002/11/18 22:35:18 lampret
// Bug fix. Interrupts were also asserted when condition was not met.
//
// Revision 1.12 2002/11/11 21:36:28 lampret
// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC].
//
112,7 → 115,6
parameter dw = 32;
parameter aw = `GPIO_ADDRHH+1;
parameter gw = `GPIO_IOS;
 
//
// WISHBONE Interface
//
269,7 → 271,7
if (wb_rst_i)
wb_ack_o <= #1 1'b0;
else
wb_ack_o <= #1 wb_ack & ~wb_ack_o;
wb_ack_o <= #1 wb_ack & ~wb_ack_o & (!wb_err) ;
`else
assign wb_ack_o = wb_ack;
`endif
348,7 → 350,41
if (wb_rst_i)
rgpio_out <= #1 {gw{1'b0}};
else if (rgpio_out_sel && wb_we_i)
begin
`ifdef GPIO_STRICT_32BIT_ACCESS
rgpio_out <= #1 wb_dat_i[gw-1:0];
`endif
 
`ifdef GPIO_WB_BYTES4
if ( wb_sel_i [3] == 1'b1 )
rgpio_out [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
if ( wb_sel_i [2] == 1'b1 )
rgpio_out [23:16] <= #1 wb_dat_i [23:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES3
if ( wb_sel_i [2] == 1'b1 )
rgpio_out [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES2
if ( wb_sel_i [1] == 1'b1 )
rgpio_out [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES1
if ( wb_sel_i [0] == 1'b1 )
rgpio_out [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
`endif
end
 
`else
assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
`endif
357,11 → 393,45
// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.
//
`ifdef GPIO_RGPIO_OE
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
always @(posedge ~wb_clk_i or posedge ~wb_rst_i)
if (~wb_rst_i)
rgpio_oe <= #1 {gw{1'b0}};
else if (rgpio_oe_sel && wb_we_i)
else if (rgpio_oe_sel && ~wb_we_i)
begin
`ifdef GPIO_STRICT_32BIT_ACCESS
rgpio_oe <= #1 ~wb_dat_i[gw-1:0];
`endif
 
`ifdef GPIO_WB_BYTES4
if ( ~wb_sel_i [3] == 1'b1 )
rgpio_oe [gw-1:24] <= #1 ~wb_dat_i [gw-1:24] ;
if ( ~wb_sel_i [2] == 1'b1 )
rgpio_oe [23:16] <= #1 ~wb_dat_i [23:16] ;
if ( ~wb_sel_i [1] == 1'b1 )
rgpio_oe [15:8] <= #1 ~wb_dat_i [15:8] ;
if ( ~wb_sel_i [0] == 1'b1 )
rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES3
if ( ~wb_sel_i [2] == 1'b1 )
rgpio_oe [gw-1:16] <= #1 ~wb_dat_i [gw-1:16] ;
if ( ~wb_sel_i [1] == 1'b1 )
rgpio_oe [15:8] <= #1 ~wb_dat_i [15:8] ;
if ( ~wb_sel_i [0] == 1'b1 )
rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES2
if ( ~wb_sel_i [1] == 1'b1 )
rgpio_oe [gw-1:8] <= #1 ~wb_dat_i [gw-1:8] ;
if ( ~wb_sel_i [0] == 1'b1 )
rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES1
if ( ~wb_sel_i [0] == 1'b1 )
rgpio_oe [gw-1:0] <= #1 ~wb_dat_i [gw-1:0] ;
`endif
end
 
`else
assign rgpio_oe = `GPIO_DEF_RPGIO_OE; // RGPIO_OE = 0x0
`endif
374,7 → 444,42
if (wb_rst_i)
rgpio_inte <= #1 {gw{1'b0}};
else if (rgpio_inte_sel && wb_we_i)
begin
`ifdef GPIO_STRICT_32BIT_ACCESS
rgpio_inte <= #1 wb_dat_i[gw-1:0];
`endif
 
`ifdef GPIO_WB_BYTES4
if ( wb_sel_i [3] == 1'b1 )
rgpio_inte [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
if ( wb_sel_i [2] == 1'b1 )
rgpio_inte [23:16] <= #1 wb_dat_i [23:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES3
if ( wb_sel_i [2] == 1'b1 )
rgpio_inte [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES2
if ( wb_sel_i [1] == 1'b1 )
rgpio_inte [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES1
if ( wb_sel_i [0] == 1'b1 )
rgpio_inte [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
`endif
end
 
 
`else
assign rgpio_inte = `GPIO_DEF_RPGIO_INTE; // RGPIO_INTE = 0x0
`endif
387,7 → 492,41
if (wb_rst_i)
rgpio_ptrig <= #1 {gw{1'b0}};
else if (rgpio_ptrig_sel && wb_we_i)
begin
`ifdef GPIO_STRICT_32BIT_ACCESS
rgpio_ptrig <= #1 wb_dat_i[gw-1:0];
`endif
 
`ifdef GPIO_WB_BYTES4
if ( wb_sel_i [3] == 1'b1 )
rgpio_ptrig [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
if ( wb_sel_i [2] == 1'b1 )
rgpio_ptrig [23:16] <= #1 wb_dat_i [23:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES3
if ( wb_sel_i [2] == 1'b1 )
rgpio_ptrig [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES2
if ( wb_sel_i [1] == 1'b1 )
rgpio_ptrig [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES1
if ( wb_sel_i [0] == 1'b1 )
rgpio_ptrig [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
`endif
end
`else
assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG; // RGPIO_PTRIG = 0x0
`endif
400,7 → 539,41
if (wb_rst_i)
rgpio_aux <= #1 {gw{1'b0}};
else if (rgpio_aux_sel && wb_we_i)
begin
`ifdef GPIO_STRICT_32BIT_ACCESS
rgpio_aux <= #1 wb_dat_i[gw-1:0];
`endif
 
`ifdef GPIO_WB_BYTES4
if ( wb_sel_i [3] == 1'b1 )
rgpio_aux [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
if ( wb_sel_i [2] == 1'b1 )
rgpio_aux [23:16] <= #1 wb_dat_i [23:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES3
if ( wb_sel_i [2] == 1'b1 )
rgpio_aux [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES2
if ( wb_sel_i [1] == 1'b1 )
rgpio_aux [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES1
if ( wb_sel_i [0] == 1'b1 )
rgpio_aux [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
`endif
end
 
`else
assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.