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/tags/rel_6/bench/verilog/wb_master.v
0,0 → 1,308
`include "timescale.v" |
`include "gpio_defines.v" |
|
// -*- Mode: Verilog -*- |
// Filename : wb_master.v |
// Description : Wishbone Master Behavorial |
// Author : Winefred Washington |
// Created On : Thu Jan 11 21:18:41 2001 |
// Last Modified By: . |
// Last Modified On: . |
// Update Count : 0 |
// Status : Unknown, Use with caution! |
|
// Description Specification |
// General Description: 8, 16, 32-bit WISHBONE Master |
// Supported cycles: MASTER, READ/WRITE |
// MASTER, BLOCK READ/WRITE |
// MASTER, RMW |
// Data port, size: 8, 16, 32-bit |
// Data port, granularity 8-bit |
// Data port, Max. operand size 32-bit |
// Data transfer ordering: little endian |
// Data transfer sequencing: undefined |
// |
|
module wb_master(CLK_I, RST_I, TAG_I, TAG_O, |
ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O); |
|
parameter aw = `GPIO_ADDRHH+1 ; |
input CLK_I; |
input RST_I; |
input [3:0] TAG_I; |
output [3:0] TAG_O; |
input ACK_I; |
output [aw-1:0] ADR_O; |
output CYC_O; |
input [31:0] DAT_I; |
output [31:0] DAT_O; |
input ERR_I; |
input RTY_I; |
output [3:0] SEL_O; |
output STB_O; |
output WE_O; |
|
reg [aw-1:0] ADR_O; |
reg [3:0] SEL_O; |
reg CYC_O; |
reg STB_O; |
reg WE_O; |
reg [31:0] DAT_O; |
|
wire [15:0] mem_sizes; // determines the data width of an address range |
reg [31:0] write_burst_buffer[0:7]; |
reg [31:0] read_burst_buffer[0:7]; |
|
reg GO; |
integer cycle_end; |
integer address; |
integer data; |
integer selects; |
integer write_flag; |
|
// |
// mem_sizes determines the data widths of memory space |
// The memory space is divided into eight regions. Each |
// region is controlled by a two bit field. |
// |
// Bits |
// 00 = 8 bit memory space |
// 01 = 16 bit |
// 10 = 32 bit |
// 11 = 64 bit (not supported in this model |
// |
|
assign mem_sizes = 16'b10_01_10_11_00_01_10_11; |
|
function [1:0] data_width; |
input [31:0] adr; |
begin |
casex (adr[31:29]) |
3'b000: data_width = mem_sizes[15:14]; |
3'b001: data_width = mem_sizes[13:12]; |
3'b010: data_width = mem_sizes[11:10]; |
3'b011: data_width = mem_sizes[9:8]; |
3'b100: data_width = mem_sizes[7:6]; |
3'b101: data_width = mem_sizes[5:4]; |
3'b110: data_width = mem_sizes[3:2]; |
3'b111: data_width = mem_sizes[1:0]; |
3'bxxx: data_width = 2'bxx; |
endcase // casex (adr[31:29]) |
end |
endfunction |
|
always @(posedge CLK_I or posedge RST_I) |
begin |
if (RST_I) |
begin |
GO = 1'b0; |
end |
end |
|
// read single |
task rd; |
input [31:0] adr; |
output [31:0] result; |
|
begin |
cycle_end = 1; |
address = adr; |
selects = 255; |
write_flag = 0; |
|
GO <= 1; |
@(posedge CLK_I); |
// GO <= 0; |
|
// wait for cycle to start |
while (~CYC_O) |
@(posedge CLK_I); |
|
// wait for cycle to end |
while (CYC_O) |
@(posedge CLK_I); |
|
result = data; |
// $display(" Reading %h from address %h", result, address); |
|
end |
endtask // read |
|
task wr; |
input [31:0] adr; |
input [31:0] dat; |
input [3:0] sel; |
begin |
cycle_end = 1; |
address = adr; |
selects = sel; |
write_flag = 1; |
data = dat; |
|
GO <= 1; |
@(posedge CLK_I); |
// GO <= 0; |
|
// wait for cycle to start |
while (~CYC_O) |
@(posedge CLK_I); |
|
// wait for cycle to end |
while (CYC_O) |
@(posedge CLK_I); |
// $display(" Writing %h to address %h", data, address); |
|
end |
endtask // wr |
|
// block read |
task blkrd; |
input [31:0] adr; |
input end_flag; |
output [31:0] result; |
|
begin |
write_flag = 0; |
cycle_end = end_flag; |
address = adr; |
GO <= 1; |
@(posedge CLK_I); |
// GO <= 0; |
|
while (~(ACK_I & STB_O)) |
@(posedge CLK_I); |
|
result = data; |
end |
endtask // blkrd |
|
// block write |
task blkwr; |
input [31:0] adr; |
input [31:0] dat; |
input [3:0] sel; |
input end_flag; |
begin |
write_flag = 1; |
cycle_end = end_flag; |
address = adr; |
data = dat; |
selects = sel; |
GO <= 1; |
@(posedge CLK_I); |
// GO <= 0; |
|
while (~(ACK_I & STB_O)) |
@(posedge CLK_I); |
|
end |
endtask // blkwr |
|
// RMW |
task rmw; |
input [31:0] adr; |
input [31:0] dat; |
input [3:0] sel; |
output [31:0] result; |
|
begin |
// read phase |
write_flag = 0; |
cycle_end = 0; |
address = adr; |
GO <= 1; |
@(posedge CLK_I); |
// GO <= 0; |
|
while (~(ACK_I & STB_O)) |
@(posedge CLK_I); |
|
result = data; |
|
// write phase |
write_flag = 1; |
address = adr; |
selects = sel; |
GO <= 1; |
data <= dat; |
cycle_end <= 1; |
@(posedge CLK_I); |
// GO <= 0; |
|
while (~(ACK_I & STB_O)) |
@(posedge CLK_I); |
|
end |
endtask // rmw |
|
always @(posedge CLK_I) |
begin |
if (RST_I) |
ADR_O <= 32'h0000_0000; |
else |
ADR_O <= address; |
end |
|
always @(posedge CLK_I) |
begin |
if (RST_I | ERR_I | RTY_I) |
CYC_O <= 1'b0; |
else if ((cycle_end == 1) & ACK_I) |
CYC_O <= 1'b0; |
else if (GO | CYC_O) begin |
CYC_O <= 1'b1; |
GO <= 1'b0; |
end |
end |
|
// stb control |
always @(posedge CLK_I) |
begin |
if (RST_I | ERR_I | RTY_I) |
STB_O <= 1'b0; |
else if (STB_O & ACK_I) |
STB_O <= 1'b0; |
else if (GO | STB_O) |
STB_O <= 1'b1; |
end |
|
// selects & data |
always @(posedge CLK_I) |
begin |
if (write_flag == 0) begin |
SEL_O <= 4'b1111; |
if (STB_O & ACK_I) |
data <= DAT_I; |
end |
else begin |
case (data_width(address)) |
2'b00: begin |
SEL_O <= {3'b000, selects[0]}; |
DAT_O <= {data[7:0], data[7:0], data[7:0], data[7:0]}; |
end |
2'b01: begin |
SEL_O <= {2'b00, selects[1:0]}; |
DAT_O <= {data[15:0], data[15:0]}; |
end |
2'b10: begin |
SEL_O <= selects; |
DAT_O <= data; |
end |
endcase |
end |
end |
|
always @(posedge CLK_I) |
begin |
if (RST_I) |
WE_O <= 1'b0; |
else if (GO) |
WE_O <= write_flag; |
end |
|
endmodule |
|
|
|
|
|
/tags/rel_6/bench/verilog/gpio_mon.v
0,0 → 1,135
////////////////////////////////////////////////////////////////////// |
//// //// |
//// GPIO Monitor //// |
//// //// |
//// This file is part of the GPIO project //// |
//// http://www.opencores.org/cores/gpio/ //// |
//// //// |
//// Description //// |
//// Generates and monitors GPIO external signals (+auxiliary) //// |
//// //// |
//// To Do: //// |
//// Nothing //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/21 21:39:27 lampret |
// Changed directory structure, port names and drfines. |
// |
// Revision 1.2 2001/07/14 20:37:20 lampret |
// Test bench improvements. |
// |
// Revision 1.1 2001/06/05 07:45:22 lampret |
// Added initial RTL and test benches. There are still some issues with these files. |
// |
// |
|
`include "timescale.v" |
`include "gpio_defines.v" |
|
module gpio_mon(gpio_aux, gpio_in, gpio_eclk, gpio_out, gpio_oen); |
|
parameter gw = `GPIO_IOS; |
|
// |
// I/O ports |
// |
output [gw-1:0] gpio_aux; // Auxiliary |
output [gw-1:0] gpio_in; // GPIO inputs |
output gpio_eclk; // GPIO external clock |
input [gw-1:0] gpio_out; // GPIO outputs |
input [gw-1:0] gpio_oen; // GPIO output enables |
|
// |
// Internal regs |
// |
reg [gw-1:0] gpio_aux; |
reg [gw-1:0] gpio_in; |
reg gpio_eclk; |
|
initial gpio_eclk = 0; |
|
// |
// Set gpio_in |
// |
task set_gpioin; |
input [31:0] val; |
begin |
gpio_in = val; |
end |
endtask |
|
// |
// Set gpio_aux |
// |
task set_gpioaux; |
input [31:0] val; |
begin |
gpio_aux = val; |
end |
endtask |
|
// |
// Set gpio_eclk |
// |
task set_gpioeclk; |
input [31:0] val; |
begin |
gpio_eclk = val[0]; |
end |
endtask |
|
|
// |
// Get gpio_out |
// |
task get_gpioout; |
output [31:0] val; |
reg [31:0] val; |
begin |
val = gpio_out; |
end |
endtask |
|
// |
// Get gpio_oen |
// |
task get_gpiooen; |
output [31:0] val; |
begin |
val = gpio_oen; |
end |
endtask |
|
endmodule |
/tags/rel_6/bench/verilog/tb_top.v
0,0 → 1,164
////////////////////////////////////////////////////////////////////// |
//// //// |
//// GPIO Testbench Top //// |
//// //// |
//// This file is part of the GPIO project //// |
//// http://www.opencores.org/cores/gpio/ //// |
//// //// |
//// Description //// |
//// Top level of testbench. It instantiates all blocks. //// |
//// //// |
//// To Do: //// |
//// Nothing //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/03/13 20:56:16 lampret |
// Removed zero padding as per Avi Shamli suggestion. |
// |
// Revision 1.2 2001/09/18 15:43:28 lampret |
// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v. |
// |
// Revision 1.1 2001/08/21 21:39:27 lampret |
// Changed directory structure, port names and drfines. |
// |
// Revision 1.2 2001/07/14 20:37:24 lampret |
// Test bench improvements. |
// |
// Revision 1.1 2001/06/05 07:45:22 lampret |
// Added initial RTL and test benches. There are still some issues with these files. |
// |
// |
|
`include "timescale.v" |
`include "gpio_defines.v" |
|
module tb_top; |
|
parameter aw = `GPIO_ADDRHH+1 ; |
parameter dw = 32; |
parameter gw = `GPIO_IOS; |
|
// |
// Interconnect wires |
// |
wire clk; // Clock |
wire rst; // Reset |
wire cyc; // Cycle valid |
wire [aw-1:0] adr; // Address bus |
wire [dw-1:0] dat_m; // Data bus from PTC to WBM |
wire [3:0] sel; // Data selects |
wire we; // Write enable |
wire stb; // Strobe |
wire [dw-1:0] dat_ptc;// Data bus from WBM to PTC |
wire ack; // Successful cycle termination |
wire err; // Failed cycle termination |
wire [gw-1:0] gpio_aux; // GPIO auxiliary signals |
wire [gw-1:0] gpio_in; // GPIO inputs |
wire gpio_eclk; // GPIO external clock |
wire [gw-1:0] gpio_out; // GPIO outputs |
wire [gw-1:0] gpio_oen; // GPIO output enables |
wire [ 3 : 0 ] tag_o ; |
|
// |
// Instantiation of Clock/Reset Generator |
// |
clkrst clkrst( |
// Clock |
.clk_o(clk), |
// Reset |
.rst_o(rst) |
); |
|
// |
// Instantiation of Master WISHBONE BFM |
// |
wb_master wb_master( |
// WISHBONE Interface |
.CLK_I(clk), |
.RST_I(rst), |
.CYC_O(cyc), |
.ADR_O(adr), |
.DAT_O(dat_ptc), |
.SEL_O(sel), |
.WE_O(we), |
.STB_O(stb), |
.DAT_I(dat_m), |
.ACK_I(ack), |
.ERR_I(err), |
.RTY_I(1'b0), |
.TAG_I(4'b0), |
.TAG_O ( tag_o ) |
); |
|
// |
// Instantiation of PTC core |
// |
gpio_top gpio_top( |
// WISHBONE Interface |
.wb_clk_i(clk), |
.wb_rst_i(rst), |
.wb_cyc_i(cyc), |
.wb_adr_i(adr), |
.wb_dat_i(dat_ptc), |
.wb_sel_i(sel), |
.wb_we_i(we), |
.wb_stb_i(stb), |
.wb_dat_o(dat_m), |
.wb_ack_o(ack), |
.wb_err_o(err), |
.wb_inta_o(), |
|
// Auxiliary inputs interface |
.aux_i(gpio_aux), |
|
// External GPIO Interface |
.ext_pad_i(gpio_in), |
.clk_pad_i(gpio_eclk), |
.ext_pad_o(gpio_out), |
.ext_padoen_o(gpio_oen) |
); |
|
// |
// GPIO Monitor |
// |
gpio_mon gpio_mon( |
.gpio_aux(gpio_aux), |
.gpio_in(gpio_in), |
.gpio_eclk(gpio_eclk), |
.gpio_out(gpio_out), |
.gpio_oen(gpio_oen) |
); |
|
endmodule |
/tags/rel_6/bench/verilog/tb_tasks.v
0,0 → 1,992
////////////////////////////////////////////////////////////////////// |
//// //// |
//// GPIO Testbench Tasks //// |
//// //// |
//// This file is part of the GPIO project //// |
//// http://www.opencores.org/cores/gpio/ //// |
//// //// |
//// Description //// |
//// Testbench tasks. //// |
//// //// |
//// To Do: //// |
//// Nothing //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2001/12/25 17:21:06 lampret |
// Fixed two typos. |
// |
// Revision 1.5 2001/12/25 17:12:28 lampret |
// Added RGPIO_INTS. |
// |
// Revision 1.4 2001/11/15 02:26:32 lampret |
// Updated timing and fixed some typing errors. |
// |
// Revision 1.3 2001/09/18 16:37:55 lampret |
// Changed VCD output location. |
// |
// Revision 1.2 2001/09/18 15:43:27 lampret |
// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v. |
// |
// Revision 1.1 2001/08/21 21:39:27 lampret |
// Changed directory structure, port names and drfines. |
// |
// Revision 1.2 2001/07/14 20:37:23 lampret |
// Test bench improvements. |
// |
// Revision 1.1 2001/06/05 07:45:22 lampret |
// Added initial RTL and test benches. There are still some issues with these files. |
// |
// |
|
`include "timescale.v" |
`include "gpio_defines.v" |
`include "tb_defines.v" |
|
module tb_tasks; |
|
integer nr_failed; |
integer ints_disabled; |
integer ints_working; |
integer local_errs; |
|
parameter sh_addr = `GPIO_ADDRLH+1; |
parameter gw = `GPIO_IOS ; |
// |
// Count/report failed tests |
// |
task failed; |
begin |
$display("FAILED !!!"); |
nr_failed = nr_failed + 1; |
end |
endtask |
|
// |
// Set RGPIO_OUT register |
// |
task setout; |
input [31:0] val; |
|
reg [ 31:0 ] addr ; |
begin |
addr = `GPIO_RGPIO_OUT <<sh_addr ; |
#100 tb_top.wb_master.wr(`GPIO_RGPIO_OUT<<sh_addr, val, 4'b1111); |
/* $display ( " addr : %h %h", addr, val ) ; |
$display ( " out_pad : %h ", tb_top.gpio_top.out_pad ) ; |
$display ( " rgpio_aux : %h ", tb_top.gpio_top.rgpio_aux) ; |
$display ( " aux_i : %h ", tb_top.gpio_top.aux_i ) ; |
$display ( " rgpio_out : %h ", tb_top.gpio_top.rgpio_out ) ; |
*/ |
end |
|
endtask |
|
// |
// Set RGPIO_OE register |
// |
task setoe; |
input [31:0] val; |
|
begin |
#100 tb_top.wb_master.wr(`GPIO_RGPIO_OE<<sh_addr, val, 4'b1111); |
end |
|
endtask |
|
// |
// Set RGPIO_INTE register |
// |
task setinte; |
input [31:0] val; |
|
begin |
#100 tb_top.wb_master.wr(`GPIO_RGPIO_INTE<<sh_addr, val, 4'b1111); |
end |
|
endtask |
|
// |
// Set RGPIO_PTRIG register |
// |
task setptrig; |
input [31:0] val; |
|
begin |
#100 tb_top.wb_master.wr(`GPIO_RGPIO_PTRIG<<sh_addr, val, 4'b1111); |
end |
|
endtask |
|
// |
// Set RGPIO_AUX register |
// |
task setaux; |
input [31:0] val; |
|
begin |
#100 tb_top.wb_master.wr(`GPIO_RGPIO_AUX<<sh_addr, val, 4'b1111); |
end |
|
endtask |
|
// |
// Set RGPIO_CTRL register |
// |
task setctrl; |
input [31:0] val; |
|
begin |
#100 tb_top.wb_master.wr(`GPIO_RGPIO_CTRL<<sh_addr, val, 4'b1111); |
end |
|
endtask |
|
// |
// Set RGPIO_INTS register |
// |
task setints; |
input [31:0] val; |
|
begin |
#100 tb_top.wb_master.wr(`GPIO_RGPIO_INTS<<sh_addr, val, 4'b1111); |
end |
|
endtask |
|
// |
// Display RGPIO_IN register |
// |
task showin; |
|
reg [31:0] tmp; |
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp); |
$write(" RGPIO_IN: %h", tmp); |
end |
|
endtask |
|
// |
// Display RGPIO_OUT register |
// |
task showout; |
|
reg [31:0] tmp; |
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp); |
$write(" RGPIO_OUT: %h", tmp); |
end |
|
endtask |
|
|
// |
// Display RGPIO_OE register |
// |
task showoe; |
|
reg [31:0] tmp; |
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp); |
$write(" RGPIO_OE:%h", tmp); |
end |
|
endtask |
|
// |
// Display RGPIO_INTE register |
// |
task showinte; |
|
reg [31:0] tmp; |
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp); |
$write(" RGPIO_INTE:%h", tmp); |
end |
|
endtask |
|
// |
// Display RGPIO_PTRIG register |
// |
task showptrig; |
|
reg [31:0] tmp; |
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp); |
$write(" RGPIO_PTRIG:%h", tmp); |
end |
|
endtask |
|
// |
// Display RGPIO_AUX register |
// |
task showaux; |
|
reg [31:0] tmp; |
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp); |
$write(" RGPIO_AUX:%h", tmp); |
end |
|
endtask |
|
// |
// Display RGPIO_CTRL register |
// |
task showctrl; |
|
reg [31:0] tmp; |
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp); |
$write(" RGPIO_CTRL: %h", tmp); |
end |
|
endtask |
|
// |
// Display RGPIO_INTS register |
// |
task showints; |
|
reg [31:0] tmp; |
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTS<<sh_addr, tmp); |
$write(" RGPIO_INTS:%h", tmp); |
end |
|
endtask |
|
// |
// Compare parameter with RGPIO_IN register |
// |
task comp_in; |
input [31:0] val; |
output ret; |
|
reg [31:0] tmp; |
reg ret; |
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp); |
|
if (tmp == val) |
ret = 1; |
else |
ret = 0; |
end |
|
endtask |
|
// |
// Get RGPIO_IN register |
// |
task getin; |
output [31:0] tmp; |
|
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp); |
end |
|
endtask |
|
// |
// Get RGPIO_OUT register |
// |
task getout; |
output [31:0] tmp; |
|
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp); |
end |
|
endtask |
|
// |
// Get RGPIO_OE register |
// |
task getoe; |
output [31:0] tmp; |
|
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp); |
end |
|
endtask |
|
// |
// Get RGPIO_INTE register |
// |
task getinte; |
output [31:0] tmp; |
|
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp); |
end |
|
endtask |
|
// |
// Get RGPIO_PTRIG register |
// |
task getptrig; |
output [31:0] tmp; |
|
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp); |
end |
|
endtask |
|
// |
// Get RGPIO_AUX register |
// |
task getaux; |
output [31:0] tmp; |
|
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp); |
end |
|
endtask |
|
// |
// Get RGPIO_CTRL register |
// |
task getctrl; |
output [31:0] tmp; |
|
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp); |
end |
|
endtask |
|
// |
// Get RGPIO_INTS register |
// |
task getints; |
output [31:0] tmp; |
|
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTS<<sh_addr, tmp); |
end |
|
endtask |
|
// |
// Calculate a random and make it narrow to fit on GPIO I/O pins |
// |
task random_gpio; |
output [31:0] tmp; |
|
begin |
tmp = $random & ((1<<`GPIO_IOS)-1); |
end |
|
endtask |
|
// |
// Test operation of control bit RGPIO_CTRL[ECLK] |
// |
task test_eclk; |
reg [gw-1:0 ] l1, l2, l3; |
reg [gw-1:0 ] r1, r2, r3; |
begin |
|
// Set external clock to low state |
tb_top.gpio_mon.set_gpioeclk(0); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// |
// Phase 1 |
// |
// GPIO uses WISHBONE clock to latch gpio_in |
// |
|
// Put something on gpio_in pins |
random_gpio(r1); |
tb_top.gpio_mon.set_gpioin(r1); |
|
// Reset GPIO_CTRL |
setctrl(0); |
|
// Wait for time to advance |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Read GPIO_RGPIO_IN |
getin(l1); |
|
// |
// Phase 2 |
// |
// GPIO uses external clock to latch gpio_in |
// |
|
// Set GPIO to use external clock, NEC bit cleared |
setctrl(1 << `GPIO_RGPIO_CTRL_ECLK); |
|
// Put something else on gpio_in pins |
random_gpio(r2); |
tb_top.gpio_mon.set_gpioin(r2); |
|
// Make an external posedge clock pulse |
tb_top.gpio_mon.set_gpioeclk(0); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
tb_top.gpio_mon.set_gpioeclk(1); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Read RGPIO_IN |
getin(l2); |
|
// |
// Phase 3 |
// |
// Change GPIO inputs and WB clock but not external clock. |
// RGPIO_IN should not change. |
// |
|
// Put something else on gpio_in pins |
random_gpio(r3); |
tb_top.gpio_mon.set_gpioin(r3); |
|
// Wait for WB clock |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Read RGPIO_IN |
getin(l3); |
|
// |
// Phase 4 |
// |
// Compare phases |
// |
if (l1 == r1 && l2 == r2 && l2 == l3) |
$write("."); |
else |
local_errs = local_errs + 1; |
end |
endtask |
|
// |
// Test operation of control bit RGPIO_CTRL[NEC] |
// |
task test_nec; |
integer l1, l2; |
integer r1, r2; |
begin |
// |
// Phase 1 |
// |
// Compare RGPIO_IN before and after negative edge |
// |
|
// Set external clock to low state |
tb_top.gpio_mon.set_gpioeclk(0); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Set GPIO to use external clock and set RGPIO_CTRL[NEC] |
setctrl(1 << `GPIO_RGPIO_CTRL_ECLK | 1 << `GPIO_RGPIO_CTRL_NEC); |
|
// Put random on gpio inputs |
random_gpio(r1); |
tb_top.gpio_mon.set_gpioin(r1); |
|
// Advance time by making an external negedge clock pulse |
tb_top.gpio_mon.set_gpioeclk(1); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
tb_top.gpio_mon.set_gpioeclk(0); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Put something on gpio_in pins |
random_gpio(r2); |
tb_top.gpio_mon.set_gpioin(r2); |
|
// Make an external posedge clock pulse |
tb_top.gpio_mon.set_gpioeclk(0); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
tb_top.gpio_mon.set_gpioeclk(1); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Read RGPIO_IN (should be the same as r1) |
getin(l1); |
|
// Make an external negedge clock pulse |
tb_top.gpio_mon.set_gpioeclk(1); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
tb_top.gpio_mon.set_gpioeclk(0); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Read RGPIO_IN (should be the same as r2) |
getin(l2); |
|
// |
// Phase 2 |
// |
// Compare phases |
// |
// $display("l1 %h l2 %h r1 %h r2 %h", l1, l2, r1, r2); |
if (l1 == r1 && l2 == r2) |
$write("."); |
else |
local_errs = local_errs + 1; |
end |
endtask |
|
// |
// Test input polled mode, output mode and bidirectional |
// |
task test_simple; |
reg [gw-1:0] l1, l2, l3, l4; |
integer i, err; |
begin |
$write(" Testing input mode ..."); |
|
// |
// Phase 1 |
// |
// Compare RGPIO_IN and gpio_in |
// |
|
// Set GPIO to use WB clock |
setctrl(0); |
|
err = 0; |
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin |
// Put something on gpio_in pins |
random_gpio(l1); |
tb_top.gpio_mon.set_gpioin(l1); |
|
// Advance time |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Read GPIO_RGPIO_IN |
getin(l2); |
|
// Compare gpio_in and RGPIO_IN. Should be equal. |
if (l1 != l2) |
err = err + 1; |
end |
|
// Phase 2 |
// |
// Output result for previous test |
// |
if (!err) |
$display(" OK"); |
else |
failed; |
|
$write(" Testing output mode ..."); |
|
// |
// Phase 3 |
// |
// Compare RGPIO_OUT and gpio_out |
// |
|
err = 0; |
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin |
// Put something in RGPIO_OUT pins |
l1 = $random; |
setout(l1); |
|
// Advance time |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Read gpio_out |
tb_top.gpio_mon.get_gpioout(l2); |
|
// Compare gpio_out and RGPIO_OUT. Should be equal. |
if (l1 != l2) |
err = err + 1; |
end |
|
// Phase 4 |
// |
// Output result for previous test |
// |
if (!err) |
$display(" OK"); |
else |
failed; |
|
$write(" Testing bidirectional I/O ..."); |
|
// |
// Phase 5 |
// |
// Compare RGPIO_OE and gpio_oen |
// |
|
err = 0; |
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin |
// Put something in RGPIO_OE pins |
l1 = $random; |
setoe(l1); |
|
// Advance time |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Read gpio_oen |
tb_top.gpio_mon.get_gpiooen(l2); |
|
// Compare gpio_oen and RGPIO_OE. Should be exactly opposite. |
if (l1 != ~l2) |
err = err + 1; |
end |
|
// Phase 6 |
// |
// Output result for previous test |
// |
if (!err) |
$display(" OK"); |
else |
failed; |
|
$write(" Testing auxiliary feature ..."); |
|
// |
// Phase 7 |
// |
// Compare RGPIO_OUT, gpio_out, RGPIO_AUX and gpio_aux |
// |
|
err = 0; |
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin |
// Put something on gpio_aux pins |
l1 = $random; |
tb_top.gpio_mon.set_gpioaux(l1); |
|
// Put something in RGPIO_AUX pins |
l2 = $random; |
setaux(l2); |
|
// Put something in RGPIO_OUT pins |
l3 = $random; |
setout(l3); |
|
// Advance time |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Read gpio_out |
tb_top.gpio_mon.get_gpioout(l4); |
|
// Compare gpio_out, RGPIO_OUT, RGPIO_AUX and gpio_aux. |
// RGPIO_AUX specifies which gpio_aux bits and RGPIO_OUT |
// bits are present on gpio_out and where |
if ((l1 & l2 | l3 & ~l2) != l4) |
err = err + 1; |
end |
|
// Phase 8 |
// |
// Output result for previous test |
// |
if (!err) |
$display(" OK"); |
else |
failed; |
|
end |
endtask |
|
// |
// Test interrupts |
// |
task test_ints; |
integer l1, l2, l3, l4; |
integer i, rnd, err; |
integer r1; |
begin |
|
$write(" Testing control bit RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ..."); |
|
// |
// Phase 1 |
// |
// Generate patterns on inputs in interrupt mode |
// |
|
// Disable spurious interrupt monitor |
ints_disabled = 0; |
|
err = 0; |
for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin |
|
// Set gpio_in pins |
r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff; |
tb_top.gpio_mon.set_gpioin(r1); |
|
// Low level triggering |
setptrig(0); |
|
// Clear RGPIO_INTS |
setints(0); |
|
// Enable interrupts in RGPIO_CTRL |
setctrl(1 << `GPIO_RGPIO_CTRL_INTE); |
|
// Enable interrupts in RGPIO_INTE |
setinte(r1); |
|
// Advance time |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Sample interrupt request. Should be zero. |
l1 = tb_top.gpio_top.wb_inta_o; |
|
// Clear gpio_in pins |
tb_top.gpio_mon.set_gpioin(0); |
|
// Advance time |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Sample interrupt request. Should be one. |
l2 = tb_top.gpio_top.wb_inta_o; |
|
// Clear interrupt request |
setctrl(0); |
|
// Advance time |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Sample interrupt request. Should be zero. |
l3 = tb_top.gpio_top.wb_inta_o; |
|
// Get RGPIO_INTS. Should be nonzero. |
getints(l4); |
|
// Check for errors |
if (l1 || !l2 || l3 || (l4 != r1)) begin |
err = err +1; |
end |
end |
|
// Enable spurious interrupt monitor |
ints_disabled = 1; |
|
// Phase 2 |
// |
// Check results |
// |
if (!err) |
$display(" OK"); |
else |
failed; |
end |
endtask |
|
// |
// Test ptrig |
// |
task test_ptrig; |
integer l1, l2, l3; |
integer i, rnd, err; |
integer r1; |
begin |
$write(" Testing ptrig features ..."); |
|
// |
// Phase 1 |
// |
// Generate patterns on inputs in interrupt mode |
// |
|
// Disable spurious interrupt monitor |
ints_disabled = 0; |
|
err = 0; |
for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin |
|
// Set bits to one |
r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff; |
|
// Set gpio_in pins |
tb_top.gpio_mon.set_gpioin('h00000000); |
|
// Clear old interrupts |
setints(0); |
|
// High level triggering |
setptrig('hffffffff); |
|
// Enable interrupts in RGPIO_CTRL |
setctrl(1 << `GPIO_RGPIO_CTRL_INTE); |
|
// Enable interrupts in RGPIO_INTE |
setinte(r1); |
|
// Advance time |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Sample interrupt request. Should be zero. |
l1 = tb_top.gpio_top.wb_inta_o; |
|
// Clear gpio_in pins |
tb_top.gpio_mon.set_gpioin('hffffffff); |
|
// Advance time |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Sample interrupt request. Should be one. |
l2 = tb_top.gpio_top.wb_inta_o; |
|
// Clear interrupt request |
setctrl(0); |
setints(0); |
|
// Advance time |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Sample interrupt request. Should be zero. |
l3 = tb_top.gpio_top.wb_inta_o; |
|
// Check for errors |
if (l1 || !l2 || l3) |
err = err +1; |
end |
|
// Enable spurious interrupt monitor |
ints_disabled = 1; |
|
// Phase 2 |
// |
// Check results |
// |
if (!err) |
$display(" OK"); |
else |
failed; |
end |
endtask |
|
// |
// Do continues check for interrupts |
// |
always @(posedge tb_top.gpio_top.wb_inta_o) |
if (ints_disabled) begin |
$display("Spurious interrupt detected. "); |
failed; |
ints_working = 9876; |
$display; |
end |
|
// |
// Start of testbench test tasks |
// |
integer i; |
initial begin |
`ifdef GPIO_DUMP_VCD |
$dumpfile("../out/tb_top.vcd"); |
$dumpvars(0); |
`endif |
nr_failed = 0; |
ints_disabled = 1; |
ints_working = 0; |
tb_top.gpio_mon.set_gpioin(0); |
tb_top.gpio_mon.set_gpioaux(0); |
tb_top.gpio_mon.set_gpioeclk(0); |
$display; |
$display("###"); |
$display("### GPIO IP Core Verification ###"); |
$display("###"); |
$display; |
$display("I. Testing correct operation of RGPIO_CTRL control bits"); |
$display; |
|
|
$write(" Testing control bit RGPIO_CTRL[ECLK] ..."); |
local_errs = 0; |
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) |
test_eclk; |
if (local_errs == 0) |
$display(" OK"); |
else |
failed; |
|
|
$write(" Testing control bit RGPIO_CTRL[NEC] ..."); |
local_errs = 0; |
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) |
test_nec; |
if (local_errs == 0) |
$display(" OK"); |
else |
failed; |
|
test_ints; |
|
$display; |
$display("II. Testing modes of operation ..."); |
$display; |
|
test_simple; |
test_ptrig; |
|
$display; |
$display("###"); |
$display("### FAILED TESTS: %d ###", nr_failed); |
$display("###"); |
$display; |
$finish; |
end |
|
endmodule |
/tags/rel_6/bench/verilog/tb_defines.v
0,0 → 1,76
////////////////////////////////////////////////////////////////////// |
//// //// |
//// GPIO Testbench Definitions //// |
//// //// |
//// This file is part of the GPIO project //// |
//// http://www.opencores.org/cores/gpio/ //// |
//// //// |
//// Description //// |
//// Testbench definitions that affect how testbench simulation //// |
//// is performed. //// |
//// //// |
//// To Do: //// |
//// Nothing //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/21 22:01:50 lampret |
// More intensive verification. |
// |
// Revision 1.1 2001/08/21 21:39:27 lampret |
// Changed directory structure, port names and drfines. |
// |
// Revision 1.2 2001/07/14 20:37:23 lampret |
// Test bench improvements. |
// |
// Revision 1.1 2001/06/05 07:45:22 lampret |
// Added initial RTL and test benches. There are still some issues with these files. |
// |
// |
|
// |
// Define if you want VCD dump |
// |
`define GPIO_DUMP_VCD |
|
// |
// Intensity of verification |
// |
// Higher number means more intensive verification. Higher number |
// means more loops of each subtest (e.g. for some subtests |
// 5 means 50 loops, for others 100 etc). Good numbers are from 1 |
// (very fast and very little verification) to 200 (slow but thorough). |
// Default is 200. |
// |
`define GPIO_VERIF_INTENSITY 200 |
/tags/rel_6/bench/verilog/clkrst.v
0,0 → 1,80
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Clock and Reset Generator //// |
//// //// |
//// This file is part of the GPIO project //// |
//// http://www.opencores.org/cores/gpio/ //// |
//// //// |
//// Description //// |
//// Clock and reset generator. //// |
//// //// |
//// To Do: //// |
//// Nothing //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/06/05 07:45:21 lampret |
// Added initial RTL and test benches. There are still some issues with these files. |
// |
// |
|
`include "timescale.v" |
|
module clkrst(clk_o, rst_o); |
|
// |
// I/O ports |
// |
output clk_o; // Clock |
output rst_o; // Reset |
|
// |
// Internal regs |
// |
reg clk_o; // Clock |
reg rst_o; // Reset |
|
initial begin |
clk_o = 0; |
rst_o = 1; |
#20; |
rst_o = 0; |
end |
|
// |
// Clock |
// |
always #4 clk_o = ~clk_o; |
|
endmodule |
/tags/rel_6/bench/verilog/timescale.v
0,0 → 1,80
`timescale 1ns/10ps |
/tags/rel_6/rtl/verilog/gpio_top.v
0,0 → 1,769
////////////////////////////////////////////////////////////////////// |
//// //// |
//// WISHBONE General-Purpose I/O //// |
//// //// |
//// This file is part of the GPIO project //// |
//// http://www.opencores.org/cores/gpio/ //// |
//// //// |
//// Description //// |
//// Implementation of GPIO IP core according to //// |
//// GPIO IP core specification document. //// |
//// //// |
//// To Do: //// |
//// Nothing //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.14 2003/11/06 13:59:07 gorand |
// added support for 8-bit access to registers. |
// |
// Revision 1.13 2002/11/18 22:35:18 lampret |
// Bug fix. Interrupts were also asserted when condition was not met. |
// |
// Revision 1.12 2002/11/11 21:36:28 lampret |
// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC]. |
// |
// Revision 1.11 2002/03/13 20:56:28 lampret |
// Removed zero padding as per Avi Shamli suggestion. |
// |
// Revision 1.10 2002/03/13 20:47:57 lampret |
// Ports changed per Ran Aviram suggestions. |
// |
// Revision 1.9 2002/03/09 03:43:27 lampret |
// Interrupt is asserted only when an input changes (code patch by Jacob Gorban) |
// |
// Revision 1.8 2002/01/14 19:06:28 lampret |
// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification. |
// |
// Revision 1.7 2001/12/25 17:21:21 lampret |
// Fixed two typos. |
// |
// Revision 1.6 2001/12/25 17:12:35 lampret |
// Added RGPIO_INTS. |
// |
// Revision 1.5 2001/12/12 20:35:53 lampret |
// Fixing style. |
// |
// Revision 1.4 2001/12/12 07:12:58 lampret |
// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS) |
// |
// Revision 1.3 2001/11/15 02:24:37 lampret |
// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS. |
// |
// Revision 1.2 2001/10/31 02:26:51 lampret |
// Fixed wb_err_o. |
// |
// Revision 1.1 2001/09/18 18:49:07 lampret |
// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v. |
// |
// Revision 1.1 2001/08/21 21:39:28 lampret |
// Changed directory structure, port names and drfines. |
// |
// Revision 1.2 2001/07/14 20:39:26 lampret |
// Better configurability. |
// |
// Revision 1.1 2001/06/05 07:45:26 lampret |
// Added initial RTL and test benches. There are still some issues with these files. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "gpio_defines.v" |
|
module gpio_top( |
// WISHBONE Interface |
wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i, |
wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o, |
|
// Auxiliary inputs interface |
aux_i, |
|
// External GPIO Interface |
ext_pad_i, clk_pad_i, ext_pad_o, ext_padoen_o |
); |
|
parameter dw = 32; |
parameter aw = `GPIO_ADDRHH+1; |
parameter gw = `GPIO_IOS; |
// |
// WISHBONE Interface |
// |
input wb_clk_i; // Clock |
input wb_rst_i; // Reset |
input wb_cyc_i; // cycle valid input |
input [aw-1:0] wb_adr_i; // address bus inputs |
input [dw-1:0] wb_dat_i; // input data bus |
input [3:0] wb_sel_i; // byte select inputs |
input wb_we_i; // indicates write transfer |
input wb_stb_i; // strobe input |
output [dw-1:0] wb_dat_o; // output data bus |
output wb_ack_o; // normal termination |
output wb_err_o; // termination w/ error |
output wb_inta_o; // Interrupt request output |
|
// Auxiliary Inputs Interface |
input [gw-1:0] aux_i; // Auxiliary inputs |
|
// |
// External GPIO Interface |
// |
input [gw-1:0] ext_pad_i; // GPIO Inputs |
input clk_pad_i; // GPIO Eclk |
output [gw-1:0] ext_pad_o; // GPIO Outputs |
output [gw-1:0] ext_padoen_o; // GPIO output drivers enables |
|
`ifdef GPIO_IMPLEMENTED |
|
// |
// GPIO Input Register (or no register) |
// |
`ifdef GPIO_RGPIO_IN |
reg [gw-1:0] rgpio_in; // RGPIO_IN register |
`else |
wire [gw-1:0] rgpio_in; // No register |
`endif |
|
// |
// GPIO Output Register (or no register) |
// |
`ifdef GPIO_RGPIO_OUT |
reg [gw-1:0] rgpio_out; // RGPIO_OUT register |
`else |
wire [gw-1:0] rgpio_out; // No register |
`endif |
|
// |
// GPIO Output Driver Enable Register (or no register) |
// |
`ifdef GPIO_RGPIO_OE |
reg [gw-1:0] rgpio_oe; // RGPIO_OE register |
`else |
wire [gw-1:0] rgpio_oe; // No register |
`endif |
|
// |
// GPIO Interrupt Enable Register (or no register) |
// |
`ifdef GPIO_RGPIO_INTE |
reg [gw-1:0] rgpio_inte; // RGPIO_INTE register |
`else |
wire [gw-1:0] rgpio_inte; // No register |
`endif |
|
// |
// GPIO Positive edge Triggered Register (or no register) |
// |
`ifdef GPIO_RGPIO_PTRIG |
reg [gw-1:0] rgpio_ptrig; // RGPIO_PTRIG register |
`else |
wire [gw-1:0] rgpio_ptrig; // No register |
`endif |
|
// |
// GPIO Auxiliary select Register (or no register) |
// |
`ifdef GPIO_RGPIO_AUX |
reg [gw-1:0] rgpio_aux; // RGPIO_AUX register |
`else |
wire [gw-1:0] rgpio_aux; // No register |
`endif |
|
// |
// GPIO Control Register (or no register) |
// |
`ifdef GPIO_RGPIO_CTRL |
reg [3:0] rgpio_ctrl; // RGPIO_CTRL register |
`else |
wire [3:0] rgpio_ctrl; // No register |
`endif |
|
// |
// GPIO Interrupt Status Register (or no register) |
// |
`ifdef GPIO_RGPIO_INTS |
reg [gw-1:0] rgpio_ints; // RGPIO_INTS register |
`else |
wire [gw-1:0] rgpio_ints; // No register |
`endif |
|
// |
// Internal wires & regs |
// |
wire rgpio_out_sel; // RGPIO_OUT select |
wire rgpio_oe_sel; // RGPIO_OE select |
wire rgpio_inte_sel; // RGPIO_INTE select |
wire rgpio_ptrig_sel;// RGPIO_PTRIG select |
wire rgpio_aux_sel; // RGPIO_AUX select |
wire rgpio_ctrl_sel; // RGPIO_CTRL select |
wire rgpio_ints_sel; // RGPIO_INTS select |
wire latch_clk; // Latch clock |
wire full_decoding; // Full address decoding qualification |
wire [gw-1:0] in_muxed; // Muxed inputs |
wire wb_ack; // WB Acknowledge |
wire wb_err; // WB Error |
wire wb_inta; // WB Interrupt |
reg [dw-1:0] wb_dat; // WB Data out |
`ifdef GPIO_REGISTERED_WB_OUTPUTS |
reg wb_ack_o; // WB Acknowledge |
reg wb_err_o; // WB Error |
reg wb_inta_o; // WB Interrupt |
reg [dw-1:0] wb_dat_o; // WB Data out |
`endif |
wire [gw-1:0] out_pad; // GPIO Outputs |
`ifdef GPIO_REGISTERED_IO_OUTPUTS |
reg [gw-1:0] ext_pad_o; // GPIO Outputs |
`endif |
wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock |
wire pext_clk; // External clock for posedge flops |
reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs |
`ifdef GPIO_NO_NEGEDGE_FLOPS |
`else |
reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs |
`endif |
|
// |
// All WISHBONE transfer terminations are successful except when: |
// a) full address decoding is enabled and address doesn't match |
// any of the GPIO registers |
// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero |
// |
|
// |
// WB Acknowledge |
// |
assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o; |
|
// |
// Optional registration of WB Ack |
// |
`ifdef GPIO_REGISTERED_WB_OUTPUTS |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
wb_ack_o <= #1 1'b0; |
else |
wb_ack_o <= #1 wb_ack & ~wb_ack_o & (!wb_err) ; |
`else |
assign wb_ack_o = wb_ack; |
`endif |
|
// |
// WB Error |
// |
`ifdef GPIO_FULL_DECODE |
`ifdef GPIO_STRICT_32BIT_ACCESS |
assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111)); |
`else |
assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding; |
`endif |
`else |
`ifdef GPIO_STRICT_32BIT_ACCESS |
assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111); |
`else |
assign wb_err = 1'b0; |
`endif |
`endif |
|
// |
// Optional registration of WB error |
// |
`ifdef GPIO_REGISTERED_WB_OUTPUTS |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
wb_err_o <= #1 1'b0; |
else |
wb_err_o <= #1 wb_err & ~wb_err_o; |
`else |
assign wb_err_o = wb_err; |
`endif |
|
// |
// Full address decoder |
// |
`ifdef GPIO_FULL_DECODE |
assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) & |
(wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}}); |
`else |
assign full_decoding = 1'b1; |
`endif |
|
// |
// GPIO registers address decoder |
// |
assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding; |
assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding; |
assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding; |
assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding; |
assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding; |
assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding; |
assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding; |
|
// |
// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit |
// |
`ifdef GPIO_RGPIO_CTRL |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
rgpio_ctrl <= #1 4'b0; |
else if (rgpio_ctrl_sel && wb_we_i) |
rgpio_ctrl <= #1 wb_dat_i[3:0]; |
else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE]) |
rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o; |
`else |
assign rgpio_ctrl = 4'h01; // RGPIO_CTRL[EN] = 1 |
`endif |
|
// |
// Write to RGPIO_OUT |
// |
`ifdef GPIO_RGPIO_OUT |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
rgpio_out <= #1 {gw{1'b0}}; |
else if (rgpio_out_sel && wb_we_i) |
begin |
`ifdef GPIO_STRICT_32BIT_ACCESS |
rgpio_out <= #1 wb_dat_i[gw-1:0]; |
`endif |
|
`ifdef GPIO_WB_BYTES4 |
if ( wb_sel_i [3] == 1'b1 ) |
rgpio_out [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; |
if ( wb_sel_i [2] == 1'b1 ) |
rgpio_out [23:16] <= #1 wb_dat_i [23:16] ; |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_out [15:8] <= #1 wb_dat_i [15:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_out [7:0] <= #1 wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES3 |
if ( wb_sel_i [2] == 1'b1 ) |
rgpio_out [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_out [15:8] <= #1 wb_dat_i [15:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_out [7:0] <= #1 wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES2 |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_out [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_out [7:0] <= #1 wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES1 |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_out [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; |
`endif |
end |
|
`else |
assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0 |
`endif |
|
// |
// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted. |
// |
`ifdef GPIO_RGPIO_OE |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
rgpio_oe <= #1 {gw{1'b0}}; |
else if (rgpio_oe_sel && wb_we_i) |
begin |
`ifdef GPIO_STRICT_32BIT_ACCESS |
rgpio_oe <= #1 ~wb_dat_i[gw-1:0]; |
`endif |
|
`ifdef GPIO_WB_BYTES4 |
if ( wb_sel_i [3] == 1'b1 ) |
rgpio_oe [gw-1:24] <= #1 ~wb_dat_i [gw-1:24] ; |
if ( wb_sel_i [2] == 1'b1 ) |
rgpio_oe [23:16] <= #1 ~wb_dat_i [23:16] ; |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_oe [15:8] <= #1 ~wb_dat_i [15:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES3 |
if ( wb_sel_i [2] == 1'b1 ) |
rgpio_oe [gw-1:16] <= #1 ~wb_dat_i [gw-1:16] ; |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_oe [15:8] <= #1 ~wb_dat_i [15:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES2 |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_oe [gw-1:8] <= #1 ~wb_dat_i [gw-1:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES1 |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_oe [gw-1:0] <= #1 ~wb_dat_i [gw-1:0] ; |
`endif |
end |
|
`else |
assign rgpio_oe = `GPIO_DEF_RPGIO_OE; // RGPIO_OE = 0x0 |
`endif |
|
// |
// Write to RGPIO_INTE |
// |
`ifdef GPIO_RGPIO_INTE |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
rgpio_inte <= #1 {gw{1'b0}}; |
else if (rgpio_inte_sel && wb_we_i) |
begin |
`ifdef GPIO_STRICT_32BIT_ACCESS |
rgpio_inte <= #1 wb_dat_i[gw-1:0]; |
`endif |
|
`ifdef GPIO_WB_BYTES4 |
if ( wb_sel_i [3] == 1'b1 ) |
rgpio_inte [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; |
if ( wb_sel_i [2] == 1'b1 ) |
rgpio_inte [23:16] <= #1 wb_dat_i [23:16] ; |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES3 |
if ( wb_sel_i [2] == 1'b1 ) |
rgpio_inte [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES2 |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_inte [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES1 |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_inte [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; |
`endif |
end |
|
|
`else |
assign rgpio_inte = `GPIO_DEF_RPGIO_INTE; // RGPIO_INTE = 0x0 |
`endif |
|
// |
// Write to RGPIO_PTRIG |
// |
`ifdef GPIO_RGPIO_PTRIG |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
rgpio_ptrig <= #1 {gw{1'b0}}; |
else if (rgpio_ptrig_sel && wb_we_i) |
begin |
`ifdef GPIO_STRICT_32BIT_ACCESS |
rgpio_ptrig <= #1 wb_dat_i[gw-1:0]; |
`endif |
|
`ifdef GPIO_WB_BYTES4 |
if ( wb_sel_i [3] == 1'b1 ) |
rgpio_ptrig [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; |
if ( wb_sel_i [2] == 1'b1 ) |
rgpio_ptrig [23:16] <= #1 wb_dat_i [23:16] ; |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES3 |
if ( wb_sel_i [2] == 1'b1 ) |
rgpio_ptrig [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES2 |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_ptrig [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES1 |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_ptrig [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; |
`endif |
end |
|
`else |
assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG; // RGPIO_PTRIG = 0x0 |
`endif |
|
// |
// Write to RGPIO_AUX |
// |
`ifdef GPIO_RGPIO_AUX |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
rgpio_aux <= #1 {gw{1'b0}}; |
else if (rgpio_aux_sel && wb_we_i) |
begin |
`ifdef GPIO_STRICT_32BIT_ACCESS |
rgpio_aux <= #1 wb_dat_i[gw-1:0]; |
`endif |
|
`ifdef GPIO_WB_BYTES4 |
if ( wb_sel_i [3] == 1'b1 ) |
rgpio_aux [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; |
if ( wb_sel_i [2] == 1'b1 ) |
rgpio_aux [23:16] <= #1 wb_dat_i [23:16] ; |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES3 |
if ( wb_sel_i [2] == 1'b1 ) |
rgpio_aux [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES2 |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_aux [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES1 |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_aux [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; |
`endif |
end |
|
`else |
assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0 |
`endif |
|
// |
// Latch into RGPIO_IN |
// |
`ifdef GPIO_RGPIO_IN |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
rgpio_in <= #1 {gw{1'b0}}; |
else |
rgpio_in <= #1 in_muxed; |
`else |
assign rgpio_in = in_muxed; |
`endif |
|
// |
// Mux inputs directly from input pads with inputs sampled by external clock |
// |
assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : ext_pad_i; |
|
// |
// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed. |
// If negedge flops are allowed, pext_clk only clocks posedge flops. |
// |
`ifdef GPIO_NO_NEGEDGE_FLOPS |
`ifdef GPIO_NO_CLKPAD_LOGIC |
assign pext_clk = clk_pad_i; |
`else |
assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~clk_pad_i : clk_pad_i; |
`endif |
`else |
assign pext_clk = clk_pad_i; |
`endif |
|
// |
// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops. |
// |
`ifdef GPIO_NO_NEGEDGE_FLOPS |
assign extc_in = pextc_sampled; |
`else |
assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled; |
`endif |
|
// |
// Latch using posedge external clock |
// |
always @(posedge pext_clk or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled <= #1 {gw{1'b0}}; |
else |
pextc_sampled <= #1 ext_pad_i; |
|
// |
// Latch using negedge external clock |
// |
`ifdef GPIO_NO_NEGEDGE_FLOPS |
`else |
always @(negedge clk_pad_i or posedge wb_rst_i) |
if (wb_rst_i) |
nextc_sampled <= #1 {gw{1'b0}}; |
else |
nextc_sampled <= #1 ext_pad_i; |
`endif |
|
// |
// Mux all registers when doing a read of GPIO registers |
// |
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or |
rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints) |
case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case |
`ifdef GPIO_READREGS |
`GPIO_RGPIO_OUT: begin |
wb_dat[dw-1:0] = rgpio_out; |
end |
`GPIO_RGPIO_OE: begin |
wb_dat[dw-1:0] = ~rgpio_oe; |
end |
`GPIO_RGPIO_INTE: begin |
wb_dat[dw-1:0] = rgpio_inte; |
end |
`GPIO_RGPIO_PTRIG: begin |
wb_dat[dw-1:0] = rgpio_ptrig; |
end |
`GPIO_RGPIO_AUX: begin |
wb_dat[dw-1:0] = rgpio_aux; |
end |
`GPIO_RGPIO_CTRL: begin |
wb_dat[3:0] = rgpio_ctrl; |
wb_dat[dw-1:4] = {dw-4{1'b0}}; |
end |
`endif |
`GPIO_RGPIO_INTS: begin |
wb_dat[dw-1:0] = rgpio_ints; |
end |
default: begin |
wb_dat[dw-1:0] = rgpio_in; |
end |
endcase |
|
// |
// WB data output |
// |
`ifdef GPIO_REGISTERED_WB_OUTPUTS |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
wb_dat_o <= #1 {dw{1'b0}}; |
else |
wb_dat_o <= #1 wb_dat; |
`else |
assign wb_dat_o = wb_dat; |
`endif |
|
// |
// RGPIO_INTS |
// |
`ifdef GPIO_RGPIO_INTS |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
rgpio_ints <= #1 {gw{1'b0}}; |
else if (rgpio_ints_sel && wb_we_i) |
rgpio_ints <= #1 wb_dat_i[gw-1:0]; |
else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE]) |
rgpio_ints <= #1 (rgpio_ints | ((ext_pad_i ^ rgpio_in) & ~(ext_pad_i ^ rgpio_ptrig)) & rgpio_inte); |
`else |
assign rgpio_ints = (rgpio_ints | ((ext_pad_i ^ rgpio_in) & ~(ext_pad_i ^ rgpio_ptrig)) & rgpio_inte); |
`endif |
|
// |
// Generate interrupt request |
// |
assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0; |
|
// |
// Optional registration of WB interrupt |
// |
`ifdef GPIO_REGISTERED_WB_OUTPUTS |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
wb_inta_o <= #1 1'b0; |
else |
wb_inta_o <= #1 wb_inta; |
`else |
assign wb_inta_o = wb_inta; |
`endif |
|
// |
// Output enables are RGPIO_OE bits |
// |
assign ext_padoen_o = rgpio_oe; |
|
// |
// Generate GPIO outputs |
// |
assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux; |
|
// |
// Optional registration of GPIO outputs |
// |
`ifdef GPIO_REGISTERED_IO_OUTPUTS |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
ext_pad_o <= #1 {gw{1'b0}}; |
else |
ext_pad_o <= #1 out_pad; |
`else |
assign ext_pad_o = out_pad; |
`endif |
|
`else |
|
// |
// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL |
// is cleared and WISHBONE transfers complete with errors |
// |
assign wb_inta_o = 1'b0; |
assign wb_ack_o = 1'b0; |
assign wb_err_o = wb_cyc_i & wb_stb_i; |
assign ext_padoen_o = {gw{1'b1}}; |
assign ext_pad_o = {gw{1'b0}}; |
|
// |
// Read GPIO registers |
// |
assign wb_dat_o = {dw{1'b0}}; |
|
`endif |
|
endmodule |
/tags/rel_6/rtl/verilog/gpio_defines.v
0,0 → 1,246
////////////////////////////////////////////////////////////////////// |
//// //// |
//// WISHBONE GPIO Definitions //// |
//// //// |
//// This file is part of the GPIO project //// |
//// http://www.opencores.org/cores/gpio/ //// |
//// //// |
//// Description //// |
//// GPIO IP Definitions. //// |
//// //// |
//// To Do: //// |
//// Nothing //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2003/10/02 18:54:35 simons |
// GPIO signals muxed with other peripherals, higland_board fixed. |
// |
// Revision 1.1.1.1 2003/06/24 09:09:23 simons |
// This files were moved here from toplevel folder. |
// |
// Revision 1.1.1.1 2003/06/11 18:51:13 simons |
// Initial import. |
// |
// Revision 1.5 2002/11/11 21:36:28 lampret |
// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC]. |
// |
// Revision 1.4 2002/05/06 18:25:31 lampret |
// negedge flops are enabled by default. |
// |
// Revision 1.3 2001/12/25 17:12:35 lampret |
// Added RGPIO_INTS. |
// |
// Revision 1.2 2001/11/15 02:24:37 lampret |
// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS. |
// |
// Revision 1.1 2001/09/18 18:49:07 lampret |
// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v. |
// |
// Revision 1.1 2001/08/21 21:39:28 lampret |
// Changed directory structure, port names and drfines. |
// |
// Revision 1.3 2001/07/15 00:21:10 lampret |
// Registers can be omitted and will have certain default values |
// |
// Revision 1.2 2001/07/14 20:39:26 lampret |
// Better configurability. |
// |
// Revision 1.1 2001/06/05 07:45:26 lampret |
// Added initial RTL and test benches. There are still some issues with these files. |
// |
// |
|
// |
// Number of GPIO I/O signals |
// |
// This is the most important parameter of the GPIO IP core. It defines how many |
// I/O signals core has. Range is from 1 to 32. If more than 32 I/O signals are |
// required, use several instances of GPIO IP core. |
// |
// Default is 16. |
// |
`define GPIO_IOS 31 |
|
|
// |
// Undefine this one if you don't want to remove GPIO block from your design |
// but you also don't need it. When it is undefined, all GPIO ports still |
// remain valid and the core can be synthesized however internally there is |
// no GPIO funationality. |
// |
// Defined by default (duhh !). |
// |
`define GPIO_IMPLEMENTED |
|
// |
// Define to register all WISHBONE outputs. |
// |
// Register outputs if you are using GPIO core as a block and synthesizing |
// and place&routing it separately from the rest of the system. |
// |
// If you do not need registered outputs, you can save some area by not defining |
// this macro. By default it is defined. |
// |
`define GPIO_REGISTERED_WB_OUTPUTS |
|
// |
// Define to register all GPIO pad outputs. |
// |
// Register outputs if you are using GPIO core as a block and synthesizing |
// and place&routing it separately from the rest of the system. |
// |
// If you do not need registered outputs, you can save some area by not defining |
// this macro. By default it is defined. |
// |
`define GPIO_REGISTERED_IO_OUTPUTS |
|
// |
// Define to avoid using negative edge clock flip-flops for external clock |
// (caused by RGPIO_CTRL[NEC] bit. Instead an inverted external clock with |
// positive edge clock flip-flops will be used. |
// |
// By default it is not defined. |
// |
//`define GPIO_NO_NEGEDGE_FLOPS |
|
// |
// If GPIO_NO_NEGEDGE_FLOPS is defined, a mux needs to be placed on external clock |
// clk_pad_i to implement RGPIO_CTRL[NEC] functionality. If no mux is allowed on |
// clock signal, enable the following define. |
// |
// By default it is not defined. |
// |
//`define GPIO_NO_CLKPAD_LOGIC |
|
// |
// Undefine if you don't need to read GPIO registers except for RGPIO_IN register. |
// When it is undefined all reads of GPIO registers return RGPIO_IN register. This |
// is usually useful if you want really small area (for example when implemented in |
// FPGA). |
// |
// To follow GPIO IP core specification document this one must be defined. Also to |
// successfully run the test bench it must be defined. By default it is defined. |
// |
`define GPIO_READREGS |
|
// |
// Full WISHBONE address decoding |
// |
// It is is undefined, partial WISHBONE address decoding is performed. |
// Undefine it if you need to save some area. |
// |
// By default it is defined. |
// |
`define GPIO_FULL_DECODE |
|
// |
// Strict 32-bit WISHBONE access |
// |
// If this one is defined, all WISHBONE accesses must be 32-bit. If it is |
// not defined, err_o is asserted whenever 8- or 16-bit access is made. |
// Undefine it if you need to save some area. |
// |
// By default it is defined. |
// |
//`define GPIO_STRICT_32BIT_ACCESS |
// |
`ifndef GPIO_STRICT_32BIT_ACCESS |
// added by gorand : |
// if GPIO_STRICT_32BIT_ACCESS is not defined, |
// depending on number of gpio I/O lines, the following are defined : |
// if the number of I/O lines is in range 1-8, GPIO_WB_BYTES1 is defined, |
// if the number of I/O lines is in range 9-16, GPIO_WB_BYTES2 is defined, |
// if the number of I/O lines is in range 17-24, GPIO_WB_BYTES3 is defined, |
// if the number of I/O lines is in range 25-32, GPIO_WB_BYTES4 is defined, |
|
`define GPIO_WB_BYTES4 |
`endif |
|
// |
// WISHBONE address bits used for full decoding of GPIO registers. |
// |
`define GPIO_ADDRHH 6 |
`define GPIO_ADDRHL 5 |
`define GPIO_ADDRLH 1 |
`define GPIO_ADDRLL 0 |
|
// |
// Bits of WISHBONE address used for partial decoding of GPIO registers. |
// |
// Default 4:2. |
// |
`define GPIO_OFS_BITS `GPIO_ADDRHL-1:`GPIO_ADDRLH+1 |
|
// |
// Addresses of GPIO registers |
// |
// To comply with GPIO IP core specification document they must go from |
// address 0 to address 0x18 in the following order: RGPIO_IN, RGPIO_OUT, |
// RGPIO_OE, RGPIO_INTE, RGPIO_PTRIG, RGPIO_AUX and RGPIO_CTRL |
// |
// If particular register is not needed, it's address definition can be omitted |
// and the register will not be implemented. Instead a fixed default value will |
// be used. |
// |
`define GPIO_RGPIO_IN 3'h0 // Address 0x00 |
`define GPIO_RGPIO_OUT 3'h1 // Address 0x04 |
`define GPIO_RGPIO_OE 3'h2 // Address 0x08 |
`define GPIO_RGPIO_INTE 3'h3 // Address 0x0c |
`define GPIO_RGPIO_PTRIG 3'h4 // Address 0x10 |
`define GPIO_RGPIO_AUX 3'h5 // Address 0x14 |
`define GPIO_RGPIO_CTRL 3'h6 // Address 0x18 |
`define GPIO_RGPIO_INTS 3'h7 // Address 0x1c |
|
// |
// Default values for unimplemented GPIO registers |
// |
`define GPIO_DEF_RGPIO_IN `GPIO_IOS'h0 |
`define GPIO_DEF_RGPIO_OUT `GPIO_IOS'h0 |
`define GPIO_DEF_RGPIO_OE `GPIO_IOS'h0 |
`define GPIO_DEF_RGPIO_INTE `GPIO_IOS'h0 |
`define GPIO_DEF_RGPIO_PTRIG `GPIO_IOS'h0 |
`define GPIO_DEF_RGPIO_AUX `GPIO_IOS'h0 |
`define GPIO_DEF_RGPIO_CTRL `GPIO_IOS'h0 |
|
// |
// RGPIO_CTRL bits |
// |
// To comply with the GPIO IP core specification document they must go from |
// bit 0 to bit 3 in the following order: ECLK, NEC, INTE, INT |
// |
`define GPIO_RGPIO_CTRL_ECLK 0 |
`define GPIO_RGPIO_CTRL_NEC 1 |
`define GPIO_RGPIO_CTRL_INTE 2 |
`define GPIO_RGPIO_CTRL_INTS 3 |
/tags/rel_6/doc/gpio_spec.pdf
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tags/rel_6/doc/gpio_spec.pdf
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+application/octet-stream
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Index: tags/rel_6/doc/src/gpio_spec.doc
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/rel_6/doc/src/gpio_spec.doc
===================================================================
--- tags/rel_6/doc/src/gpio_spec.doc (nonexistent)
+++ tags/rel_6/doc/src/gpio_spec.doc (revision 38)
tags/rel_6/doc/src/gpio_spec.doc
Property changes :
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/rel_6/sim/rtl_sim/bin/sim.sh
===================================================================
--- tags/rel_6/sim/rtl_sim/bin/sim.sh (nonexistent)
+++ tags/rel_6/sim/rtl_sim/bin/sim.sh (revision 38)
@@ -0,0 +1,125 @@
+#!/bin/bash
+
+#
+# This script runs RTL and gate-level simulation using different simultion tools.
+# Right now Cadence Verilog-XL and NCSim are supported.
+#
+# Author: Damjan Lampret
+#
+
+#
+# User definitions
+#
+
+# Set simulation tool you are using (xl, ncsim, ncver)
+SIMTOOL=ncsim
+
+# Set test bench top module(s)
+TB_TOP="tb_tasks"
+
+# Set include directories
+INCLUDE_DIRS="../../../rtl/verilog/ ../../../bench/verilog/"
+
+# Set test bench files
+BENCH_FILES="../../../bench/verilog/*.v"
+
+# Set RTL source files
+RTL_FILES="../../../rtl/verilog/*.v"
+
+# Set gate-level netlist files
+GATE_FILES="../syn/out/final_gpio.v"
+
+# Set libraries (standard cell etc.)
+LIB_FILES="/libs/Virtual_silicon/UMCL18U250D2_2.1/verilog_simulation_models/*.v"
+
+# Set parameters for simulation tool
+if [ $SIMTOOL == xl ]; then
+ PARAM="+turbo+3 -q"
+ for i in $INCLUDE_DIRS; do
+ INCDIR=$INCDIR" +incdir+$i"
+ done
+elif [ $SIMTOOL == ncver ]; then
+ NCVER_PARAM=""
+ for i in $INCLUDE_DIRS; do
+ INCDIR=$INCDIR" +incdir+$i"
+ done
+elif [ $SIMTOOL == ncsim ]; then
+ NCPREP_PARAM="-UPDATE +overwrite"
+ NCSIM_PARAM="-MESSAGES -NOCOPYRIGHT"
+ for i in $INCLUDE_DIRS; do
+ INCDIR=$INCDIR" +incdir+$i"
+ done
+else
+ echo "$SIMTOOL is unsupported simulation tool."
+ exit 0
+fi
+
+#
+# Don't change anything below unless you know what you are doing
+#
+
+# Run simulation in sim directory
+cd ../sim
+
+# Run actual simulation
+
+# Cadence Verilog-XL
+if [ $SIMTOOL == xl ]; then
+
+ # RTL simulation
+ if [ "$1" == rtl ]; then
+ verilog $PARAM $INCDIR $BENCH_FILES $RTL_FILES
+
+ # Gate-level simulation
+ elif [ "$1" == gate ]; then
+ verilog $PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
+
+ # Wrong parameter or no parameter
+ else
+ echo "Usage: $0 [rtl|gate]"
+ exit 0
+ fi
+
+# Cadence Ncverilog
+elif [ $SIMTOOL == ncver ]; then
+
+ # RTL simulation
+ if [ "$1" == rtl ]; then
+ ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $RTL_FILES
+ cp ncverilog.log ../log
+
+ # Gate-level simulation
+ elif [ "$1" == gate ]; then
+ ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
+ cp ncverilog.log ../log
+
+ # Wrong parameter or no parameter
+ else
+ echo "Usage: $0 [rtl|gate]"
+ exit 0
+ fi
+
+# Cadence Ncsim
+elif [ $SIMTOOL == ncsim ]; then
+
+ # RTL simulation
+ if [ "$1" == rtl ]; then
+ ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $RTL_FILES
+ ./RUN_NC
+
+ # Gate-level simulation
+ elif [ "$1" == gate ]; then
+ ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
+ ./RUN_NC
+
+ # Wrong parameter or no parameter
+ else
+ echo "Usage: $0 [rtl|gate]"
+ exit 0
+ fi
+
+# Unsupported simulation tool
+else
+ echo "$SIMTOOL is unsupported simulation tool."
+ exit 0;
+fi
tags/rel_6/sim/rtl_sim/bin/sim.sh
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## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_6/syn/run/dodesign
===================================================================
--- tags/rel_6/syn/run/dodesign (nonexistent)
+++ tags/rel_6/syn/run/dodesign (revision 38)
@@ -0,0 +1,5 @@
+#!/bin/sh -f
+
+# nohup dc_shell -f ../bin/top.scr | tee ../log/top.log
+dc_shell -f ../bin/top_gpio.scr > ../log/top_gpio.log
+mv command.log ../log
tags/rel_6/syn/run/dodesign
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## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_6/syn/bin/cons_vs_umc18.inc
===================================================================
--- tags/rel_6/syn/bin/cons_vs_umc18.inc (nonexistent)
+++ tags/rel_6/syn/bin/cons_vs_umc18.inc (revision 38)
@@ -0,0 +1,51 @@
+/* Constraints */
+CLK_UNCERTAINTY = 0.1 /* 100 ps */
+DFFPQ2_CKQ = 0.2 /* Clk to Q in technology time units */
+DFFPQ2_SETUP = 0.1 /* Setup time in technology time units */
+
+/* Clocks constraints */
+create_clock CLK -period CLK_PERIOD
+create_clock ECLK -period CLK_PERIOD
+set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY
+set_dont_touch_network all_clocks()
+
+/* Reset constraints */
+set_driving_cell -none RST
+set_drive 0 RST
+set_dont_touch_network RST
+
+/* All inputs except reset and clock */
+all_inputs_wo_rst_clk = all_inputs() - CLK - RST
+
+/* Set output delays and load for output signals
+ *
+ * All outputs are assumed to go directly into
+ * external flip-flops for the purpose of this
+ * synthesis
+ */
+set_output_delay DFFPQ2_SETUP -clock CLK all_outputs()
+set_load load_of(umcl18u250t2_typ/DFFPQ2/D) * 4 all_outputs()
+
+/* Input delay and driving cell of all inputs
+ *
+ * All these signals are assumed to come directly from
+ * flip-flops for the purpose of this synthesis
+ *
+ */
+set_input_delay DFFPQ2_CKQ -clock CLK all_inputs_wo_rst_clk
+set_driving_cell -cell DFFPQ2 -pin Q all_inputs_wo_rst_clk
+
+/* Set design fanout */
+/*
+set_max_fanout 10 TOPLEVEL
+*/
+
+/* Set area constraint */
+set_max_area MAX_AREA
+
+/* Optimize all near-critical paths to give extra slack for layout */
+c_range = CLK_PERIOD * 0.1
+group_path -critical_range c_range -name CLK -to CLK
+
+/* Operating conditions */
+set_operating_conditions TYPICAL
Index: tags/rel_6/syn/bin/save_design.inc
===================================================================
--- tags/rel_6/syn/bin/save_design.inc (nonexistent)
+++ tags/rel_6/syn/bin/save_design.inc (revision 38)
@@ -0,0 +1,5 @@
+/* Save current design using synopsys format */
+write -hierarchy -format db -output GATE_PATH + STAGE + _ + TOPLEVEL + .db
+
+/* Save current design using verilog format */
+write -hierarchy -format verilog -output GATE_PATH + STAGE + _ + TOPLEVEL + .v
Index: tags/rel_6/syn/bin/tech_vs_umc18.inc
===================================================================
--- tags/rel_6/syn/bin/tech_vs_umc18.inc (nonexistent)
+++ tags/rel_6/syn/bin/tech_vs_umc18.inc (revision 38)
@@ -0,0 +1,16 @@
+/* Set Virtual Silicon UMC 0.18u standard cell library */
+
+search_path = {. /libs/Virtual_silicon/UMCL18U250D2_2.1/design_compiler/ }
+snps = get_unix_variable("SYNOPSYS")
+synthetic_library = { \
+ snps + "/libraries/syn/dw01.sldb" \
+ snps + "/libraries/syn/dw02.sldb" \
+ snps + "/libraries/syn/dw03.sldb" \
+ snps + "/libraries/syn/dw04.sldb" \
+ snps + "/libraries/syn/dw05.sldb" \
+ snps + "/libraries/syn/dw06.sldb" \
+ snps + "/libraries/syn/dw07.sldb" }
+target_library = { umcl18u250t2_typ.db }
+link_library = target_library + synthetic_library
+symbol_library = { umcl18u250t2.sdb }
+
Index: tags/rel_6/syn/bin/reports.inc
===================================================================
--- tags/rel_6/syn/bin/reports.inc (nonexistent)
+++ tags/rel_6/syn/bin/reports.inc (revision 38)
@@ -0,0 +1,10 @@
+/* Basic reports */
+report_area > LOG_PATH + STAGE + _ + TOPLEVEL + _area.log
+report_timing -nworst 10 > LOG_PATH + STAGE + _ + TOPLEVEL + _timing.log
+report_hierarchy > LOG_PATH + STAGE + _ + TOPLEVEL + _hierarchy.log
+report_resources > LOG_PATH + STAGE + _ + TOPLEVEL + _resources.log
+report_constraint > LOG_PATH + STAGE + _ + TOPLEVEL + _constraint.log
+/*
+report_power > LOG_PATH + STAGE + _ + TOPLEVEL + _power.log
+*/
+
Index: tags/rel_6/syn/bin/top_gpio.scr
===================================================================
--- tags/rel_6/syn/bin/top_gpio.scr (nonexistent)
+++ tags/rel_6/syn/bin/top_gpio.scr (revision 38)
@@ -0,0 +1,65 @@
+/*
+ * User defines for synthesizing GPIO IP core
+ *
+ */
+TOPLEVEL = gpio
+include select_tech.inc
+CLK = clk_i
+ECLK = gpio_eclk
+RST = rst_i
+CLK_PERIOD = 5 /* 200 MHz */
+MAX_AREA = 0 /* Push hard */
+DO_UNGROUP = yes /* yes, no */
+DO_VERIFY = yes /* yes, no */
+
+/* Starting timestamp */
+sh date
+
+/* Set some basic variables related to environment */
+include set_env.inc
+STAGE = final
+
+/* Load libraries */
+include tech_ + TECH + .inc
+
+/* Load HDL source files */
+include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log
+
+/* Set design top */
+current_design TOPLEVEL
+
+/* Link all blocks and uniquify them */
+link
+uniquify
+check_design > LOG_PATH + check_design_ + TOPLEVEL + .log
+
+/* Apply constraints */
+if (TECH == "vs_umc18") {
+ include cons_vs_umc18.inc
+} else if (TECH == "art_umc18") {
+ include cons_art_umc18.inc
+} else {
+ echo "Error: Unsupported technology"
+ exit
+}
+
+/* Lets do basic synthesis */
+if (DO_UNGROUP == "yes") {
+ ungroup -all
+}
+compile -boundary_optimization -map_effort low
+
+/* Dump gate-level from incremental synthesis */
+include save_design.inc
+
+/* Generate reports for incremental synthesis */
+include reports.inc
+
+/* Verify design */
+if (DO_VERIFY == "yes") {
+ compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log
+}
+
+/* Finish */
+sh date
+exit
Index: tags/rel_6/syn/bin/select_tech.inc
===================================================================
--- tags/rel_6/syn/bin/select_tech.inc (nonexistent)
+++ tags/rel_6/syn/bin/select_tech.inc (revision 38)
@@ -0,0 +1,5 @@
+/* Defaults */
+
+TECH = vs_umc18 /* vs_umc18, art_umc18 */
+CLK_PERIOD = 5 /* 200 MHz */
+MAX_AREA = 0 /* Push hard */
Index: tags/rel_6/syn/bin/set_env.inc
===================================================================
--- tags/rel_6/syn/bin/set_env.inc (nonexistent)
+++ tags/rel_6/syn/bin/set_env.inc (revision 38)
@@ -0,0 +1,18 @@
+/* Enable Verilog HDL preprocessor */
+hdlin_enable_vpp = true
+
+/* Set log path */
+LOG_PATH = "../log/"
+
+/* Set gate-level netlist path */
+GATE_PATH = "../out/"
+
+/* Set RAMS_PATH */
+RAMS_PATH = "../../../lib/"
+
+/* Set RTL source path */
+RTL_PATH = "../../rtl/verilog/"
+
+/* Optimize adders */
+synlib_model_map_effort = high
+hlo_share_effort = medium
Index: tags/rel_6/syn/bin/read_design.inc
===================================================================
--- tags/rel_6/syn/bin/read_design.inc (nonexistent)
+++ tags/rel_6/syn/bin/read_design.inc (revision 38)
@@ -0,0 +1,11 @@
+/* Set search path for verilog include files */
+search_path = search_path + { RTL_PATH } + { GATE_PATH }
+
+/* Read verilog files of the GPIO IP core */
+if (TOPLEVEL == "gpio") {
+ read -f verilog gpio.v
+} else {
+ echo "Non-existing top level."
+ exit
+}
+
Index: tags/rel_6/syn/bin/cons_art_umc18.inc
===================================================================
--- tags/rel_6/syn/bin/cons_art_umc18.inc (nonexistent)
+++ tags/rel_6/syn/bin/cons_art_umc18.inc (revision 38)
@@ -0,0 +1,51 @@
+/* Constraints */
+CLK_UNCERTAINTY = 0.1 /* 100 ps */
+DFFHQX2_CKQ = 0.2 /* Clk to Q in technology time units */
+DFFHQX2_SETUP = 0.1 /* Setup time in technology time units */
+
+/* Clocks constraints */
+create_clock CLK -period CLK_PERIOD
+create_clock ECLK -period CLK_PERIOD
+set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY
+set_dont_touch_network all_clocks()
+
+/* Reset constraints */
+set_driving_cell -none RST
+set_drive 0 RST
+set_dont_touch_network RST
+
+/* All inputs except reset and clock */
+all_inputs_wo_rst_clk = all_inputs() - CLK - RST
+
+/* Set output delays and load for output signals
+ *
+ * All outputs are assumed to go directly into
+ * external flip-flops for the purpose of this
+ * synthesis
+ */
+set_output_delay DFFHQX2_SETUP -clock CLK all_outputs()
+set_load load_of(typical/DFFHQX2/D) * 1 all_outputs()
+
+/* Input delay and driving cell of all inputs
+ *
+ * All these signals are assumed to come directly from
+ * flip-flops for the purpose of this synthesis
+ *
+ */
+set_input_delay DFFHQX2_CKQ -clock CLK all_inputs_wo_rst_clk
+set_driving_cell -cell DFFHQX2 -pin Q all_inputs_wo_rst_clk
+
+/* Set design fanout */
+/*
+set_max_fanout 10 TOPLEVEL
+*/
+
+/* Set area constraint */
+set_max_area MAX_AREA
+
+/* Optimize all near-critical paths to give extra slack for layout */
+c_range = CLK_PERIOD * 0.05
+group_path -critical_range c_range -name CLK -to CLK
+
+/* Operating conditions */
+set_operating_conditions typical
Index: tags/rel_6/syn/bin/tech_art_umc18.inc
===================================================================
--- tags/rel_6/syn/bin/tech_art_umc18.inc (nonexistent)
+++ tags/rel_6/syn/bin/tech_art_umc18.inc (revision 38)
@@ -0,0 +1,17 @@
+/* Set Artisan Sage-X UMC 0.18u standard cell library */
+
+search_path = {. /libs/Artisan/aci/sc-x/synopsys/ } + \
+ { /libs/Artisan/aci/sc-x/symbols/synopsys/ }
+snps = get_unix_variable("SYNOPSYS")
+synthetic_library = { \
+ snps + "/libraries/syn/dw01.sldb" \
+ snps + "/libraries/syn/dw02.sldb" \
+ snps + "/libraries/syn/dw03.sldb" \
+ snps + "/libraries/syn/dw04.sldb" \
+ snps + "/libraries/syn/dw05.sldb" \
+ snps + "/libraries/syn/dw06.sldb" \
+ snps + "/libraries/syn/dw07.sldb" }
+target_library = { typical.db }
+link_library = target_library + synthetic_library
+symbol_library = { umc18.sdb }
+