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/trunk/rtl/verilog/gpio_defines.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2003/12/17 13:00:52 gorand
// added ECLK and NEC registers, all tests passed.
//
// Revision 1.7 2003/12/01 17:10:44 simons
// ifndef directive is not supported by all tools.
//
138,9 → 141,27
`define GPIO_REGISTERED_IO_OUTPUTS
 
//
// Implement aux feature. If this define is not defined also aux_i port and
// RGPIO_AUX register will be removed
//
// Defined by default.
//
`define GPIO_AUX_IMPLEMENT
 
//
// If this is not defined clk_pad_i will be removed. Input lines will be lached on
// positive edge of system clock
// if disabled defines GPIO_NO_NEGEDGE_FLOPS, GPIO_NO_CLKPAD_LOGIC will have no effect.
//
// Defined by default.
//
`define GPIO_CLKPAD
 
//
// Define to avoid using negative edge clock flip-flops for external clock
// (caused by NEC register. Instead an inverted external clock with
// positive edge clock flip-flops will be used.
// This define don't have any effect if GPIO_CLKPAD is not defined and if GPIO_SYNC_IN_CLK is defined
//
// By default it is not defined.
//
150,11 → 171,42
// If GPIO_NO_NEGEDGE_FLOPS is defined, a mux needs to be placed on external clock
// clk_pad_i to implement RGPIO_CTRL[NEC] functionality. If no mux is allowed on
// clock signal, enable the following define.
// This define don't have any effect if GPIO_CLKPAD is not defined and if GPIO_SYNC_IN_CLK is defined
//
// By default it is not defined.
//
//`define GPIO_NO_CLKPAD_LOGIC
 
 
//
// synchronization defines
//
// Two synchronization flops to input lineis added.
// system clock synchronization.
//
`define GPIO_SYNC_IN_WB
 
//
// Add synchronization flops to external clock input line. Gpio will have just one clock domain,
// everithing will be synchronized to wishbone clock. External clock muas be at least 2-3x slower
// as systam clock.
//
`define GPIO_SYNC_CLK_WB
 
//
// Add synchronization to input pads. synchronization to external clock.
// Don't hawe any effect if GPIO_SYNC_CLK_WB is defined.
//
//`define GPIO_SYNC_IN_CLK
 
//
// Add synchronization flops between system clock and external clock.
// Only possible if external clock is enabled and clock synchroization is disabled.
//
//`define GPIO_SYNC_IN_CLK_WB
 
 
 
//
// Undefine if you don't need to read GPIO registers except for RGPIO_IN register.
// When it is undefined all reads of GPIO registers return RGPIO_IN register. This
198,6 → 250,10
// if the number of I/O lines is in range 25-32, GPIO_WB_BYTES4 is defined,
 
`define GPIO_WB_BYTES4
//`define GPIO_WB_BYTES3
//`define GPIO_WB_BYTES2
//`define GPIO_WB_BYTES1
 
`endif
 
//
231,11 → 287,18
`define GPIO_RGPIO_OE 4'h2 // Address 0x08
`define GPIO_RGPIO_INTE 4'h3 // Address 0x0c
`define GPIO_RGPIO_PTRIG 4'h4 // Address 0x10
 
`ifdef GPIO_AUX_IMPLEMENT
`define GPIO_RGPIO_AUX 4'h5 // Address 0x14
`endif // GPIO_AUX_IMPLEMENT
 
`define GPIO_RGPIO_CTRL 4'h6 // Address 0x18
`define GPIO_RGPIO_INTS 4'h7 // Address 0x1c
 
`ifdef GPIO_CLKPAD
`define GPIO_RGPIO_ECLK 4'h8 // Address 0x20
`define GPIO_RGPIO_NEC 4'h9 // Address 0x24
`endif // GPIO_CLKPAD
 
//
// Default values for unimplemented GPIO registers
260,97 → 323,4
`define GPIO_RGPIO_CTRL_INTE 0
`define GPIO_RGPIO_CTRL_INTS 1
 
`ifdef GPIO_LINES32
`define GPIO_LINES31
`endif
`ifdef GPIO_LINES31
`define GPIO_LINES30
`endif
`ifdef GPIO_LINES30
`define GPIO_LINES29
`endif
`ifdef GPIO_LINES29
`define GPIO_LINES28
`endif
`ifdef GPIO_LINES28
`define GPIO_LINES27
`endif
`ifdef GPIO_LINES27
`define GPIO_LINES26
`endif
`ifdef GPIO_LINES26
`define GPIO_LINES25
`endif
`ifdef GPIO_LINES25
`define GPIO_LINES24
`endif
`ifdef GPIO_LINES24
`define GPIO_LINES23
`endif
`ifdef GPIO_LINES23
`define GPIO_LINES22
`endif
`ifdef GPIO_LINES22
`define GPIO_LINES21
`endif
`ifdef GPIO_LINES21
`define GPIO_LINES20
`endif
`ifdef GPIO_LINES20
`define GPIO_LINES19
`endif
`ifdef GPIO_LINES19
`define GPIO_LINES18
`endif
`ifdef GPIO_LINES18
`define GPIO_LINES17
`endif
`ifdef GPIO_LINES17
`define GPIO_LINES16
`endif
`ifdef GPIO_LINES16
`define GPIO_LINES15
`endif
`ifdef GPIO_LINES15
`define GPIO_LINES14
`endif
`ifdef GPIO_LINES14
`define GPIO_LINES13
`endif
`ifdef GPIO_LINES13
`define GPIO_LINES12
`endif
`ifdef GPIO_LINES12
`define GPIO_LINES11
`endif
`ifdef GPIO_LINES11
`define GPIO_LINES10
`endif
`ifdef GPIO_LINES10
`define GPIO_LINES9
`endif
`ifdef GPIO_LINES9
`define GPIO_LINES8
`endif
`ifdef GPIO_LINES8
`define GPIO_LINES7
`endif
`ifdef GPIO_LINES7
`define GPIO_LINES6
`endif
`ifdef GPIO_LINES6
`define GPIO_LINES5
`endif
`ifdef GPIO_LINES5
`define GPIO_LINES4
`endif
`ifdef GPIO_LINES4
`define GPIO_LINES3
`endif
`ifdef GPIO_LINES3
`define GPIO_LINES2
`endif
`ifdef GPIO_LINES2
`define GPIO_LINES1
`endif
 
/trunk/rtl/verilog/gpio_top.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.17 2004/05/05 08:21:00 andreje
// Bugfixes when GPIO_RGPIO_ECLK/GPIO_RGPIO_NEC disabled, gpio oe name change and set to active-high according to spec
//
// Revision 1.16 2003/12/17 13:00:52 gorand
// added ECLK and NEC registers, all tests passed.
//
114,11 → 117,16
wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,
wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,
 
`ifdef GPIO_AUX_IMPLEMENT
// Auxiliary inputs interface
aux_i,
`endif // GPIO_AUX_IMPLEMENT
 
// External GPIO Interface
ext_pad_i, clk_pad_i, ext_pad_o, ext_padoe_o
ext_pad_i, ext_pad_o, ext_padoe_o
`ifdef GPIO_CLKPAD
, clk_pad_i
`endif
);
 
parameter dw = 32;
127,29 → 135,33
//
// WISHBONE Interface
//
input wb_clk_i; // Clock
input wb_rst_i; // Reset
input wb_cyc_i; // cycle valid input
input [aw-1:0] wb_adr_i; // address bus inputs
input [dw-1:0] wb_dat_i; // input data bus
input [3:0] wb_sel_i; // byte select inputs
input wb_we_i; // indicates write transfer
input wb_stb_i; // strobe input
output [dw-1:0] wb_dat_o; // output data bus
output wb_ack_o; // normal termination
output wb_err_o; // termination w/ error
output wb_inta_o; // Interrupt request output
input wb_clk_i; // Clock
input wb_rst_i; // Reset
input wb_cyc_i; // cycle valid input
input [aw-1:0] wb_adr_i; // address bus inputs
input [dw-1:0] wb_dat_i; // input data bus
input [3:0] wb_sel_i; // byte select inputs
input wb_we_i; // indicates write transfer
input wb_stb_i; // strobe input
output [dw-1:0] wb_dat_o; // output data bus
output wb_ack_o; // normal termination
output wb_err_o; // termination w/ error
output wb_inta_o; // Interrupt request output
 
`ifdef GPIO_AUX_IMPLEMENT
// Auxiliary Inputs Interface
input [gw-1:0] aux_i; // Auxiliary inputs
input [gw-1:0] aux_i; // Auxiliary inputs
`endif // GPIO_AUX_IMPLEMENT
 
//
// External GPIO Interface
//
input [gw-1:0] ext_pad_i; // GPIO Inputs
input clk_pad_i; // GPIO Eclk
output [gw-1:0] ext_pad_o; // GPIO Outputs
output [gw-1:0] ext_padoe_o; // GPIO output drivers enables
input [gw-1:0] ext_pad_i; // GPIO Inputs
`ifdef GPIO_CLKPAD
input clk_pad_i; // GPIO Eclk
`endif // GPIO_CLKPAD
output [gw-1:0] ext_pad_o; // GPIO Outputs
output [gw-1:0] ext_padoe_o; // GPIO output drivers enables
 
`ifdef GPIO_IMPLEMENTED
 
243,41 → 255,60
wire [gw-1:0] rgpio_nec; // No register
`endif
 
 
//
// Synchronization flops for input signals
//
`ifdef GPIO_SYNC_IN_WB
reg [gw-1:0] sync ,
ext_pad_s ;
`else
wire [gw-1:0] ext_pad_s ;
`endif
 
 
 
//
// Internal wires & regs
//
wire rgpio_out_sel; // RGPIO_OUT select
wire rgpio_oe_sel; // RGPIO_OE select
wire rgpio_inte_sel; // RGPIO_INTE select
wire rgpio_ptrig_sel;// RGPIO_PTRIG select
wire rgpio_aux_sel; // RGPIO_AUX select
wire rgpio_ctrl_sel; // RGPIO_CTRL select
wire rgpio_ints_sel; // RGPIO_INTS select
wire rgpio_eclk_sel ;
wire rgpio_nec_sel ;
wire full_decoding; // Full address decoding qualification
wire rgpio_out_sel; // RGPIO_OUT select
wire rgpio_oe_sel; // RGPIO_OE select
wire rgpio_inte_sel; // RGPIO_INTE select
wire rgpio_ptrig_sel;// RGPIO_PTRIG select
wire rgpio_aux_sel; // RGPIO_AUX select
wire rgpio_ctrl_sel; // RGPIO_CTRL select
wire rgpio_ints_sel; // RGPIO_INTS select
wire rgpio_eclk_sel ;
wire rgpio_nec_sel ;
wire full_decoding; // Full address decoding qualification
wire [gw-1:0] in_muxed; // Muxed inputs
wire wb_ack; // WB Acknowledge
wire wb_err; // WB Error
wire wb_inta; // WB Interrupt
reg [dw-1:0] wb_dat; // WB Data out
wire wb_ack; // WB Acknowledge
wire wb_err; // WB Error
wire wb_inta; // WB Interrupt
reg [dw-1:0] wb_dat; // WB Data out
`ifdef GPIO_REGISTERED_WB_OUTPUTS
reg wb_ack_o; // WB Acknowledge
reg wb_err_o; // WB Error
reg wb_inta_o; // WB Interrupt
reg [dw-1:0] wb_dat_o; // WB Data out
reg wb_ack_o; // WB Acknowledge
reg wb_err_o; // WB Error
reg wb_inta_o; // WB Interrupt
reg [dw-1:0] wb_dat_o; // WB Data out
`endif
wire [gw-1:0] out_pad; // GPIO Outputs
`ifdef GPIO_REGISTERED_IO_OUTPUTS
reg [gw-1:0] ext_pad_o; // GPIO Outputs
reg [gw-1:0] ext_pad_o; // GPIO Outputs
`endif
`ifdef GPIO_CLKPAD
wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock
wire [gw-1:0] pext_clk; // External clock for posedge flops
reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs
reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs
`ifdef GPIO_NO_NEGEDGE_FLOPS
`ifdef GPIO_NO_CLKPAD_LOGIC
`else
reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs
reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs
`endif // GPIO_NO_CLKPAD_LOGIC
`else
reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs
`endif
`endif // GPIO_CLKPAD
 
 
//
727,8 → 758,23
assign rgpio_nec = `GPIO_DEF_RGPIO_NEC; // RGPIO_NEC = 0x0
`endif
 
 
//
// synchronize inputs to systam clock
//
`ifdef GPIO_SYNC_IN_WB
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i) begin
sync <= #1 {gw{1'b0}} ;
ext_pad_s <= #1 {gw{1'b0}} ;
end else begin
sync <= #1 ext_pad_i ;
ext_pad_s <= #1 sync ;
end
`else
assign ext_pad_s = ext_pad_i;
`endif // GPIO_SYNC_IN_WB
//
// Latch into RGPIO_IN
//
`ifdef GPIO_RGPIO_IN
741,699 → 787,199
assign rgpio_in = in_muxed;
`endif
 
//
// Mux inputs directly from input pads with inputs sampled by external clock
//
//assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : ext_pad_i;
`ifdef GPIO_CLKPAD
 
 
`ifdef GPIO_LINES32
assign in_muxed [31] = rgpio_eclk [31] ? extc_in[31] : ext_pad_i[31] ;
`endif
 
`ifdef GPIO_LINES31
assign in_muxed [30] = rgpio_eclk [30] ? extc_in[30] : ext_pad_i[30] ;
`endif
 
`ifdef GPIO_LINES30
assign in_muxed [29] = rgpio_eclk [29] ? extc_in[29] : ext_pad_i[29] ;
`endif
 
`ifdef GPIO_LINES29
assign in_muxed [28] = rgpio_eclk [28] ? extc_in[28] : ext_pad_i[28] ;
`endif
 
`ifdef GPIO_LINES28
assign in_muxed [27] = rgpio_eclk [27] ? extc_in[27] : ext_pad_i[27] ;
`endif
 
`ifdef GPIO_LINES27
assign in_muxed [26] = rgpio_eclk [26] ? extc_in[26] : ext_pad_i[26] ;
`endif
 
`ifdef GPIO_LINES26
assign in_muxed [25] = rgpio_eclk [25] ? extc_in[25] : ext_pad_i[25] ;
`endif
 
`ifdef GPIO_LINES25
assign in_muxed [24] = rgpio_eclk [24] ? extc_in[24] : ext_pad_i[24] ;
`endif
 
`ifdef GPIO_LINES24
assign in_muxed [23] = rgpio_eclk [23] ? extc_in[23] : ext_pad_i[23] ;
`endif
 
`ifdef GPIO_LINES23
assign in_muxed [22] = rgpio_eclk [22] ? extc_in[22] : ext_pad_i[22] ;
`endif
 
`ifdef GPIO_LINES22
assign in_muxed [21] = rgpio_eclk [21] ? extc_in[21] : ext_pad_i[21] ;
`endif
 
`ifdef GPIO_LINES21
assign in_muxed [20] = rgpio_eclk [20] ? extc_in[20] : ext_pad_i[20] ;
`endif
 
`ifdef GPIO_LINES20
assign in_muxed [19] = rgpio_eclk [19] ? extc_in[19] : ext_pad_i[19] ;
`endif
 
`ifdef GPIO_LINES19
assign in_muxed [18] = rgpio_eclk [18] ? extc_in[18] : ext_pad_i[18] ;
`endif
 
`ifdef GPIO_LINES18
assign in_muxed [17] = rgpio_eclk [17] ? extc_in[17] : ext_pad_i[17] ;
`endif
 
`ifdef GPIO_LINES17
assign in_muxed [16] = rgpio_eclk [16] ? extc_in[16] : ext_pad_i[16] ;
`endif
 
`ifdef GPIO_LINES16
assign in_muxed [15] = rgpio_eclk [15] ? extc_in[15] : ext_pad_i[15] ;
`endif
 
`ifdef GPIO_LINES15
assign in_muxed [14] = rgpio_eclk [14] ? extc_in[14] : ext_pad_i[14] ;
`endif
 
`ifdef GPIO_LINES14
assign in_muxed [13] = rgpio_eclk [13] ? extc_in[13] : ext_pad_i[13] ;
`endif
 
`ifdef GPIO_LINES13
assign in_muxed [12] = rgpio_eclk [12] ? extc_in[12] : ext_pad_i[12] ;
`endif
 
`ifdef GPIO_LINES12
assign in_muxed [11] = rgpio_eclk [11] ? extc_in[11] : ext_pad_i[11] ;
`endif
 
`ifdef GPIO_LINES11
assign in_muxed [10] = rgpio_eclk [10] ? extc_in[10] : ext_pad_i[10] ;
`endif
 
`ifdef GPIO_LINES10
assign in_muxed [9] = rgpio_eclk [9] ? extc_in[9] : ext_pad_i[9] ;
`endif
 
`ifdef GPIO_LINES9
assign in_muxed [8] = rgpio_eclk [8] ? extc_in[8] : ext_pad_i[8] ;
`endif
 
`ifdef GPIO_LINES8
assign in_muxed [7] = rgpio_eclk [7] ? extc_in[7] : ext_pad_i[7] ;
`endif
 
`ifdef GPIO_LINES7
assign in_muxed [6] = rgpio_eclk [6] ? extc_in[6] : ext_pad_i[6] ;
`endif
 
`ifdef GPIO_LINES6
assign in_muxed [5] = rgpio_eclk [5] ? extc_in[5] : ext_pad_i[5] ;
`endif
 
`ifdef GPIO_LINES5
assign in_muxed [4] = rgpio_eclk [4] ? extc_in[4] : ext_pad_i[4] ;
`endif
 
`ifdef GPIO_LINES4
assign in_muxed [3] = rgpio_eclk [3] ? extc_in[3] : ext_pad_i[3] ;
`endif
 
`ifdef GPIO_LINES3
assign in_muxed [2] = rgpio_eclk [2] ? extc_in[2] : ext_pad_i[2] ;
`endif
 
`ifdef GPIO_LINES2
assign in_muxed [1] = rgpio_eclk [1] ? extc_in[1] : ext_pad_i[1] ;
`endif
 
`ifdef GPIO_LINES1
assign in_muxed [0] = rgpio_eclk [0] ? extc_in[0] : ext_pad_i[0] ;
`endif
 
 
`ifdef GPIO_SYNC_CLK_WB
//
// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.
// If negedge flops are allowed, pext_clk only clocks posedge flops.
// external clock enabled
// synchronized to system clock
// (one clock domain)
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
`ifdef GPIO_NO_CLKPAD_LOGIC
assign pext_clk = {gw{clk_pad_i}};
`else
 
//assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~clk_pad_i : clk_pad_i;
reg sync_clk,
clk_s ,
clk_r ;
wire pedge ,
nedge ;
wire [gw-1:0] pedge_vec ,
nedge_vec ;
wire [gw-1:0] in_lach ;
 
assign pedge = clk_s & !clk_r ;
assign nedge = !clk_s & clk_r ;
assign pedge_vec = {gw{pedge}} ;
assign nedge_vec = {gw{nedge}} ;
 
`ifdef GPIO_LINES32
assign pext_clk [31] = rgpio_nec [31] ? ~clk_pad_i : clk_pad_i ;
`endif
assign in_lach = (~rgpio_nec & pedge_vec) | (rgpio_nec & nedge_vec) ;
assign extc_in = (in_lach & ext_pad_s) | (~in_lach & pextc_sampled) ;
 
`ifdef GPIO_LINES31
assign pext_clk [30] = rgpio_nec [30] ? ~clk_pad_i : clk_pad_i ;
`endif
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i) begin
sync_clk <= #1 1'b0 ;
clk_s <= #1 1'b0 ;
clk_r <= #1 1'b0 ;
end else begin
sync_clk <= #1 clk_pad_i ;
clk_s <= #1 sync_clk ;
clk_r <= #1 clk_s ;
end
 
`ifdef GPIO_LINES30
assign pext_clk [29] = rgpio_nec [29] ? ~clk_pad_i : clk_pad_i ;
`endif
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i) begin
pextc_sampled <= #1 {gw{1'b0}};
end else begin
pextc_sampled <= #1 extc_in ;
end
 
`ifdef GPIO_LINES29
assign pext_clk [28] = rgpio_nec [28] ? ~clk_pad_i : clk_pad_i ;
`endif
assign in_muxed = (rgpio_eclk & pextc_sampled) | (~rgpio_eclk & ext_pad_s) ;
 
`ifdef GPIO_LINES28
assign pext_clk [27] = rgpio_nec [27] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES27
assign pext_clk [26] = rgpio_nec [26] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES26
assign pext_clk [25] = rgpio_nec [25] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES25
assign pext_clk [24] = rgpio_nec [24] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES24
assign pext_clk [23] = rgpio_nec [23] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES23
assign pext_clk [22] = rgpio_nec [22] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES22
assign pext_clk [21] = rgpio_nec [21] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES21
assign pext_clk [20] = rgpio_nec [20] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES20
assign pext_clk [19] = rgpio_nec [19] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES19
assign pext_clk [18] = rgpio_nec [18] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES18
assign pext_clk [17] = rgpio_nec [17] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES17
assign pext_clk [16] = rgpio_nec [16] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES16
assign pext_clk [15] = rgpio_nec [15] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES15
assign pext_clk [14] = rgpio_nec [14] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES14
assign pext_clk [13] = rgpio_nec [13] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES13
assign pext_clk [12] = rgpio_nec [12] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES12
assign pext_clk [11] = rgpio_nec [11] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES11
assign pext_clk [10] = rgpio_nec [10] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES10
assign pext_clk [9] = rgpio_nec [9] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES9
assign pext_clk [8] = rgpio_nec [8] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES8
assign pext_clk [7] = rgpio_nec [7] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES7
assign pext_clk [6] = rgpio_nec [6] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES6
assign pext_clk [5] = rgpio_nec [5] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES5
assign pext_clk [4] = rgpio_nec [4] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES4
assign pext_clk [3] = rgpio_nec [3] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES3
assign pext_clk [2] = rgpio_nec [2] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES2
assign pext_clk [1] = rgpio_nec [1] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`ifdef GPIO_LINES1
assign pext_clk [0] = rgpio_nec [0] ? ~clk_pad_i : clk_pad_i ;
`endif
 
`endif
`else
assign pext_clk = {gw{clk_pad_i}};
`endif
 
 
//
// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.
// external clock enabled
// not synchronized to system clock
// (two clock domains)
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
assign extc_in = pextc_sampled;
`else
//assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;
 
`ifdef GPIO_SYNC_IN_CLK_WB
 
`ifdef GPIO_LINES32
assign extc_in [31] = rgpio_nec [31] ? nextc_sampled[31] : pextc_sampled[31] ;
`endif
reg [gw-1:0] syn_extc ,
extc_s ;
 
`ifdef GPIO_LINES31
assign extc_in [30] = rgpio_nec [30] ? nextc_sampled[30] : pextc_sampled[30] ;
`endif
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i) begin
syn_extc <= #1 {gw{1'b0}};
extc_s <= #1 {gw{1'b0}};
end else begin
syn_extc <= #1 extc_in ;
extc_s <= #1 syn_extc;
end
 
`ifdef GPIO_LINES30
assign extc_in [29] = rgpio_nec [29] ? nextc_sampled[29] : pextc_sampled[29] ;
`endif
`else
 
`ifdef GPIO_LINES29
assign extc_in [28] = rgpio_nec [28] ? nextc_sampled[28] : pextc_sampled[28] ;
`endif
wire [gw-1:0] extc_s ;
assign extc_s = syn_extc ;
 
`ifdef GPIO_LINES28
assign extc_in [27] = rgpio_nec [27] ? nextc_sampled[27] : pextc_sampled[27] ;
`endif
`endif // GPIO_SYNC_IN_CLK_WB
 
`ifdef GPIO_LINES27
assign extc_in [26] = rgpio_nec [26] ? nextc_sampled[26] : pextc_sampled[26] ;
`endif
`ifdef GPIO_SYNC_IN_CLK
reg [gw-1:0] syn_pclk ,
ext_pad_spc ;
 
`ifdef GPIO_LINES26
assign extc_in [25] = rgpio_nec [25] ? nextc_sampled[25] : pextc_sampled[25] ;
`endif
always @(posedge clk_pad_i or posedge wb_rst_i)
if (wb_rst_i) begin
syn_pclk <= #1 {gw{1'b0}} ;
ext_pad_spc <= #1 {gw{1'b0}} ;
end else begin
syn_pclk <= #1 ext_pad_i ;
ext_pad_spc <= #1 syn_pclk ;
end
 
`ifdef GPIO_LINES25
assign extc_in [24] = rgpio_nec [24] ? nextc_sampled[24] : pextc_sampled[24] ;
`endif
`else
 
`ifdef GPIO_LINES24
assign extc_in [23] = rgpio_nec [23] ? nextc_sampled[23] : pextc_sampled[23] ;
`endif
wire [gw-1:0] ext_pad_spc ;
assign ext_pad_spc = ext_pad_i ;
 
`ifdef GPIO_LINES23
assign extc_in [22] = rgpio_nec [22] ? nextc_sampled[22] : pextc_sampled[22] ;
`endif
`endif // GPIO_SYNC_IN_CLK
 
`ifdef GPIO_LINES22
assign extc_in [21] = rgpio_nec [21] ? nextc_sampled[21] : pextc_sampled[21] ;
`endif
always @(posedge clk_pad_i or posedge wb_rst_i)
if (wb_rst_i) begin
pextc_sampled <= #1 {gw{1'b0}};
end else begin
pextc_sampled <= #1 ext_pad_spc ;
end
 
`ifdef GPIO_LINES21
assign extc_in [20] = rgpio_nec [20] ? nextc_sampled[20] : pextc_sampled[20] ;
`endif
 
`ifdef GPIO_LINES20
assign extc_in [19] = rgpio_nec [19] ? nextc_sampled[19] : pextc_sampled[19] ;
`endif
`ifdef GPIO_NO_NEGEDGE_FLOPS
 
`ifdef GPIO_LINES19
assign extc_in [18] = rgpio_nec [18] ? nextc_sampled[18] : pextc_sampled[18] ;
`endif
`ifdef GPIO_NO_CLKPAD_LOGIC
 
`ifdef GPIO_LINES18
assign extc_in [17] = rgpio_nec [17] ? nextc_sampled[17] : pextc_sampled[17] ;
`endif
assign extc_in = pextc_sampled;
 
`ifdef GPIO_LINES17
assign extc_in [16] = rgpio_nec [16] ? nextc_sampled[16] : pextc_sampled[16] ;
`endif
`else
 
`ifdef GPIO_LINES16
assign extc_in [15] = rgpio_nec [15] ? nextc_sampled[15] : pextc_sampled[15] ;
`endif
wire clk_n;
assign clk_n = !clk_pad_i;
 
`ifdef GPIO_LINES15
assign extc_in [14] = rgpio_nec [14] ? nextc_sampled[14] : pextc_sampled[14] ;
`endif
`ifdef GPIO_SYNC_IN_CLK
reg [gw-1:0] syn_nclk ,
ext_pad_snc ;
 
`ifdef GPIO_LINES14
assign extc_in [13] = rgpio_nec [13] ? nextc_sampled[13] : pextc_sampled[13] ;
`endif
always @(posedge clk_n or posedge wb_rst_i)
if (wb_rst_i) begin
syn_nclk <= #1 {gw{1'b0}} ;
ext_pad_snc <= #1 {gw{1'b0}} ;
end else begin
syn_nclk <= #1 ext_pad_i ;
ext_pad_snc <= #1 syn_nclk ;
end
 
`ifdef GPIO_LINES13
assign extc_in [12] = rgpio_nec [12] ? nextc_sampled[12] : pextc_sampled[12] ;
`endif
`else
 
`ifdef GPIO_LINES12
assign extc_in [11] = rgpio_nec [11] ? nextc_sampled[11] : pextc_sampled[11] ;
`endif
wire [gw-1:0] ext_pad_snc ;
assign ext_pad_snc = ext_pad_i ;
 
`ifdef GPIO_LINES11
assign extc_in [10] = rgpio_nec [10] ? nextc_sampled[10] : pextc_sampled[10] ;
`endif
`endif // GPIO_SYNC_IN_CLK
 
`ifdef GPIO_LINES10
assign extc_in [9] = rgpio_nec [9] ? nextc_sampled[9] : pextc_sampled[9] ;
`endif
always @(posedge clk_n or posedge wb_rst_i)
if (wb_rst_i) begin
nextc_sampled <= #1 {gw{1'b0}};
end else begin
nextc_sampled <= #1 ext_pad_snc ;
end
 
`ifdef GPIO_LINES9
assign extc_in [8] = rgpio_nec [8] ? nextc_sampled[8] : pextc_sampled[8] ;
`endif
assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ;
 
`ifdef GPIO_LINES8
assign extc_in [7] = rgpio_nec [7] ? nextc_sampled[7] : pextc_sampled[7] ;
`endif
`endif // GPIO_NO_CLKPAD_LOGIC
 
`ifdef GPIO_LINES7
assign extc_in [6] = rgpio_nec [6] ? nextc_sampled[6] : pextc_sampled[6] ;
`endif
 
`ifdef GPIO_LINES6
assign extc_in [5] = rgpio_nec [5] ? nextc_sampled[5] : pextc_sampled[5] ;
`endif
`else
 
`ifdef GPIO_LINES5
assign extc_in [4] = rgpio_nec [4] ? nextc_sampled[4] : pextc_sampled[4] ;
`endif
`ifdef GPIO_SYNC_IN_CLK
reg [gw-1:0] syn_nclk ,
ext_pad_snc ;
 
`ifdef GPIO_LINES4
assign extc_in [3] = rgpio_nec [3] ? nextc_sampled[3] : pextc_sampled[3] ;
`endif
always @(negedge clk_n or posedge wb_rst_i)
if (wb_rst_i) begin
syn_nclk <= #1 {gw{1'b0}} ;
ext_pad_snc <= #1 {gw{1'b0}} ;
end else begin
syn_nclk <= #1 ext_pad_i ;
ext_pad_snc <= #1 syn_nclk ;
end
 
`ifdef GPIO_LINES3
assign extc_in [2] = rgpio_nec [2] ? nextc_sampled[2] : pextc_sampled[2] ;
`endif
`else
 
`ifdef GPIO_LINES2
assign extc_in [1] = rgpio_nec [1] ? nextc_sampled[1] : pextc_sampled[1] ;
`endif
wire [gw-1:0] ext_pad_snc ;
assign ext_pad_snc = ext_pad_i ;
 
`ifdef GPIO_LINES1
assign extc_in [0] = rgpio_nec [0] ? nextc_sampled[0] : pextc_sampled[0] ;
`endif
`endif // GPIO_SYNC_IN_CLK
 
`endif
always @(negedge clk_pad_i or posedge wb_rst_i)
if (wb_rst_i) begin
nextc_sampled <= #1 {gw{1'b0}};
end else begin
nextc_sampled <= #1 ext_pad_snc ;
end
 
//
// Latch using posedge external clock
//
assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ;
 
`ifdef GPIO_LINES32
always @(posedge pext_clk[31] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[31] <= #1 1'b0;
else
pextc_sampled[31] <= #1 ext_pad_i[31];
`endif
`endif // GPIO_NO_NEGEDGE_FLOPS
 
`ifdef GPIO_LINES31
always @(posedge pext_clk[30] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[30] <= #1 1'b0;
else
pextc_sampled[30] <= #1 ext_pad_i[30];
`endif
assign in_muxed = (rgpio_eclk & extc_s) | (~rgpio_eclk & ext_pad_s) ;
 
`ifdef GPIO_LINES30
always @(posedge pext_clk[29] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[29] <= #1 1'b0;
else
pextc_sampled[29] <= #1 ext_pad_i[29];
`endif
 
`ifdef GPIO_LINES29
always @(posedge pext_clk[28] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[28] <= #1 1'b0;
else
pextc_sampled[28] <= #1 ext_pad_i[28];
`endif
`endif // GPIO_SYNC_CLK_WB
 
`ifdef GPIO_LINES28
always @(posedge pext_clk[27] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[27] <= #1 1'b0;
else
pextc_sampled[27] <= #1 ext_pad_i[27];
`endif
 
`ifdef GPIO_LINES27
always @(posedge pext_clk[26] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[26] <= #1 1'b0;
else
pextc_sampled[26] <= #1 ext_pad_i[26];
`endif
`else
 
`ifdef GPIO_LINES26
always @(posedge pext_clk[25] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[25] <= #1 1'b0;
else
pextc_sampled[25] <= #1 ext_pad_i[25];
`endif
assign in_muxed = ext_pad_s ;
 
`ifdef GPIO_LINES25
always @(posedge pext_clk[24] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[24] <= #1 1'b0;
else
pextc_sampled[24] <= #1 ext_pad_i[24];
`endif
`endif // GPIO_CLKPAD
 
`ifdef GPIO_LINES24
always @(posedge pext_clk[23] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[23] <= #1 1'b0;
else
pextc_sampled[23] <= #1 ext_pad_i[23];
`endif
 
`ifdef GPIO_LINES23
always @(posedge pext_clk[22] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[22] <= #1 1'b0;
else
pextc_sampled[22] <= #1 ext_pad_i[22];
`endif
 
`ifdef GPIO_LINES22
always @(posedge pext_clk[21] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[21] <= #1 1'b0;
else
pextc_sampled[21] <= #1 ext_pad_i[21];
`endif
 
`ifdef GPIO_LINES21
always @(posedge pext_clk[20] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[20] <= #1 1'b0;
else
pextc_sampled[20] <= #1 ext_pad_i[20];
`endif
 
`ifdef GPIO_LINES20
always @(posedge pext_clk[19] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[19] <= #1 1'b0;
else
pextc_sampled[19] <= #1 ext_pad_i[19];
`endif
 
`ifdef GPIO_LINES19
always @(posedge pext_clk[18] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[18] <= #1 1'b0;
else
pextc_sampled[18] <= #1 ext_pad_i[18];
`endif
 
`ifdef GPIO_LINES18
always @(posedge pext_clk[17] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[17] <= #1 1'b0;
else
pextc_sampled[17] <= #1 ext_pad_i[17];
`endif
 
`ifdef GPIO_LINES17
always @(posedge pext_clk[16] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[16] <= #1 1'b0;
else
pextc_sampled[16] <= #1 ext_pad_i[16];
`endif
 
`ifdef GPIO_LINES16
always @(posedge pext_clk[15] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[15] <= #1 1'b0;
else
pextc_sampled[15] <= #1 ext_pad_i[15];
`endif
 
`ifdef GPIO_LINES15
always @(posedge pext_clk[14] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[14] <= #1 1'b0;
else
pextc_sampled[14] <= #1 ext_pad_i[14];
`endif
 
`ifdef GPIO_LINES14
always @(posedge pext_clk[13] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[13] <= #1 1'b0;
else
pextc_sampled[13] <= #1 ext_pad_i[13];
`endif
 
`ifdef GPIO_LINES13
always @(posedge pext_clk[12] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[12] <= #1 1'b0;
else
pextc_sampled[12] <= #1 ext_pad_i[12];
`endif
 
`ifdef GPIO_LINES12
always @(posedge pext_clk[11] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[11] <= #1 1'b0;
else
pextc_sampled[11] <= #1 ext_pad_i[11];
`endif
 
`ifdef GPIO_LINES11
always @(posedge pext_clk[10] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[10] <= #1 1'b0;
else
pextc_sampled[10] <= #1 ext_pad_i[10];
`endif
 
`ifdef GPIO_LINES10
always @(posedge pext_clk[9] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[9] <= #1 1'b0;
else
pextc_sampled[9] <= #1 ext_pad_i[9];
`endif
 
`ifdef GPIO_LINES9
always @(posedge pext_clk[8] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[8] <= #1 1'b0;
else
pextc_sampled[8] <= #1 ext_pad_i[8];
`endif
 
`ifdef GPIO_LINES8
always @(posedge pext_clk[7] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[7] <= #1 1'b0;
else
pextc_sampled[7] <= #1 ext_pad_i[7];
`endif
 
`ifdef GPIO_LINES7
always @(posedge pext_clk[6] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[6] <= #1 1'b0;
else
pextc_sampled[6] <= #1 ext_pad_i[6];
`endif
 
`ifdef GPIO_LINES6
always @(posedge pext_clk[5] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[5] <= #1 1'b0;
else
pextc_sampled[5] <= #1 ext_pad_i[5];
`endif
 
`ifdef GPIO_LINES5
always @(posedge pext_clk[4] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[4] <= #1 1'b0;
else
pextc_sampled[4] <= #1 ext_pad_i[4];
`endif
 
`ifdef GPIO_LINES4
always @(posedge pext_clk[3] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[3] <= #1 1'b0;
else
pextc_sampled[3] <= #1 ext_pad_i[3];
`endif
 
`ifdef GPIO_LINES3
always @(posedge pext_clk[2] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[2] <= #1 1'b0;
else
pextc_sampled[2] <= #1 ext_pad_i[2];
`endif
 
`ifdef GPIO_LINES2
always @(posedge pext_clk[1] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[1] <= #1 1'b0;
else
pextc_sampled[1] <= #1 ext_pad_i[1];
`endif
 
`ifdef GPIO_LINES1
always @(posedge pext_clk[0] or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled[0] <= #1 1'b0;
else
pextc_sampled[0] <= #1 ext_pad_i[0];
`endif
 
//
// Latch using negedge external clock
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
`else
always @(negedge clk_pad_i or posedge wb_rst_i)
if (wb_rst_i)
nextc_sampled <= #1 {gw{1'b0}};
else
nextc_sampled <= #1 ext_pad_i;
`endif
 
//
// Mux all registers when doing a read of GPIO registers
//
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
1515,9 → 1061,9
else if (rgpio_ints_sel && wb_we_i)
rgpio_ints <= #1 wb_dat_i[gw-1:0];
else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
rgpio_ints <= #1 (rgpio_ints | ((ext_pad_i ^ rgpio_in) & ~(ext_pad_i ^ rgpio_ptrig)) & rgpio_inte);
rgpio_ints <= #1 (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte);
`else
assign rgpio_ints = (rgpio_ints | ((ext_pad_i ^ rgpio_in) & ~(ext_pad_i ^ rgpio_ptrig)) & rgpio_inte);
assign rgpio_ints = (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte);
`endif
 
//
1536,7 → 1082,7
wb_inta_o <= #1 wb_inta;
`else
assign wb_inta_o = wb_inta;
`endif
`endif // GPIO_REGISTERED_WB_OUTPUTS
 
//
// Output enables are RGPIO_OE bits
1546,7 → 1092,11
//
// Generate GPIO outputs
//
`ifdef GPIO_AUX_IMPLEMENT
assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
`else
assign out_pad = rgpio_out ;
`endif // GPIO_AUX_IMPLEMENT
 
//
// Optional registration of GPIO outputs
1559,8 → 1109,9
ext_pad_o <= #1 out_pad;
`else
assign ext_pad_o = out_pad;
`endif
`endif // GPIO_REGISTERED_IO_OUTPUTS
 
 
`else
 
//
1578,7 → 1129,7
//
assign wb_dat_o = {dw{1'b0}};
 
`endif
`endif // GPIO_IMPLEMENTED
 
endmodule
 

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