URL
https://opencores.org/ocsvn/gpio/gpio/trunk
Subversion Repositories gpio
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- This comparison shows the changes necessary to convert path
/gpio/trunk/syn/bin
- from Rev 9 to Rev 65
- ↔ Reverse comparison
Rev 9 → Rev 65
/cons_vs_umc18.inc
0,0 → 1,51
/* Constraints */ |
CLK_UNCERTAINTY = 0.1 /* 100 ps */ |
DFFPQ2_CKQ = 0.2 /* Clk to Q in technology time units */ |
DFFPQ2_SETUP = 0.1 /* Setup time in technology time units */ |
|
/* Clocks constraints */ |
create_clock CLK -period CLK_PERIOD |
create_clock ECLK -period CLK_PERIOD |
set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY |
set_dont_touch_network all_clocks() |
|
/* Reset constraints */ |
set_driving_cell -none RST |
set_drive 0 RST |
set_dont_touch_network RST |
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/* All inputs except reset and clock */ |
all_inputs_wo_rst_clk = all_inputs() - CLK - RST |
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/* Set output delays and load for output signals |
* |
* All outputs are assumed to go directly into |
* external flip-flops for the purpose of this |
* synthesis |
*/ |
set_output_delay DFFPQ2_SETUP -clock CLK all_outputs() |
set_load load_of(umcl18u250t2_typ/DFFPQ2/D) * 4 all_outputs() |
|
/* Input delay and driving cell of all inputs |
* |
* All these signals are assumed to come directly from |
* flip-flops for the purpose of this synthesis |
* |
*/ |
set_input_delay DFFPQ2_CKQ -clock CLK all_inputs_wo_rst_clk |
set_driving_cell -cell DFFPQ2 -pin Q all_inputs_wo_rst_clk |
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/* Set design fanout */ |
/* |
set_max_fanout 10 TOPLEVEL |
*/ |
|
/* Set area constraint */ |
set_max_area MAX_AREA |
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/* Optimize all near-critical paths to give extra slack for layout */ |
c_range = CLK_PERIOD * 0.1 |
group_path -critical_range c_range -name CLK -to CLK |
|
/* Operating conditions */ |
set_operating_conditions TYPICAL |
/save_design.inc
0,0 → 1,5
/* Save current design using synopsys format */ |
write -hierarchy -format db -output GATE_PATH + STAGE + _ + TOPLEVEL + .db |
|
/* Save current design using verilog format */ |
write -hierarchy -format verilog -output GATE_PATH + STAGE + _ + TOPLEVEL + .v |
/tech_vs_umc18.inc
0,0 → 1,16
/* Set Virtual Silicon UMC 0.18u standard cell library */ |
|
search_path = {. /libs/Virtual_silicon/UMCL18U250D2_2.1/design_compiler/ } |
snps = get_unix_variable("SYNOPSYS") |
synthetic_library = { \ |
snps + "/libraries/syn/dw01.sldb" \ |
snps + "/libraries/syn/dw02.sldb" \ |
snps + "/libraries/syn/dw03.sldb" \ |
snps + "/libraries/syn/dw04.sldb" \ |
snps + "/libraries/syn/dw05.sldb" \ |
snps + "/libraries/syn/dw06.sldb" \ |
snps + "/libraries/syn/dw07.sldb" } |
target_library = { umcl18u250t2_typ.db } |
link_library = target_library + synthetic_library |
symbol_library = { umcl18u250t2.sdb } |
|
/reports.inc
0,0 → 1,10
/* Basic reports */ |
report_area > LOG_PATH + STAGE + _ + TOPLEVEL + _area.log |
report_timing -nworst 10 > LOG_PATH + STAGE + _ + TOPLEVEL + _timing.log |
report_hierarchy > LOG_PATH + STAGE + _ + TOPLEVEL + _hierarchy.log |
report_resources > LOG_PATH + STAGE + _ + TOPLEVEL + _resources.log |
report_constraint > LOG_PATH + STAGE + _ + TOPLEVEL + _constraint.log |
/* |
report_power > LOG_PATH + STAGE + _ + TOPLEVEL + _power.log |
*/ |
|
/top_gpio.scr
0,0 → 1,65
/* |
* User defines for synthesizing GPIO IP core |
* |
*/ |
TOPLEVEL = gpio |
include select_tech.inc |
CLK = clk_i |
ECLK = gpio_eclk |
RST = rst_i |
CLK_PERIOD = 5 /* 200 MHz */ |
MAX_AREA = 0 /* Push hard */ |
DO_UNGROUP = yes /* yes, no */ |
DO_VERIFY = yes /* yes, no */ |
|
/* Starting timestamp */ |
sh date |
|
/* Set some basic variables related to environment */ |
include set_env.inc |
STAGE = final |
|
/* Load libraries */ |
include tech_ + TECH + .inc |
|
/* Load HDL source files */ |
include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log |
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/* Set design top */ |
current_design TOPLEVEL |
|
/* Link all blocks and uniquify them */ |
link |
uniquify |
check_design > LOG_PATH + check_design_ + TOPLEVEL + .log |
|
/* Apply constraints */ |
if (TECH == "vs_umc18") { |
include cons_vs_umc18.inc |
} else if (TECH == "art_umc18") { |
include cons_art_umc18.inc |
} else { |
echo "Error: Unsupported technology" |
exit |
} |
|
/* Lets do basic synthesis */ |
if (DO_UNGROUP == "yes") { |
ungroup -all |
} |
compile -boundary_optimization -map_effort low |
|
/* Dump gate-level from incremental synthesis */ |
include save_design.inc |
|
/* Generate reports for incremental synthesis */ |
include reports.inc |
|
/* Verify design */ |
if (DO_VERIFY == "yes") { |
compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log |
} |
|
/* Finish */ |
sh date |
exit |
/select_tech.inc
0,0 → 1,5
/* Defaults */ |
|
TECH = vs_umc18 /* vs_umc18, art_umc18 */ |
CLK_PERIOD = 5 /* 200 MHz */ |
MAX_AREA = 0 /* Push hard */ |
/set_env.inc
0,0 → 1,18
/* Enable Verilog HDL preprocessor */ |
hdlin_enable_vpp = true |
|
/* Set log path */ |
LOG_PATH = "../log/" |
|
/* Set gate-level netlist path */ |
GATE_PATH = "../out/" |
|
/* Set RAMS_PATH */ |
RAMS_PATH = "../../../lib/" |
|
/* Set RTL source path */ |
RTL_PATH = "../../rtl/verilog/" |
|
/* Optimize adders */ |
synlib_model_map_effort = high |
hlo_share_effort = medium |
/read_design.inc
0,0 → 1,11
/* Set search path for verilog include files */ |
search_path = search_path + { RTL_PATH } + { GATE_PATH } |
|
/* Read verilog files of the GPIO IP core */ |
if (TOPLEVEL == "gpio") { |
read -f verilog gpio.v |
} else { |
echo "Non-existing top level." |
exit |
} |
|
/cons_art_umc18.inc
0,0 → 1,51
/* Constraints */ |
CLK_UNCERTAINTY = 0.1 /* 100 ps */ |
DFFHQX2_CKQ = 0.2 /* Clk to Q in technology time units */ |
DFFHQX2_SETUP = 0.1 /* Setup time in technology time units */ |
|
/* Clocks constraints */ |
create_clock CLK -period CLK_PERIOD |
create_clock ECLK -period CLK_PERIOD |
set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY |
set_dont_touch_network all_clocks() |
|
/* Reset constraints */ |
set_driving_cell -none RST |
set_drive 0 RST |
set_dont_touch_network RST |
|
/* All inputs except reset and clock */ |
all_inputs_wo_rst_clk = all_inputs() - CLK - RST |
|
/* Set output delays and load for output signals |
* |
* All outputs are assumed to go directly into |
* external flip-flops for the purpose of this |
* synthesis |
*/ |
set_output_delay DFFHQX2_SETUP -clock CLK all_outputs() |
set_load load_of(typical/DFFHQX2/D) * 1 all_outputs() |
|
/* Input delay and driving cell of all inputs |
* |
* All these signals are assumed to come directly from |
* flip-flops for the purpose of this synthesis |
* |
*/ |
set_input_delay DFFHQX2_CKQ -clock CLK all_inputs_wo_rst_clk |
set_driving_cell -cell DFFHQX2 -pin Q all_inputs_wo_rst_clk |
|
/* Set design fanout */ |
/* |
set_max_fanout 10 TOPLEVEL |
*/ |
|
/* Set area constraint */ |
set_max_area MAX_AREA |
|
/* Optimize all near-critical paths to give extra slack for layout */ |
c_range = CLK_PERIOD * 0.05 |
group_path -critical_range c_range -name CLK -to CLK |
|
/* Operating conditions */ |
set_operating_conditions typical |
/tech_art_umc18.inc
0,0 → 1,17
/* Set Artisan Sage-X UMC 0.18u standard cell library */ |
|
search_path = {. /libs/Artisan/aci/sc-x/synopsys/ } + \ |
{ /libs/Artisan/aci/sc-x/symbols/synopsys/ } |
snps = get_unix_variable("SYNOPSYS") |
synthetic_library = { \ |
snps + "/libraries/syn/dw01.sldb" \ |
snps + "/libraries/syn/dw02.sldb" \ |
snps + "/libraries/syn/dw03.sldb" \ |
snps + "/libraries/syn/dw04.sldb" \ |
snps + "/libraries/syn/dw05.sldb" \ |
snps + "/libraries/syn/dw06.sldb" \ |
snps + "/libraries/syn/dw07.sldb" } |
target_library = { typical.db } |
link_library = target_library + synthetic_library |
symbol_library = { umc18.sdb } |
|