URL
https://opencores.org/ocsvn/i2c/i2c/trunk
Subversion Repositories i2c
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 57 to Rev 58
- ↔ Reverse comparison
Rev 57 → Rev 58
/trunk/bench/verilog/tst_bench_top.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: tst_bench_top.v,v 1.7 2005-02-27 09:24:18 rherveille Exp $ |
// $Id: tst_bench_top.v,v 1.8 2006-09-04 09:08:51 rherveille Exp $ |
// |
// $Date: 2005-02-27 09:24:18 $ |
// $Revision: 1.7 $ |
// $Date: 2006-09-04 09:08:51 $ |
// $Revision: 1.8 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.7 2005/02/27 09:24:18 rherveille |
// Fixed scl, sda delay. |
// |
// Revision 1.6 2004/02/28 15:40:42 rherveille |
// *** empty log message *** |
// |
272,6 → 275,11
u0.wb_write(0, CR, 8'h10); // set command (write) |
$display("status: %t write data a5", $time); |
|
while (scl) #1; |
force scl= 1'b0; |
#100000; |
release scl; |
|
// check tip bit |
u0.wb_read(1, SR, q); |
while(q[1]) |
/trunk/bench/verilog/i2c_slave_model.v
36,10 → 36,10
|
// CVS Log |
// |
// $Id: i2c_slave_model.v,v 1.6 2005-02-28 11:33:48 rherveille Exp $ |
// $Id: i2c_slave_model.v,v 1.7 2006-09-04 09:08:51 rherveille Exp $ |
// |
// $Date: 2005-02-28 11:33:48 $ |
// $Revision: 1.6 $ |
// $Date: 2006-09-04 09:08:51 $ |
// $Revision: 1.7 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
46,6 → 46,10
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2005/02/28 11:33:48 rherveille |
// Fixed Tsu:sta timing check. |
// Added Thd:sta timing check. |
// |
// Revision 1.5 2003/12/05 11:05:19 rherveille |
// Fixed slave address MSB='1' bug |
// |
287,7 → 291,7
ld <= #1 1'b1; |
|
if(rw) |
if(sda) // read operation && master send NACK |
if(sr[0]) // read operation && master send NACK |
begin |
state <= #1 idle; |
sda_o <= #1 1'b1; |