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URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

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    from Rev 58 to Rev 57
    Reverse comparison

Rev 58 → Rev 57

/trunk/bench/verilog/i2c_slave_model.v
36,10 → 36,10
 
// CVS Log
//
// $Id: i2c_slave_model.v,v 1.7 2006-09-04 09:08:51 rherveille Exp $
// $Id: i2c_slave_model.v,v 1.6 2005-02-28 11:33:48 rherveille Exp $
//
// $Date: 2006-09-04 09:08:51 $
// $Revision: 1.7 $
// $Date: 2005-02-28 11:33:48 $
// $Revision: 1.6 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
46,10 → 46,6
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.6 2005/02/28 11:33:48 rherveille
// Fixed Tsu:sta timing check.
// Added Thd:sta timing check.
//
// Revision 1.5 2003/12/05 11:05:19 rherveille
// Fixed slave address MSB='1' bug
//
291,7 → 287,7
ld <= #1 1'b1;
 
if(rw)
if(sr[0]) // read operation && master send NACK
if(sda) // read operation && master send NACK
begin
state <= #1 idle;
sda_o <= #1 1'b1;
/trunk/bench/verilog/tst_bench_top.v
37,10 → 37,10
 
// CVS Log
//
// $Id: tst_bench_top.v,v 1.8 2006-09-04 09:08:51 rherveille Exp $
// $Id: tst_bench_top.v,v 1.7 2005-02-27 09:24:18 rherveille Exp $
//
// $Date: 2006-09-04 09:08:51 $
// $Revision: 1.8 $
// $Date: 2005-02-27 09:24:18 $
// $Revision: 1.7 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
47,9 → 47,6
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.7 2005/02/27 09:24:18 rherveille
// Fixed scl, sda delay.
//
// Revision 1.6 2004/02/28 15:40:42 rherveille
// *** empty log message ***
//
275,11 → 272,6
u0.wb_write(0, CR, 8'h10); // set command (write)
$display("status: %t write data a5", $time);
 
while (scl) #1;
force scl= 1'b0;
#100000;
release scl;
 
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])

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