URL
https://opencores.org/ocsvn/i2c/i2c/trunk
Subversion Repositories i2c
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- This comparison shows the changes necessary to convert path
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- from Rev 66 to Rev 65
- ↔ Reverse comparison
Rev 66 → Rev 65
/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
37,10 → 37,10
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-- CVS Log |
-- |
-- $Id: i2c_master_bit_ctrl.vhd,v 1.16 2009-01-20 20:40:36 rherveille Exp $ |
-- $Id: i2c_master_bit_ctrl.vhd,v 1.15 2009-01-20 10:34:51 rherveille Exp $ |
-- |
-- $Date: 2009-01-20 20:40:36 $ |
-- $Revision: 1.16 $ |
-- $Date: 2009-01-20 10:34:51 $ |
-- $Revision: 1.15 $ |
-- $Author: rherveille $ |
-- $Locker: $ |
-- $State: Exp $ |
47,10 → 47,6
-- |
-- Change History: |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.15 2009/01/20 10:34:51 rherveille |
-- Added SCL clock synchronization logic |
-- Fixed slave_wait signal generation |
-- |
-- Revision 1.14 2006/10/11 12:10:13 rherveille |
-- Added missing semicolons ';' on endif |
-- |
207,13 → 203,13
if (nReset = '0') then |
slave_wait <= '0'; |
else |
slave_wait <= (iscl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL); |
slave_wait <= (scl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL); |
end if; |
end process; |
|
-- master drives SCL high, but another master pulls it low |
-- master start counting down its low cycle now (clock synchronization) |
scl_sync <= dSCL and not sSCL and iscl_oen; |
scl_sync <= dSCL and not sSCL and scl_oen; |
|
-- generate clk enable signal |
gen_clken: process(clk, nReset) |