OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 54 to Rev 55
    Reverse comparison

Rev 54 → Rev 55

/trunk/rtl/verilog/i2c_master_top.v
37,10 → 37,10
 
// CVS Log
//
// $Id: i2c_master_top.v,v 1.10 2003-09-01 10:34:38 rherveille Exp $
// $Id: i2c_master_top.v,v 1.11 2005-02-27 09:26:24 rherveille Exp $
//
// $Date: 2003-09-01 10:34:38 $
// $Revision: 1.10 $
// $Date: 2005-02-27 09:26:24 $
// $Revision: 1.11 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
47,6 → 47,9
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.10 2003/09/01 10:34:38 rherveille
// Fix a blocking vs. non-blocking error in the wb_dat output mux.
//
// Revision 1.9 2003/01/09 16:44:45 rherveille
// Fixed a bug in the Command Register declaration.
//
155,7 → 158,7
// assign DAT_O
always @(posedge wb_clk_i)
begin
case (wb_adr_i) // synopsis full_case parallel_case
case (wb_adr_i) // synopsis parallel_case
3'b000: wb_dat_o <= #1 prer[ 7:0];
3'b001: wb_dat_o <= #1 prer[15:8];
3'b010: wb_dat_o <= #1 ctr;
183,11 → 186,12
end
else
if (wb_wacc)
case (wb_adr_i) // synopsis full_case parallel_case
case (wb_adr_i) // synopsis parallel_case
3'b000 : prer [ 7:0] <= #1 wb_dat_i;
3'b001 : prer [15:8] <= #1 wb_dat_i;
3'b010 : ctr <= #1 wb_dat_i;
3'b011 : txr <= #1 wb_dat_i;
default: ;
endcase
 
// generate command register (special case)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.