URL
https://opencores.org/ocsvn/i2c/i2c/trunk
Subversion Repositories i2c
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- This comparison shows the changes necessary to convert path
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- from Rev 56 to Rev 57
- ↔ Reverse comparison
Rev 56 → Rev 57
/trunk/rtl/verilog/i2c_master_bit_ctrl.v
37,10 → 37,10
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// CVS Log |
// |
// $Id: i2c_master_bit_ctrl.v,v 1.11 2004-05-07 11:02:26 rherveille Exp $ |
// $Id: i2c_master_bit_ctrl.v,v 1.12 2006-09-04 09:08:13 rherveille Exp $ |
// |
// $Date: 2004-05-07 11:02:26 $ |
// $Revision: 1.11 $ |
// $Date: 2006-09-04 09:08:13 $ |
// $Revision: 1.12 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.11 2004/05/07 11:02:26 rherveille |
// Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. |
// |
// Revision 1.10 2003/08/09 07:01:33 rherveille |
// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. |
// Fixed a potential bug in the byte controller's host-acknowledge generation. |
201,20 → 204,19
cnt <= #1 16'h0; |
clk_en <= #1 1'b1; |
end |
else if ( ~|cnt || ~ena) |
if (~slave_wait) |
begin |
cnt <= #1 clk_cnt; |
clk_en <= #1 1'b1; |
end |
else |
begin |
cnt <= #1 cnt; |
clk_en <= #1 1'b0; |
end |
else if ( ~|cnt || !ena) |
begin |
cnt <= #1 clk_cnt; |
clk_en <= #1 1'b1; |
end |
else if (slave_wait) |
begin |
cnt <= #1 cnt; |
clk_en <= #1 1'b0; |
end |
else |
begin |
cnt <= #1 cnt - 16'h1; |
cnt <= #1 cnt - 16'h1; |
clk_en <= #1 1'b0; |
end |
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