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https://opencores.org/ocsvn/i2c/i2c/trunk
Subversion Repositories i2c
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- from Rev 61 to Rev 62
- ↔ Reverse comparison
Rev 61 → Rev 62
/trunk/rtl/verilog/i2c_master_byte_ctrl.v
37,10 → 37,10
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// CVS Log |
// |
// $Id: i2c_master_byte_ctrl.v,v 1.7 2004-02-18 11:40:46 rherveille Exp $ |
// $Id: i2c_master_byte_ctrl.v,v 1.8 2009-01-19 20:29:26 rherveille Exp $ |
// |
// $Date: 2004-02-18 11:40:46 $ |
// $Revision: 1.7 $ |
// $Date: 2009-01-19 20:29:26 $ |
// $Revision: 1.8 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.7 2004/02/18 11:40:46 rherveille |
// Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. |
// |
// Revision 1.6 2003/08/09 07:01:33 rherveille |
// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. |
// Fixed a potential bug in the byte controller's host-acknowledge generation. |
193,7 → 196,7
// |
// state machine |
// |
reg [4:0] c_state; // synopsis enum_state |
reg [4:0] c_state; // synopsys enum_state |
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always @(posedge clk or negedge nReset) |
if (!nReset) |
/trunk/rtl/verilog/i2c_master_bit_ctrl.v
37,10 → 37,10
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// CVS Log |
// |
// $Id: i2c_master_bit_ctrl.v,v 1.12 2006-09-04 09:08:13 rherveille Exp $ |
// $Id: i2c_master_bit_ctrl.v,v 1.13 2009-01-19 20:29:26 rherveille Exp $ |
// |
// $Date: 2006-09-04 09:08:13 $ |
// $Revision: 1.12 $ |
// $Date: 2009-01-19 20:29:26 $ |
// $Revision: 1.13 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,10
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.12 2006/09/04 09:08:13 rherveille |
// fixed short scl high pulse after clock stretch |
// fixed slave model not returning correct '(n)ack' signal |
// |
// Revision 1.11 2004/05/07 11:02:26 rherveille |
// Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. |
// |
178,7 → 182,7
reg [15:0] cnt; // clock divider counter (synthesis) |
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// state machine variable |
reg [16:0] c_state; // synopsys enum_state |
reg [17:0] c_state; // synopsys enum_state |
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// |
// module body |
312,24 → 316,24
// generate statemachine |
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// nxt_state decoder |
parameter [16:0] idle = 17'b0_0000_0000_0000_0000; |
parameter [16:0] start_a = 17'b0_0000_0000_0000_0001; |
parameter [16:0] start_b = 17'b0_0000_0000_0000_0010; |
parameter [16:0] start_c = 17'b0_0000_0000_0000_0100; |
parameter [16:0] start_d = 17'b0_0000_0000_0000_1000; |
parameter [16:0] start_e = 17'b0_0000_0000_0001_0000; |
parameter [16:0] stop_a = 17'b0_0000_0000_0010_0000; |
parameter [16:0] stop_b = 17'b0_0000_0000_0100_0000; |
parameter [16:0] stop_c = 17'b0_0000_0000_1000_0000; |
parameter [16:0] stop_d = 17'b0_0000_0001_0000_0000; |
parameter [16:0] rd_a = 17'b0_0000_0010_0000_0000; |
parameter [16:0] rd_b = 17'b0_0000_0100_0000_0000; |
parameter [16:0] rd_c = 17'b0_0000_1000_0000_0000; |
parameter [16:0] rd_d = 17'b0_0001_0000_0000_0000; |
parameter [16:0] wr_a = 17'b0_0010_0000_0000_0000; |
parameter [16:0] wr_b = 17'b0_0100_0000_0000_0000; |
parameter [16:0] wr_c = 17'b0_1000_0000_0000_0000; |
parameter [16:0] wr_d = 17'b1_0000_0000_0000_0000; |
parameter [17:0] idle = 18'b0_0000_0000_0000_0000; |
parameter [17:0] start_a = 18'b0_0000_0000_0000_0001; |
parameter [17:0] start_b = 18'b0_0000_0000_0000_0010; |
parameter [17:0] start_c = 18'b0_0000_0000_0000_0100; |
parameter [17:0] start_d = 18'b0_0000_0000_0000_1000; |
parameter [17:0] start_e = 18'b0_0000_0000_0001_0000; |
parameter [17:0] stop_a = 18'b0_0000_0000_0010_0000; |
parameter [17:0] stop_b = 18'b0_0000_0000_0100_0000; |
parameter [17:0] stop_c = 18'b0_0000_0000_1000_0000; |
parameter [17:0] stop_d = 18'b0_0000_0001_0000_0000; |
parameter [17:0] rd_a = 18'b0_0000_0010_0000_0000; |
parameter [17:0] rd_b = 18'b0_0000_0100_0000_0000; |
parameter [17:0] rd_c = 18'b0_0000_1000_0000_0000; |
parameter [17:0] rd_d = 18'b0_0001_0000_0000_0000; |
parameter [17:0] wr_a = 18'b0_0010_0000_0000_0000; |
parameter [17:0] wr_b = 18'b0_0100_0000_0000_0000; |
parameter [17:0] wr_c = 18'b0_1000_0000_0000_0000; |
parameter [17:0] wr_d = 18'b1_0000_0000_0000_0000; |
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always @(posedge clk or negedge nReset) |
if (!nReset) |
/trunk/rtl/verilog/i2c_master_top.v
37,10 → 37,10
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// CVS Log |
// |
// $Id: i2c_master_top.v,v 1.11 2005-02-27 09:26:24 rherveille Exp $ |
// $Id: i2c_master_top.v,v 1.12 2009-01-19 20:29:26 rherveille Exp $ |
// |
// $Date: 2005-02-27 09:26:24 $ |
// $Revision: 1.11 $ |
// $Date: 2009-01-19 20:29:26 $ |
// $Revision: 1.12 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,10
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.11 2005/02/27 09:26:24 rherveille |
// Fixed register overwrite issue. |
// Removed full_case pragma, replaced it by a default statement. |
// |
// Revision 1.10 2003/09/01 10:34:38 rherveille |
// Fix a blocking vs. non-blocking error in the wb_dat output mux. |
// |
158,7 → 162,7
// assign DAT_O |
always @(posedge wb_clk_i) |
begin |
case (wb_adr_i) // synopsis parallel_case |
case (wb_adr_i) // synopsys parallel_case |
3'b000: wb_dat_o <= #1 prer[ 7:0]; |
3'b001: wb_dat_o <= #1 prer[15:8]; |
3'b010: wb_dat_o <= #1 ctr; |
186,7 → 190,7
end |
else |
if (wb_wacc) |
case (wb_adr_i) // synopsis parallel_case |
case (wb_adr_i) // synopsys parallel_case |
3'b000 : prer [ 7:0] <= #1 wb_dat_i; |
3'b001 : prer [15:8] <= #1 wb_dat_i; |
3'b010 : ctr <= #1 wb_dat_i; |
196,7 → 200,7
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// generate command register (special case) |
always @(posedge wb_clk_i or negedge rst_i) |
if (~rst_i) |
if (!rst_i) |
cr <= #1 8'h0; |
else if (wb_rst_i) |
cr <= #1 8'h0; |
211,7 → 215,7
cr[7:4] <= #1 4'h0; // clear command bits when done |
// or when aribitration lost |
cr[2:1] <= #1 2'b0; // reserved bits |
cr[0] <= #1 2'b0; // clear IRQ_ACK bit |
cr[0] <= #1 1'b0; // clear IRQ_ACK bit |
end |
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