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/syn/mesi_isc.flow.rpt File deleted
/syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.cdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hbdb.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hbdb.hdb =================================================================== --- syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hbdb.hdb (revision 4) +++ syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hbdb.hdb (nonexistent)
syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hbdb.hdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.dfp =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.dfp =================================================================== --- syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.dfp (revision 4) +++ syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.dfp (nonexistent)
syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.dfp Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.dpi =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.dpi =================================================================== --- syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.dpi (revision 4) +++ syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.dpi (nonexistent)
syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.dpi Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hdb =================================================================== --- syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hdb (revision 4) +++ syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hdb (nonexistent)
syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.kpt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.kpt =================================================================== --- syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.kpt (revision 4) +++ syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.kpt (nonexistent)
syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.kpt Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.hdb =================================================================== --- syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.hdb (revision 4) +++ syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.hdb (nonexistent)
syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.hdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hbdb.sig =================================================================== --- syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hbdb.sig (revision 4) +++ syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hbdb.sig (nonexistent) @@ -1 +0,0 @@ -6d99a1516c2e2beefe1f386eab1dd580 \ No newline at end of file Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.kpt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.kpt =================================================================== --- syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.kpt (revision 4) +++ syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.kpt (nonexistent)
syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.kpt Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.rcfdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.rcfdb =================================================================== --- syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.rcfdb (revision 4) +++ syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.rcfdb (nonexistent)
syn/incremental_db/compiled_partitions/mesi_isc.root_partition.cmp.rcfdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hbdb.hb_info =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hbdb.hb_info =================================================================== --- syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hbdb.hb_info (revision 4) +++ syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hbdb.hb_info (nonexistent)
syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hbdb.hb_info Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hbdb.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hbdb.cdb =================================================================== --- syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hbdb.cdb (revision 4) +++ syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hbdb.cdb (nonexistent)
syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.hbdb.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.cdb =================================================================== --- syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.cdb (revision 4) +++ syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.cdb (nonexistent)
syn/incremental_db/compiled_partitions/mesi_isc.root_partition.map.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/incremental_db/README =================================================================== --- syn/incremental_db/README (revision 4) +++ syn/incremental_db/README (nonexistent) @@ -1,11 +0,0 @@ -This folder contains data for incremental compilation. - -The compiled_partitions sub-folder contains previous compilation results for each partition. -As long as this folder is preserved, incremental compilation results from earlier compiles -can be re-used. To perform a clean compilation from source files for all partitions, both -the db and incremental_db folder should be removed. - -The imported_partitions sub-folder contains the last imported QXP for each imported partition. -As long as this folder is preserved, imported partitions will be automatically re-imported -when the db or incremental_db/compiled_partitions folders are removed. - Index: syn/mesi_isc.fit.summary =================================================================== --- syn/mesi_isc.fit.summary (revision 4) +++ syn/mesi_isc.fit.summary (nonexistent) @@ -1,20 +0,0 @@ -Fitter Status : Successful - Tue Dec 25 13:54:52 2012 -Quartus II 32-bit Version : 12.0 Build 263 08/02/2012 SP 2 SJ Web Edition -Revision Name : mesi_isc -Top-level Entity Name : mesi_isc -Family : Cyclone IV GX -Device : EP4CGX30CF23C6 -Timing Models : Final -Total logic elements : 827 / 29,440 ( 3 % ) - Total combinational functions : 481 / 29,440 ( 2 % ) - Dedicated logic registers : 604 / 29,440 ( 2 % ) -Total registers : 640 -Total pins : 194 / 307 ( 63 % ) -Total virtual pins : 0 -Total memory bits : 0 / 1,105,920 ( 0 % ) -Embedded Multiplier 9-bit elements : 0 / 160 ( 0 % ) -Total GXB Receiver Channel PCS : 0 / 4 ( 0 % ) -Total GXB Receiver Channel PMA : 0 / 4 ( 0 % ) -Total GXB Transmitter Channel PCS : 0 / 4 ( 0 % ) -Total GXB Transmitter Channel PMA : 0 / 4 ( 0 % ) -Total PLLs : 0 / 6 ( 0 % ) Index: syn/README.txt =================================================================== --- syn/README.txt (revision 4) +++ syn/README.txt (nonexistent) @@ -1,9 +0,0 @@ -MESI_ISC Project -================= - -Directoy: syn -================= - -A synthesis environment of the project. - -./run_syn - Run synthesis. Index: syn/mesi_isc.map.rpt =================================================================== --- syn/mesi_isc.map.rpt (revision 4) +++ syn/mesi_isc.map.rpt (nonexistent) @@ -1,521 +0,0 @@ -Analysis & Synthesis report for mesi_isc -Tue Dec 25 13:54:13 2012 -Quartus II 32-bit Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Analysis & Synthesis Summary - 3. Analysis & Synthesis Settings - 4. Parallel Compilation - 5. Analysis & Synthesis Source Files Read - 6. Analysis & Synthesis Resource Usage Summary - 7. Analysis & Synthesis Resource Utilization by Entity - 8. General Register Statistics - 9. Inverted Register Statistics - 10. Multiplexer Restructuring Statistics (Restructuring Performed) - 11. Parameter Settings for User Entity Instance: Top-level Entity: |mesi_isc - 12. Parameter Settings for User Entity Instance: mesi_isc_broad:mesi_isc_broad - 13. Parameter Settings for User Entity Instance: mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl - 14. Parameter Settings for User Entity Instance: mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo - 15. Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos - 16. Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl - 17. Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3 - 18. Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2 - 19. Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1 - 20. Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0 - 21. Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0" - 22. Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1" - 23. Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2" - 24. Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3" - 25. Port Connectivity Checks: "mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl" - 26. Elapsed Time Per Partition - 27. Analysis & Synthesis Messages - 28. Analysis & Synthesis Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2012 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+------------------------------------------------------------------------------------+ -; Analysis & Synthesis Summary ; -+------------------------------------+-----------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Tue Dec 25 13:54:13 2012 ; -; Quartus II 32-bit Version ; 12.0 Build 263 08/02/2012 SP 2 SJ Web Edition ; -; Revision Name ; mesi_isc ; -; Top-level Entity Name ; mesi_isc ; -; Family ; Cyclone IV GX ; -; Total logic elements ; 863 ; -; Total combinational functions ; 481 ; -; Dedicated logic registers ; 636 ; -; Total registers ; 636 ; -; Total pins ; 194 ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 ; -; Embedded Multiplier 9-bit elements ; 0 ; -; Total GXB Receiver Channel PCS ; 0 ; -; Total GXB Receiver Channel PMA ; 0 ; -; Total GXB Transmitter Channel PCS ; 0 ; -; Total GXB Transmitter Channel PMA ; 0 ; -; Total PLLs ; 0 ; -+------------------------------------+-----------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Settings ; -+----------------------------------------------------------------------------+--------------------+--------------------+ -; Option ; Setting ; Default Value ; -+----------------------------------------------------------------------------+--------------------+--------------------+ -; Top-level entity name ; mesi_isc ; mesi_isc ; -; Family name ; Cyclone IV GX ; Cyclone IV GX ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Restructure Multiplexers ; Auto ; Auto ; -; Create Debugging Nodes for IP Cores ; Off ; Off ; -; Preserve fewer node names ; On ; On ; -; Disable OpenCore Plus hardware evaluation ; Off ; Off ; -; Verilog Version ; Verilog_2001 ; Verilog_2001 ; -; VHDL Version ; VHDL_1993 ; VHDL_1993 ; -; State Machine Processing ; Auto ; Auto ; -; Safe State Machine ; Off ; Off ; -; Extract Verilog State Machines ; On ; On ; -; Extract VHDL State Machines ; On ; On ; -; Ignore Verilog initial constructs ; Off ; Off ; -; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; -; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; -; Add Pass-Through Logic to Inferred RAMs ; On ; On ; -; Infer RAMs from Raw Logic ; On ; On ; -; Parallel Synthesis ; On ; On ; -; DSP Block Balancing ; Auto ; Auto ; -; NOT Gate Push-Back ; On ; On ; -; Power-Up Don't Care ; On ; On ; -; Remove Redundant Logic Cells ; Off ; Off ; -; Remove Duplicate Registers ; On ; On ; -; Ignore CARRY Buffers ; Off ; Off ; -; Ignore CASCADE Buffers ; Off ; Off ; -; Ignore GLOBAL Buffers ; Off ; Off ; -; Ignore ROW GLOBAL Buffers ; Off ; Off ; -; Ignore LCELL Buffers ; Off ; Off ; -; Ignore SOFT Buffers ; On ; On ; -; Limit AHDL Integers to 32 Bits ; Off ; Off ; -; Optimization Technique ; Balanced ; Balanced ; -; Carry Chain Length ; 70 ; 70 ; -; Auto Carry Chains ; On ; On ; -; Auto Open-Drain Pins ; On ; On ; -; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; -; Auto ROM Replacement ; On ; On ; -; Auto RAM Replacement ; On ; On ; -; Auto DSP Block Replacement ; On ; On ; -; Auto Shift Register Replacement ; Auto ; Auto ; -; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; -; Auto Clock Enable Replacement ; On ; On ; -; Strict RAM Replacement ; Off ; Off ; -; Allow Synchronous Control Signals ; On ; On ; -; Force Use of Synchronous Clear Signals ; Off ; Off ; -; Auto RAM Block Balancing ; On ; On ; -; Auto RAM to Logic Cell Conversion ; Off ; Off ; -; Auto Resource Sharing ; Off ; Off ; -; Allow Any RAM Size For Recognition ; Off ; Off ; -; Allow Any ROM Size For Recognition ; Off ; Off ; -; Allow Any Shift Register Size For Recognition ; Off ; Off ; -; Use LogicLock Constraints during Resource Balancing ; On ; On ; -; Ignore translate_off and synthesis_off directives ; Off ; Off ; -; Timing-Driven Synthesis ; On ; On ; -; Report Parameter Settings ; On ; On ; -; Report Source Assignments ; On ; On ; -; Report Connectivity Checks ; On ; On ; -; Ignore Maximum Fan-Out Assignments ; Off ; Off ; -; Synchronization Register Chain Length ; 2 ; 2 ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; HDL message level ; Level2 ; Level2 ; -; Suppress Register Optimization Related Messages ; Off ; Off ; -; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; -; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; -; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; -; Clock MUX Protection ; On ; On ; -; Auto Gated Clock Conversion ; Off ; Off ; -; Block Design Naming ; Auto ; Auto ; -; SDC constraint protection ; Off ; Off ; -; Synthesis Effort ; Auto ; Auto ; -; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; -; Analysis & Synthesis Message Level ; Medium ; Medium ; -; Disable Register Merging Across Hierarchies ; Auto ; Auto ; -; Resource Aware Inference For Block RAM ; On ; On ; -; Synthesis Seed ; 1 ; 1 ; -+----------------------------------------------------------------------------+--------------------+--------------------+ - - -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+---------------------------------------+-----------------+------------------------+----------------------------------------------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+---------------------------------------+-----------------+------------------------+----------------------------------------------------------------------+---------+ -; ../src/rtl/mesi_isc_define.v ; yes ; User Verilog HDL File ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_define.v ; ; -; ../src/rtl/mesi_isc_broad_cntl.v ; yes ; User Verilog HDL File ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad_cntl.v ; ; -; ../src/rtl/mesi_isc_broad.v ; yes ; User Verilog HDL File ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad.v ; ; -; ../src/rtl/mesi_isc_breq_fifos_cntl.v ; yes ; User Verilog HDL File ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos_cntl.v ; ; -; ../src/rtl/mesi_isc_breq_fifos.v ; yes ; User Verilog HDL File ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos.v ; ; -; ../src/rtl/mesi_isc_basic_fifo.v ; yes ; User Verilog HDL File ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v ; ; -; ../src/rtl/mesi_isc.v ; yes ; User Verilog HDL File ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v ; ; -+---------------------------------------+-----------------+------------------------+----------------------------------------------------------------------+---------+ - - -+---------------------------------------------+ -; Analysis & Synthesis Resource Usage Summary ; -+----------------------+----------------------+ -; Resource ; Usage ; -+----------------------+----------------------+ -; I/O pins ; 194 ; -; Maximum fan-out node ; clk~input ; -; Maximum fan-out ; 636 ; -; Total fan-out ; 4466 ; -; Average fan-out ; 2.97 ; -+----------------------+----------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Utilization by Entity ; -+-----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------+--------------+ -; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; -+-----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------+--------------+ -; |mesi_isc ; 481 (0) ; 636 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 194 ; 0 ; |mesi_isc ; ; -; |mesi_isc_breq_fifos:mesi_isc_breq_fifos| ; 312 (0) ; 440 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos ; ; -; |mesi_isc_basic_fifo:fifo_0| ; 41 (41) ; 106 (106) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0 ; ; -; |mesi_isc_basic_fifo:fifo_1| ; 41 (41) ; 106 (106) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1 ; ; -; |mesi_isc_basic_fifo:fifo_2| ; 41 (41) ; 106 (106) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2 ; ; -; |mesi_isc_basic_fifo:fifo_3| ; 41 (41) ; 106 (106) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3 ; ; -; |mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl| ; 148 (148) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl ; ; -; |mesi_isc_broad:mesi_isc_broad| ; 169 (0) ; 196 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |mesi_isc|mesi_isc_broad:mesi_isc_broad ; ; -; |mesi_isc_basic_fifo:broad_fifo| ; 124 (124) ; 186 (186) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo ; ; -; |mesi_isc_broad_cntl:mesi_isc_broad_cntl| ; 45 (45) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl ; ; -+-----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+------------------------------------------------------+ -; General Register Statistics ; -+----------------------------------------------+-------+ -; Statistic ; Value ; -+----------------------------------------------+-------+ -; Total registers ; 636 ; -; Number of registers using Synchronous Clear ; 0 ; -; Number of registers using Synchronous Load ; 136 ; -; Number of registers using Asynchronous Clear ; 636 ; -; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 427 ; -; Number of registers using Preset ; 0 ; -+----------------------------------------------+-------+ - - -+-----------------------------------------------------------------------------------------------------------------------+ -; Inverted Register Statistics ; -+-------------------------------------------------------------------------------------------------------------+---------+ -; Inverted Register ; Fan out ; -+-------------------------------------------------------------------------------------------------------------+---------+ -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifos_priority[0] ; 9 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|status_empty ; 39 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|status_empty ; 39 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|status_empty ; 39 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|status_empty ; 39 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|status_empty ; 47 ; -; Total number of inverted registers = 6 ; ; -+-------------------------------------------------------------------------------------------------------------+---------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Multiplexer Restructuring Statistics (Restructuring Performed) ; -+--------------------+-----------+---------------+----------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------+----------------------------+ -; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; -+--------------------+-----------+---------------+----------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------+----------------------------+ -; 5:1 ; 34 bits ; 102 LEs ; 68 LEs ; 34 LEs ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[27] ; ; -; 5:1 ; 34 bits ; 102 LEs ; 68 LEs ; 34 LEs ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[33] ; ; -; 5:1 ; 34 bits ; 102 LEs ; 68 LEs ; 34 LEs ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[29] ; ; -; 5:1 ; 34 bits ; 102 LEs ; 68 LEs ; 34 LEs ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[25] ; ; -; 5:1 ; 4 bits ; 12 LEs ; 4 LEs ; 8 LEs ; |mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[3] ; ; -; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; |mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; ; -; 9:1 ; 36 bits ; 216 LEs ; 108 LEs ; 108 LEs ; |mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[21] ; ; -; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifo_select_oh[0] ; ; -+--------------------+-----------+---------------+----------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------+----------------------------+ - - -+--------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Top-level Entity: |mesi_isc ; -+--------------------------+-------+---------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------+-------+---------------------------------------+ -; CBUS_CMD_WIDTH ; 3 ; Signed Integer ; -; ADDR_WIDTH ; 32 ; Signed Integer ; -; BROAD_TYPE_WIDTH ; 2 ; Signed Integer ; -; BROAD_ID_WIDTH ; 5 ; Signed Integer ; -; BROAD_REQ_FIFO_SIZE ; 4 ; Signed Integer ; -; BROAD_REQ_FIFO_SIZE_LOG2 ; 2 ; Signed Integer ; -; MBUS_CMD_WIDTH ; 3 ; Signed Integer ; -; BREQ_FIFO_SIZE ; 2 ; Signed Integer ; -; BREQ_FIFO_SIZE_LOG2 ; 1 ; Signed Integer ; -+--------------------------+-------+---------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: mesi_isc_broad:mesi_isc_broad ; -+--------------------------+-------+-----------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------+-------+-----------------------------------------+ -; CBUS_CMD_WIDTH ; 3 ; Signed Integer ; -; ADDR_WIDTH ; 32 ; Signed Integer ; -; BROAD_TYPE_WIDTH ; 2 ; Signed Integer ; -; BROAD_ID_WIDTH ; 5 ; Signed Integer ; -; BROAD_REQ_FIFO_SIZE ; 4 ; Signed Integer ; -; BROAD_REQ_FIFO_SIZE_LOG2 ; 2 ; Signed Integer ; -+--------------------------+-------+-----------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl ; -+------------------+-------+-----------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------+-------+-----------------------------------------------------------------------------------------+ -; CBUS_CMD_WIDTH ; 3 ; Signed Integer ; -; BROAD_TYPE_WIDTH ; 2 ; Signed Integer ; -; BROAD_ID_WIDTH ; 5 ; Signed Integer ; -+------------------+-------+-----------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo ; -+----------------+-------+----------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------+ -; DATA_WIDTH ; 41 ; Signed Integer ; -; FIFO_SIZE ; 4 ; Signed Integer ; -; FIFO_SIZE_LOG2 ; 2 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos ; -+---------------------+-------+--------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------+ -; MBUS_CMD_WIDTH ; 3 ; Signed Integer ; -; ADDR_WIDTH ; 32 ; Signed Integer ; -; BROAD_TYPE_WIDTH ; 2 ; Signed Integer ; -; BROAD_ID_WIDTH ; 5 ; Signed Integer ; -; BREQ_FIFO_SIZE ; 2 ; Signed Integer ; -; BREQ_FIFO_SIZE_LOG2 ; 1 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl ; -+------------------+-------+-------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------+-------+-------------------------------------------------------------------------------------------------------------+ -; MBUS_CMD_WIDTH ; 3 ; Signed Integer ; -; ADDR_WIDTH ; 32 ; Signed Integer ; -; BROAD_TYPE_WIDTH ; 2 ; Signed Integer ; -; BROAD_ID_WIDTH ; 5 ; Signed Integer ; -+------------------+-------+-------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3 ; -+----------------+-------+----------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 41 ; Signed Integer ; -; FIFO_SIZE ; 2 ; Signed Integer ; -; FIFO_SIZE_LOG2 ; 1 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2 ; -+----------------+-------+----------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 41 ; Signed Integer ; -; FIFO_SIZE ; 2 ; Signed Integer ; -; FIFO_SIZE_LOG2 ; 1 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1 ; -+----------------+-------+----------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 41 ; Signed Integer ; -; FIFO_SIZE ; 2 ; Signed Integer ; -; FIFO_SIZE_LOG2 ; 1 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0 ; -+----------------+-------+----------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------+ -; DATA_WIDTH ; 41 ; Signed Integer ; -; FIFO_SIZE ; 2 ; Signed Integer ; -; FIFO_SIZE_LOG2 ; 1 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0" ; -+--------------+--------+----------+-------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------+--------+----------+-------------------------------------------------------------------------------------+ -; data_o[6..5] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+--------------+--------+----------+-------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1" ; -+--------------+--------+----------+-------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------+--------+----------+-------------------------------------------------------------------------------------+ -; data_o[6..5] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+--------------+--------+----------+-------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2" ; -+--------------+--------+----------+-------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------+--------+----------+-------------------------------------------------------------------------------------+ -; data_o[6..5] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+--------------+--------+----------+-------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3" ; -+--------------+--------+----------+-------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------+--------+----------+-------------------------------------------------------------------------------------+ -; data_o[6..5] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+--------------+--------+----------+-------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl" ; -+----------------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; fifo_status_almost_empty_i ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; fifo_status_almost_full_i ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -+----------------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------+ -; Elapsed Time Per Partition ; -+----------------+--------------+ -; Partition Name ; Elapsed Time ; -+----------------+--------------+ -; Top ; 00:00:02 ; -+----------------+--------------+ - - -+-------------------------------+ -; Analysis & Synthesis Messages ; -+-------------------------------+ -Info: ******************************************************************* -Info: Running Quartus II 32-bit Analysis & Synthesis - Info: Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition - Info: Processing started: Tue Dec 25 13:54:09 2012 -Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mesi_isc -c mesi_isc -Warning (20028): Parallel compilation is not licensed and has been disabled -Info (12021): Found 0 design units, including 0 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_define.v -Info (12021): Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad_cntl.v - Info (12023): Found entity 1: mesi_isc_broad_cntl -Info (12021): Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad.v - Info (12023): Found entity 1: mesi_isc_broad -Info (12021): Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos_cntl.v - Info (12023): Found entity 1: mesi_isc_breq_fifos_cntl -Info (12021): Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos.v - Info (12023): Found entity 1: mesi_isc_breq_fifos -Info (12021): Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v - Info (12023): Found entity 1: mesi_isc_basic_fifo -Info (12021): Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v - Info (12023): Found entity 1: mesi_isc -Info (12127): Elaborating entity "mesi_isc" for the top level hierarchy -Info (12128): Elaborating entity "mesi_isc_broad" for hierarchy "mesi_isc_broad:mesi_isc_broad" -Info (12128): Elaborating entity "mesi_isc_broad_cntl" for hierarchy "mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl" -Info (12128): Elaborating entity "mesi_isc_basic_fifo" for hierarchy "mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo" -Warning (10230): Verilog HDL assignment warning at mesi_isc_basic_fifo.v(122): truncated value with size 32 to match size of target (2) -Warning (10240): Verilog HDL Always Construct warning at mesi_isc_basic_fifo.v(112): inferring latch(es) for variable "i", which holds its previous value in one or more paths through the always construct -Warning (10230): Verilog HDL assignment warning at mesi_isc_basic_fifo.v(154): truncated value with size 32 to match size of target (2) -Warning (10230): Verilog HDL assignment warning at mesi_isc_basic_fifo.v(157): truncated value with size 32 to match size of target (2) -Info (12128): Elaborating entity "mesi_isc_breq_fifos" for hierarchy "mesi_isc_breq_fifos:mesi_isc_breq_fifos" -Info (12128): Elaborating entity "mesi_isc_breq_fifos_cntl" for hierarchy "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl" -Warning (10230): Verilog HDL assignment warning at mesi_isc_breq_fifos_cntl.v(371): truncated value with size 32 to match size of target (3) -Info (12128): Elaborating entity "mesi_isc_basic_fifo" for hierarchy "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3" -Warning (10230): Verilog HDL assignment warning at mesi_isc_basic_fifo.v(122): truncated value with size 32 to match size of target (1) -Warning (10240): Verilog HDL Always Construct warning at mesi_isc_basic_fifo.v(112): inferring latch(es) for variable "i", which holds its previous value in one or more paths through the always construct -Warning (10230): Verilog HDL assignment warning at mesi_isc_basic_fifo.v(154): truncated value with size 32 to match size of target (1) -Warning (10230): Verilog HDL assignment warning at mesi_isc_basic_fifo.v(157): truncated value with size 32 to match size of target (1) -Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder -Info (13000): Registers with preset signals will power-up high -Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back -Info (286030): Timing-Driven Synthesis is running -Info (144001): Generated suppressed messages file /home/yair/Work/Projects/mesi_isc/syn/mesi_isc.map.smsg -Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" - Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL -Info (21057): Implemented 1101 device resources after synthesis - the final resource count might be different - Info (21058): Implemented 146 input pins - Info (21059): Implemented 48 output pins - Info (21061): Implemented 907 logic cells -Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings - Info: Peak virtual memory: 370 megabytes - Info: Processing ended: Tue Dec 25 13:54:13 2012 - Info: Elapsed time: 00:00:04 - Info: Total CPU time (on all processors): 00:00:04 - - -+------------------------------------------+ -; Analysis & Synthesis Suppressed Messages ; -+------------------------------------------+ -The suppressed messages can be found in /home/yair/Work/Projects/mesi_isc/syn/mesi_isc.map.smsg. - - Index: syn/mesi_isc.tcl =================================================================== --- syn/mesi_isc.tcl (revision 4) +++ syn/mesi_isc.tcl (nonexistent) @@ -1,67 +0,0 @@ -# Copyright (C) 1991-2012 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. - -# Quartus II: Generate Tcl File for Project -# File: mesi_isc.tcl -# Generated on: Tue Dec 25 13:58:34 2012 - -# Load Quartus II Tcl Project package -package require ::quartus::project - -set need_to_close_project 0 -set make_assignments 1 - -# Check that the right project is open -if {[is_project_open]} { - if {[string compare $quartus(project) "mesi_isc"]} { - puts "Project mesi_isc is not open" - set make_assignments 0 - } -} else { - # Only open if not already open - if {[project_exists mesi_isc]} { - project_open -revision mesi_isc mesi_isc - } else { - project_new -revision mesi_isc mesi_isc - } - set need_to_close_project 1 -} - -# Make assignments -if {$make_assignments} { - set_global_assignment -name FAMILY "Cyclone IV GX" - set_global_assignment -name DEVICE auto - set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.0 SP2" - set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:58:58 NOVEMBER 06, 2012" - set_global_assignment -name LAST_QUARTUS_VERSION "12.0 SP2" - set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_define.v - set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_broad_cntl.v - set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_broad.v - set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_breq_fifos_cntl.v - set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_breq_fifos.v - set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_basic_fifo.v - set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc.v - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top - - # Commit assignments - export_assignments - - # Close project - if {$need_to_close_project} { - project_close - } -} Index: syn/mesi_isc.sta.summary =================================================================== --- syn/mesi_isc.sta.summary (revision 4) +++ syn/mesi_isc.sta.summary (nonexistent) @@ -1,41 +0,0 @@ ------------------------------------------------------------- -TimeQuest Timing Analyzer Summary ------------------------------------------------------------- - -Type : Slow 1200mV 85C Model Setup 'clk' -Slack : -8.340 -TNS : -2724.862 - -Type : Slow 1200mV 85C Model Hold 'clk' -Slack : -0.278 -TNS : -0.443 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'clk' -Slack : -3.000 -TNS : -643.000 - -Type : Slow 1200mV 0C Model Setup 'clk' -Slack : -7.387 -TNS : -2375.975 - -Type : Slow 1200mV 0C Model Hold 'clk' -Slack : -0.237 -TNS : -0.279 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'clk' -Slack : -3.000 -TNS : -643.000 - -Type : Fast 1200mV 0C Model Setup 'clk' -Slack : -4.682 -TNS : -1313.549 - -Type : Fast 1200mV 0C Model Hold 'clk' -Slack : -0.271 -TNS : -3.470 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'clk' -Slack : -3.000 -TNS : -651.247 - ------------------------------------------------------------- Index: syn/mesi_isc.asm.rpt =================================================================== --- syn/mesi_isc.asm.rpt (revision 4) +++ syn/mesi_isc.asm.rpt (nonexistent) @@ -1,116 +0,0 @@ -Assembler report for mesi_isc -Tue Dec 25 13:55:00 2012 -Quartus II 32-bit Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Assembler Summary - 3. Assembler Settings - 4. Assembler Generated Files - 5. Assembler Device Options: mesi_isc.sof - 6. Assembler Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2012 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+---------------------------------------------------------------+ -; Assembler Summary ; -+-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Tue Dec 25 13:55:00 2012 ; -; Revision Name ; mesi_isc ; -; Top-level Entity Name ; mesi_isc ; -; Family ; Cyclone IV GX ; -; Device ; EP4CGX30CF23C6 ; -+-----------------------+---------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Assembler Settings ; -+-----------------------------------------------------------------------------+----------+---------------+ -; Option ; Setting ; Default Value ; -+-----------------------------------------------------------------------------+----------+---------------+ -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Generate compressed bitstreams ; On ; On ; -; Compression mode ; Off ; Off ; -; Clock source for configuration device ; Internal ; Internal ; -; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; -; Divide clock frequency by ; 1 ; 1 ; -; Auto user code ; Off ; Off ; -; Use configuration device ; Off ; Off ; -; Configuration device ; Auto ; Auto ; -; Configuration device auto user code ; Off ; Off ; -; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; -; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; -; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; -; Hexadecimal Output File start address ; 0 ; 0 ; -; Hexadecimal Output File count direction ; Up ; Up ; -; Release clears before tri-states ; Off ; Off ; -; Auto-restart configuration after error ; On ; On ; -; Enable OCT_DONE ; Off ; Off ; -; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; -; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; -+-----------------------------------------------------------------------------+----------+---------------+ - - -+---------------------------+ -; Assembler Generated Files ; -+---------------------------+ -; File Name ; -+---------------------------+ -; mesi_isc.sof ; -+---------------------------+ - - -+----------------------------------------+ -; Assembler Device Options: mesi_isc.sof ; -+----------------+-----------------------+ -; Option ; Setting ; -+----------------+-----------------------+ -; Device ; EP4CGX30CF23C6 ; -; JTAG usercode ; 0xFFFFFFFF ; -; Checksum ; 0x00453FF3 ; -+----------------+-----------------------+ - - -+--------------------+ -; Assembler Messages ; -+--------------------+ -Info: ******************************************************************* -Info: Running Quartus II 32-bit Assembler - Info: Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition - Info: Processing started: Tue Dec 25 13:54:54 2012 -Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off mesi_isc -c mesi_isc -Info (115031): Writing out detailed assembly data for power analysis -Info (115030): Assembler is generating device programming files -Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 375 megabytes - Info: Processing ended: Tue Dec 25 13:55:00 2012 - Info: Elapsed time: 00:00:06 - Info: Total CPU time (on all processors): 00:00:06 - - Index: syn/mesi_isc.done =================================================================== --- syn/mesi_isc.done (revision 4) +++ syn/mesi_isc.done (nonexistent) @@ -1 +0,0 @@ -Tue Dec 25 14:04:07 2012 Index: syn/mesi_isc.map.smsg =================================================================== --- syn/mesi_isc.map.smsg (revision 4) +++ syn/mesi_isc.map.smsg (nonexistent) @@ -1 +0,0 @@ -Warning (10268): Verilog HDL information at mesi_isc_breq_fifos_cntl.v(294): always construct contains both blocking and non-blocking assignments Index: syn/mesi_isc.fit.rpt =================================================================== --- syn/mesi_isc.fit.rpt (revision 4) +++ syn/mesi_isc.fit.rpt (nonexistent) @@ -1,4024 +0,0 @@ -Fitter report for mesi_isc -Tue Dec 25 13:54:52 2012 -Quartus II 32-bit Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Fitter Summary - 3. Fitter Settings - 4. Parallel Compilation - 5. I/O Assignment Warnings - 6. Fitter Netlist Optimizations - 7. Incremental Compilation Preservation Summary - 8. Incremental Compilation Partition Settings - 9. Incremental Compilation Placement Preservation - 10. Pin-Out File - 11. Fitter Resource Usage Summary - 12. Fitter Partition Statistics - 13. Input Pins - 14. Output Pins - 15. Dual Purpose and Dedicated Pins - 16. I/O Bank Usage - 17. All Package Pins - 18. Fitter Resource Utilization by Entity - 19. Delay Chain Summary - 20. Pad To Core Delay Chain Fanout - 21. Control Signals - 22. Global & Other Fast Signals - 23. Non-Global High Fan-Out Signals - 24. Interconnect Usage Summary - 25. LAB Logic Elements - 26. LAB-wide Signals - 27. LAB Signals Sourced - 28. LAB Signals Sourced Out - 29. LAB Distinct Inputs - 30. I/O Rules Summary - 31. I/O Rules Details - 32. I/O Rules Matrix - 33. Fitter Device Options - 34. Operating Settings and Conditions - 35. Estimated Delay Added for Hold Timing Summary - 36. Estimated Delay Added for Hold Timing Details - 37. Fitter Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2012 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+------------------------------------------------------------------------------------+ -; Fitter Summary ; -+------------------------------------+-----------------------------------------------+ -; Fitter Status ; Successful - Tue Dec 25 13:54:52 2012 ; -; Quartus II 32-bit Version ; 12.0 Build 263 08/02/2012 SP 2 SJ Web Edition ; -; Revision Name ; mesi_isc ; -; Top-level Entity Name ; mesi_isc ; -; Family ; Cyclone IV GX ; -; Device ; EP4CGX30CF23C6 ; -; Timing Models ; Final ; -; Total logic elements ; 827 / 29,440 ( 3 % ) ; -; Total combinational functions ; 481 / 29,440 ( 2 % ) ; -; Dedicated logic registers ; 604 / 29,440 ( 2 % ) ; -; Total registers ; 640 ; -; Total pins ; 194 / 307 ( 63 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 / 1,105,920 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 160 ( 0 % ) ; -; Total GXB Receiver Channel PCS ; 0 / 4 ( 0 % ) ; -; Total GXB Receiver Channel PMA ; 0 / 4 ( 0 % ) ; -; Total GXB Transmitter Channel PCS ; 0 / 4 ( 0 % ) ; -; Total GXB Transmitter Channel PMA ; 0 / 4 ( 0 % ) ; -; Total PLLs ; 0 / 6 ( 0 % ) ; -+------------------------------------+-----------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Settings ; -+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ -; Option ; Setting ; Default Value ; -+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ -; Device ; auto ; ; -; Fit Attempts to Skip ; 0 ; 0.0 ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Auto Merge PLLs ; On ; On ; -; Router Timing Optimization Level ; Normal ; Normal ; -; Perform Clocking Topology Analysis During Routing ; Off ; Off ; -; Placement Effort Multiplier ; 1.0 ; 1.0 ; -; Router Effort Multiplier ; 1.0 ; 1.0 ; -; Optimize Hold Timing ; All Paths ; All Paths ; -; Optimize Multi-Corner Timing ; On ; On ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; SSN Optimization ; Off ; Off ; -; Optimize Timing ; Normal compilation ; Normal compilation ; -; Optimize Timing for ECOs ; Off ; Off ; -; Regenerate full fit report during ECO compiles ; Off ; Off ; -; Optimize IOC Register Placement for Timing ; Normal ; Normal ; -; Limit to One Fitting Attempt ; Off ; Off ; -; Final Placement Optimizations ; Automatically ; Automatically ; -; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; -; Fitter Initial Placement Seed ; 1 ; 1 ; -; PCI I/O ; Off ; Off ; -; Weak Pull-Up Resistor ; Off ; Off ; -; Enable Bus-Hold Circuitry ; Off ; Off ; -; Auto Packed Registers ; Auto ; Auto ; -; Auto Delay Chains ; On ; On ; -; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; -; Treat Bidirectional Pin as Output Pin ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; -; Perform Register Duplication for Performance ; Off ; Off ; -; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; -; Perform Register Retiming for Performance ; Off ; Off ; -; Perform Asynchronous Signal Pipelining ; Off ; Off ; -; Fitter Effort ; Auto Fit ; Auto Fit ; -; Physical Synthesis Effort Level ; Normal ; Normal ; -; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; -; Auto Register Duplication ; Auto ; Auto ; -; Auto Global Clock ; On ; On ; -; Auto Global Register Control Signals ; On ; On ; -; Generate GXB Reconfig MIF ; Off ; Off ; -; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; -; Synchronizer Identification ; Off ; Off ; -; Enable Beneficial Skew Optimization ; On ; On ; -; Optimize Design for Metastability ; On ; On ; -; Active Serial clock source ; FREQ_40MHz ; FREQ_40MHz ; -; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; -; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; -+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ - - -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ - - -+--------------------------------------------------+ -; I/O Assignment Warnings ; -+------------------+-------------------------------+ -; Pin Name ; Reason ; -+------------------+-------------------------------+ -; cbus_addr_o[0] ; Incomplete set of assignments ; -; cbus_addr_o[1] ; Incomplete set of assignments ; -; cbus_addr_o[2] ; Incomplete set of assignments ; -; cbus_addr_o[3] ; Incomplete set of assignments ; -; cbus_addr_o[4] ; Incomplete set of assignments ; -; cbus_addr_o[5] ; Incomplete set of assignments ; -; cbus_addr_o[6] ; Incomplete set of assignments ; -; cbus_addr_o[7] ; Incomplete set of assignments ; -; cbus_addr_o[8] ; Incomplete set of assignments ; -; cbus_addr_o[9] ; Incomplete set of assignments ; -; cbus_addr_o[10] ; Incomplete set of assignments ; -; cbus_addr_o[11] ; Incomplete set of assignments ; -; cbus_addr_o[12] ; Incomplete set of assignments ; -; cbus_addr_o[13] ; Incomplete set of assignments ; -; cbus_addr_o[14] ; Incomplete set of assignments ; -; cbus_addr_o[15] ; Incomplete set of assignments ; -; cbus_addr_o[16] ; Incomplete set of assignments ; -; cbus_addr_o[17] ; Incomplete set of assignments ; -; cbus_addr_o[18] ; Incomplete set of assignments ; -; cbus_addr_o[19] ; Incomplete set of assignments ; -; cbus_addr_o[20] ; Incomplete set of assignments ; -; cbus_addr_o[21] ; Incomplete set of assignments ; -; cbus_addr_o[22] ; Incomplete set of assignments ; -; cbus_addr_o[23] ; Incomplete set of assignments ; -; cbus_addr_o[24] ; Incomplete set of assignments ; -; cbus_addr_o[25] ; Incomplete set of assignments ; -; cbus_addr_o[26] ; Incomplete set of assignments ; -; cbus_addr_o[27] ; Incomplete set of assignments ; -; cbus_addr_o[28] ; Incomplete set of assignments ; -; cbus_addr_o[29] ; Incomplete set of assignments ; -; cbus_addr_o[30] ; Incomplete set of assignments ; -; cbus_addr_o[31] ; Incomplete set of assignments ; -; cbus_cmd3_o[0] ; Incomplete set of assignments ; -; cbus_cmd3_o[1] ; Incomplete set of assignments ; -; cbus_cmd3_o[2] ; Incomplete set of assignments ; -; cbus_cmd2_o[0] ; Incomplete set of assignments ; -; cbus_cmd2_o[1] ; Incomplete set of assignments ; -; cbus_cmd2_o[2] ; Incomplete set of assignments ; -; cbus_cmd1_o[0] ; Incomplete set of assignments ; -; cbus_cmd1_o[1] ; Incomplete set of assignments ; -; cbus_cmd1_o[2] ; Incomplete set of assignments ; -; cbus_cmd0_o[0] ; Incomplete set of assignments ; -; cbus_cmd0_o[1] ; Incomplete set of assignments ; -; cbus_cmd0_o[2] ; Incomplete set of assignments ; -; mbus_ack3_o ; Incomplete set of assignments ; -; mbus_ack2_o ; Incomplete set of assignments ; -; mbus_ack1_o ; Incomplete set of assignments ; -; mbus_ack0_o ; Incomplete set of assignments ; -; clk ; Incomplete set of assignments ; -; rst ; Incomplete set of assignments ; -; cbus_ack3_i ; Incomplete set of assignments ; -; cbus_ack2_i ; Incomplete set of assignments ; -; cbus_ack1_i ; Incomplete set of assignments ; -; cbus_ack0_i ; Incomplete set of assignments ; -; mbus_cmd3_i[0] ; Incomplete set of assignments ; -; mbus_cmd3_i[2] ; Incomplete set of assignments ; -; mbus_cmd3_i[1] ; Incomplete set of assignments ; -; mbus_cmd2_i[0] ; Incomplete set of assignments ; -; mbus_cmd2_i[1] ; Incomplete set of assignments ; -; mbus_cmd2_i[2] ; Incomplete set of assignments ; -; mbus_cmd1_i[2] ; Incomplete set of assignments ; -; mbus_cmd1_i[0] ; Incomplete set of assignments ; -; mbus_cmd1_i[1] ; Incomplete set of assignments ; -; mbus_cmd0_i[0] ; Incomplete set of assignments ; -; mbus_cmd0_i[1] ; Incomplete set of assignments ; -; mbus_cmd0_i[2] ; Incomplete set of assignments ; -; mbus_addr2_i[0] ; Incomplete set of assignments ; -; mbus_addr3_i[0] ; Incomplete set of assignments ; -; mbus_addr0_i[0] ; Incomplete set of assignments ; -; mbus_addr1_i[0] ; Incomplete set of assignments ; -; mbus_addr2_i[1] ; Incomplete set of assignments ; -; mbus_addr3_i[1] ; Incomplete set of assignments ; -; mbus_addr0_i[1] ; Incomplete set of assignments ; -; mbus_addr1_i[1] ; Incomplete set of assignments ; -; mbus_addr2_i[2] ; Incomplete set of assignments ; -; mbus_addr3_i[2] ; Incomplete set of assignments ; -; mbus_addr0_i[2] ; Incomplete set of assignments ; -; mbus_addr1_i[2] ; Incomplete set of assignments ; -; mbus_addr2_i[3] ; Incomplete set of assignments ; -; mbus_addr3_i[3] ; Incomplete set of assignments ; -; mbus_addr0_i[3] ; Incomplete set of assignments ; -; mbus_addr1_i[3] ; Incomplete set of assignments ; -; mbus_addr2_i[4] ; Incomplete set of assignments ; -; mbus_addr3_i[4] ; Incomplete set of assignments ; -; mbus_addr0_i[4] ; Incomplete set of assignments ; -; mbus_addr1_i[4] ; Incomplete set of assignments ; -; mbus_addr2_i[5] ; Incomplete set of assignments ; -; mbus_addr3_i[5] ; Incomplete set of assignments ; -; mbus_addr0_i[5] ; Incomplete set of assignments ; -; mbus_addr1_i[5] ; Incomplete set of assignments ; -; mbus_addr2_i[6] ; Incomplete set of assignments ; -; mbus_addr3_i[6] ; Incomplete set of assignments ; -; mbus_addr0_i[6] ; Incomplete set of assignments ; -; mbus_addr1_i[6] ; Incomplete set of assignments ; -; mbus_addr2_i[7] ; Incomplete set of assignments ; -; mbus_addr3_i[7] ; Incomplete set of assignments ; -; mbus_addr0_i[7] ; Incomplete set of assignments ; -; mbus_addr1_i[7] ; Incomplete set of assignments ; -; mbus_addr2_i[8] ; Incomplete set of assignments ; -; mbus_addr3_i[8] ; Incomplete set of assignments ; -; mbus_addr0_i[8] ; Incomplete set of assignments ; -; mbus_addr1_i[8] ; Incomplete set of assignments ; -; mbus_addr2_i[9] ; Incomplete set of assignments ; -; mbus_addr3_i[9] ; Incomplete set of assignments ; -; mbus_addr0_i[9] ; Incomplete set of assignments ; -; mbus_addr1_i[9] ; Incomplete set of assignments ; -; mbus_addr2_i[10] ; Incomplete set of assignments ; -; mbus_addr3_i[10] ; Incomplete set of assignments ; -; mbus_addr0_i[10] ; Incomplete set of assignments ; -; mbus_addr1_i[10] ; Incomplete set of assignments ; -; mbus_addr2_i[11] ; Incomplete set of assignments ; -; mbus_addr3_i[11] ; Incomplete set of assignments ; -; mbus_addr0_i[11] ; Incomplete set of assignments ; -; mbus_addr1_i[11] ; Incomplete set of assignments ; -; mbus_addr2_i[12] ; Incomplete set of assignments ; -; mbus_addr3_i[12] ; Incomplete set of assignments ; -; mbus_addr0_i[12] ; Incomplete set of assignments ; -; mbus_addr1_i[12] ; Incomplete set of assignments ; -; mbus_addr2_i[13] ; Incomplete set of assignments ; -; mbus_addr3_i[13] ; Incomplete set of assignments ; -; mbus_addr0_i[13] ; Incomplete set of assignments ; -; mbus_addr1_i[13] ; Incomplete set of assignments ; -; mbus_addr2_i[14] ; Incomplete set of assignments ; -; mbus_addr3_i[14] ; Incomplete set of assignments ; -; mbus_addr0_i[14] ; Incomplete set of assignments ; -; mbus_addr1_i[14] ; Incomplete set of assignments ; -; mbus_addr2_i[15] ; Incomplete set of assignments ; -; mbus_addr3_i[15] ; Incomplete set of assignments ; -; mbus_addr0_i[15] ; Incomplete set of assignments ; -; mbus_addr1_i[15] ; Incomplete set of assignments ; -; mbus_addr2_i[16] ; Incomplete set of assignments ; -; mbus_addr3_i[16] ; Incomplete set of assignments ; -; mbus_addr0_i[16] ; Incomplete set of assignments ; -; mbus_addr1_i[16] ; Incomplete set of assignments ; -; mbus_addr2_i[17] ; Incomplete set of assignments ; -; mbus_addr3_i[17] ; Incomplete set of assignments ; -; mbus_addr0_i[17] ; Incomplete set of assignments ; -; mbus_addr1_i[17] ; Incomplete set of assignments ; -; mbus_addr2_i[18] ; Incomplete set of assignments ; -; mbus_addr3_i[18] ; Incomplete set of assignments ; -; mbus_addr0_i[18] ; Incomplete set of assignments ; -; mbus_addr1_i[18] ; Incomplete set of assignments ; -; mbus_addr2_i[19] ; Incomplete set of assignments ; -; mbus_addr3_i[19] ; Incomplete set of assignments ; -; mbus_addr0_i[19] ; Incomplete set of assignments ; -; mbus_addr1_i[19] ; Incomplete set of assignments ; -; mbus_addr2_i[20] ; Incomplete set of assignments ; -; mbus_addr3_i[20] ; Incomplete set of assignments ; -; mbus_addr0_i[20] ; Incomplete set of assignments ; -; mbus_addr1_i[20] ; Incomplete set of assignments ; -; mbus_addr2_i[21] ; Incomplete set of assignments ; -; mbus_addr3_i[21] ; Incomplete set of assignments ; -; mbus_addr0_i[21] ; Incomplete set of assignments ; -; mbus_addr1_i[21] ; Incomplete set of assignments ; -; mbus_addr2_i[22] ; Incomplete set of assignments ; -; mbus_addr3_i[22] ; Incomplete set of assignments ; -; mbus_addr0_i[22] ; Incomplete set of assignments ; -; mbus_addr1_i[22] ; Incomplete set of assignments ; -; mbus_addr2_i[23] ; Incomplete set of assignments ; -; mbus_addr3_i[23] ; Incomplete set of assignments ; -; mbus_addr0_i[23] ; Incomplete set of assignments ; -; mbus_addr1_i[23] ; Incomplete set of assignments ; -; mbus_addr2_i[24] ; Incomplete set of assignments ; -; mbus_addr3_i[24] ; Incomplete set of assignments ; -; mbus_addr0_i[24] ; Incomplete set of assignments ; -; mbus_addr1_i[24] ; Incomplete set of assignments ; -; mbus_addr2_i[25] ; Incomplete set of assignments ; -; mbus_addr3_i[25] ; Incomplete set of assignments ; -; mbus_addr0_i[25] ; Incomplete set of assignments ; -; mbus_addr1_i[25] ; Incomplete set of assignments ; -; mbus_addr2_i[26] ; Incomplete set of assignments ; -; mbus_addr3_i[26] ; Incomplete set of assignments ; -; mbus_addr0_i[26] ; Incomplete set of assignments ; -; mbus_addr1_i[26] ; Incomplete set of assignments ; -; mbus_addr2_i[27] ; Incomplete set of assignments ; -; mbus_addr3_i[27] ; Incomplete set of assignments ; -; mbus_addr0_i[27] ; Incomplete set of assignments ; -; mbus_addr1_i[27] ; Incomplete set of assignments ; -; mbus_addr2_i[28] ; Incomplete set of assignments ; -; mbus_addr3_i[28] ; Incomplete set of assignments ; -; mbus_addr0_i[28] ; Incomplete set of assignments ; -; mbus_addr1_i[28] ; Incomplete set of assignments ; -; mbus_addr2_i[29] ; Incomplete set of assignments ; -; mbus_addr3_i[29] ; Incomplete set of assignments ; -; mbus_addr0_i[29] ; Incomplete set of assignments ; -; mbus_addr1_i[29] ; Incomplete set of assignments ; -; mbus_addr2_i[30] ; Incomplete set of assignments ; -; mbus_addr3_i[30] ; Incomplete set of assignments ; -; mbus_addr0_i[30] ; Incomplete set of assignments ; -; mbus_addr1_i[30] ; Incomplete set of assignments ; -; mbus_addr2_i[31] ; Incomplete set of assignments ; -; mbus_addr3_i[31] ; Incomplete set of assignments ; -; mbus_addr0_i[31] ; Incomplete set of assignments ; -; mbus_addr1_i[31] ; Incomplete set of assignments ; -+------------------+-------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Netlist Optimizations ; -+-------------------------------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+--------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ -; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; -+-------------------------------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+--------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[0] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[0]~_Duplicate_1 ; Q ; ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mbus_ack0_o~output ; I ; ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[1] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[1]~_Duplicate_1 ; Q ; ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mbus_ack1_o~output ; I ; ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[2] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[2]~_Duplicate_1 ; Q ; ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mbus_ack2_o~output ; I ; ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[3] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[3]~_Duplicate_1 ; Q ; ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mbus_ack3_o~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[9] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[0]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[10] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[1]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[11] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[2]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[12] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[3]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[13] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[4]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[14] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[5]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[15] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[6]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[16] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[7]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[17] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[8]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[18] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[9]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[19] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[10]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[20] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[11]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[21] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[12]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[22] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[13]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[23] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[14]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[24] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[15]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[25] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[16]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[26] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[17]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[27] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[18]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[28] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[19]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[29] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[20]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[30] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[21]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[31] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[22]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[32] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[23]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[33] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[24]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[34] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[25]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[35] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[26]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[36] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[27]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[37] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[28]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[38] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[29]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[39] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[30]~output ; I ; ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[40] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; cbus_addr_o[31]~output ; I ; ; -+-------------------------------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+--------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ - - -+----------------------------------------------+ -; Incremental Compilation Preservation Summary ; -+---------------------+------------------------+ -; Type ; Value ; -+---------------------+------------------------+ -; Placement (by node) ; ; -; -- Requested ; 0 / 1518 ( 0.00 % ) ; -; -- Achieved ; 0 / 1518 ( 0.00 % ) ; -; ; ; -; Routing (by net) ; ; -; -- Requested ; 0 / 0 ( 0.00 % ) ; -; -- Achieved ; 0 / 0 ( 0.00 % ) ; -+---------------------+------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Incremental Compilation Partition Settings ; -+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ -; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; -+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ -; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; -; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; -+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ - - -+------------------------------------------------------------------------------------------------------------+ -; Incremental Compilation Placement Preservation ; -+--------------------------------+---------+-------------------+-------------------------+-------------------+ -; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; -+--------------------------------+---------+-------------------+-------------------------+-------------------+ -; Top ; 1508 ; 0 ; N/A ; Source File ; -; hard_block:auto_generated_inst ; 10 ; 0 ; N/A ; Source File ; -+--------------------------------+---------+-------------------+-------------------------+-------------------+ - - -+--------------+ -; Pin-Out File ; -+--------------+ -The pin-out file can be found in /home/yair/Work/Projects/mesi_isc/syn/mesi_isc.pin. - - -+-------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Usage Summary ; -+---------------------------------------------+---------------------------------------------------------------------------+ -; Resource ; Usage ; -+---------------------------------------------+---------------------------------------------------------------------------+ -; Total logic elements ; 827 / 29,440 ( 3 % ) ; -; -- Combinational with no register ; 223 ; -; -- Register only ; 346 ; -; -- Combinational with a register ; 258 ; -; ; ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 254 ; -; -- 3 input functions ; 151 ; -; -- <=2 input functions ; 76 ; -; -- Register only ; 346 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 481 ; -; -- arithmetic mode ; 0 ; -; ; ; -; Total registers* ; 640 / 30,876 ( 2 % ) ; -; -- Dedicated logic registers ; 604 / 29,440 ( 2 % ) ; -; -- I/O registers ; 36 / 1,436 ( 3 % ) ; -; ; ; -; Total LABs: partially or completely used ; 145 / 1,840 ( 8 % ) ; -; User inserted logic elements ; 0 ; -; Virtual pins ; 0 ; -; I/O pins ; 194 / 307 ( 63 % ) ; -; -- Clock pins ; 4 / 8 ( 50 % ) ; -; -- Dedicated input pins ; 0 / 17 ( 0 % ) ; -; ; ; -; Global signals ; 2 ; -; M9Ks ; 0 / 120 ( 0 % ) ; -; Total block memory bits ; 0 / 1,105,920 ( 0 % ) ; -; Total block memory implementation bits ; 0 / 1,105,920 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 160 ( 0 % ) ; -; PLLs ; 0 / 6 ( 0 % ) ; -; Global clocks ; 2 / 30 ( 7 % ) ; -; JTAGs ; 0 / 1 ( 0 % ) ; -; CRC blocks ; 0 / 1 ( 0 % ) ; -; ASMI blocks ; 0 / 1 ( 0 % ) ; -; GXB Receiver channel PCSs ; 0 / 4 ( 0 % ) ; -; GXB Receiver channel PMAs ; 0 / 4 ( 0 % ) ; -; GXB Transmitter channel PCSs ; 0 / 4 ( 0 % ) ; -; GXB Transmitter channel PMAs ; 0 / 4 ( 0 % ) ; -; Impedance control blocks ; 0 / 3 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 1% / 1% / 1% ; -; Peak interconnect usage (total/H/V) ; 11% / 9% / 14% ; -; Maximum fan-out node ; clk~inputclkctrl ; -; Maximum fan-out ; 640 ; -; Highest non-global fan-out signal ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[21]~0 ; -; Highest non-global fan-out ; 54 ; -; Total fan-out ; 4809 ; -; Average fan-out ; 2.61 ; -+---------------------------------------------+---------------------------------------------------------------------------+ -* Register count does not include registers inside RAM blocks or DSP blocks. - - - -+----------------------------------------------------------------------------------------------------+ -; Fitter Partition Statistics ; -+---------------------------------------------+---------------------+--------------------------------+ -; Statistic ; Top ; hard_block:auto_generated_inst ; -+---------------------------------------------+---------------------+--------------------------------+ -; Difficulty Clustering Region ; Low ; Low ; -; ; ; ; -; Total logic elements ; 827 / 29440 ( 3 % ) ; 0 / 29440 ( 0 % ) ; -; -- Combinational with no register ; 223 ; 0 ; -; -- Register only ; 346 ; 0 ; -; -- Combinational with a register ; 258 ; 0 ; -; ; ; ; -; Logic element usage by number of LUT inputs ; ; ; -; -- 4 input functions ; 254 ; 0 ; -; -- 3 input functions ; 151 ; 0 ; -; -- <=2 input functions ; 76 ; 0 ; -; -- Register only ; 346 ; 0 ; -; ; ; ; -; Logic elements by mode ; ; ; -; -- normal mode ; 481 ; 0 ; -; -- arithmetic mode ; 0 ; 0 ; -; ; ; ; -; Total registers ; 640 ; 0 ; -; -- Dedicated logic registers ; 604 / 29440 ( 2 % ) ; 0 / 29440 ( 0 % ) ; -; -- I/O registers ; 72 ; 0 ; -; ; ; ; -; Total LABs: partially or completely used ; 145 / 1840 ( 8 % ) ; 0 / 1840 ( 0 % ) ; -; ; ; ; -; Virtual pins ; 0 ; 0 ; -; I/O pins ; 194 ; 0 ; -; Embedded Multiplier 9-bit elements ; 0 / 160 ( 0 % ) ; 0 / 160 ( 0 % ) ; -; Total memory bits ; 0 ; 0 ; -; Total RAM block bits ; 0 ; 0 ; -; Clock control block ; 2 / 38 ( 5 % ) ; 0 / 38 ( 0 % ) ; -; Double Data Rate I/O output circuitry ; 36 / 291 ( 12 % ) ; 0 / 291 ( 0 % ) ; -; ; ; ; -; Connections ; ; ; -; -- Input Connections ; 0 ; 0 ; -; -- Registered Input Connections ; 0 ; 0 ; -; -- Output Connections ; 0 ; 0 ; -; -- Registered Output Connections ; 0 ; 0 ; -; ; ; ; -; Internal Connections ; ; ; -; -- Total Connections ; 4804 ; 5 ; -; -- Registered Connections ; 1032 ; 0 ; -; ; ; ; -; External Connections ; ; ; -; -- Top ; 0 ; 0 ; -; -- hard_block:auto_generated_inst ; 0 ; 0 ; -; ; ; ; -; Partition Interface ; ; ; -; -- Input Ports ; 146 ; 0 ; -; -- Output Ports ; 48 ; 0 ; -; -- Bidir Ports ; 0 ; 0 ; -; ; ; ; -; Registered Ports ; ; ; -; -- Registered Input Ports ; 0 ; 0 ; -; -- Registered Output Ports ; 0 ; 0 ; -; ; ; ; -; Port Connectivity ; ; ; -; -- Input Ports driven by GND ; 0 ; 0 ; -; -- Output Ports driven by GND ; 0 ; 0 ; -; -- Input Ports driven by VCC ; 0 ; 0 ; -; -- Output Ports driven by VCC ; 0 ; 0 ; -; -- Input Ports with no Source ; 0 ; 0 ; -; -- Output Ports with no Source ; 0 ; 0 ; -; -- Input Ports with no Fanout ; 0 ; 0 ; -; -- Output Ports with no Fanout ; 0 ; 0 ; -+---------------------------------------------+---------------------+--------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Input Pins ; -+------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; -+------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+ -; cbus_ack0_i ; W18 ; 4 ; 68 ; 0 ; 14 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; cbus_ack1_i ; J19 ; 6 ; 81 ; 42 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; cbus_ack2_i ; AB12 ; 4 ; 38 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; cbus_ack3_i ; AA12 ; 4 ; 38 ; 0 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; clk ; N11 ; 3A ; 38 ; 0 ; 14 ; 640 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[0] ; U12 ; 3 ; 31 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[10] ; Y16 ; 4 ; 54 ; 0 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[11] ; L15 ; 5 ; 81 ; 14 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[12] ; W15 ; 4 ; 49 ; 0 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[13] ; R20 ; 5 ; 81 ; 10 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[14] ; Y11 ; 3 ; 31 ; 0 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[15] ; AA9 ; 3 ; 26 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[16] ; Y8 ; 3 ; 26 ; 0 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[17] ; M22 ; 5 ; 81 ; 34 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[18] ; Y9 ; 3 ; 26 ; 0 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[19] ; AB11 ; 3 ; 33 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[1] ; W10 ; 3 ; 22 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[20] ; Y10 ; 3 ; 31 ; 0 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[21] ; AB18 ; 4 ; 56 ; 0 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[22] ; Y14 ; 4 ; 47 ; 0 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[23] ; W12 ; 3 ; 33 ; 0 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[24] ; W22 ; 5 ; 81 ; 3 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[25] ; AB5 ; 3 ; 19 ; 0 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[26] ; AB7 ; 3 ; 22 ; 0 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[27] ; R13 ; 4 ; 40 ; 0 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[28] ; AB6 ; 3 ; 19 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[29] ; W17 ; 4 ; 56 ; 0 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[2] ; AB9 ; 3 ; 29 ; 0 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[30] ; AA7 ; 3 ; 22 ; 0 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[31] ; V13 ; 4 ; 44 ; 0 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[3] ; AB8 ; 3 ; 29 ; 0 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[4] ; AA10 ; 3 ; 31 ; 0 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[5] ; W9 ; 3 ; 24 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[6] ; AB10 ; 3 ; 33 ; 0 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[7] ; W11 ; 3 ; 29 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[8] ; U14 ; 4 ; 49 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr0_i[9] ; Y12 ; 3 ; 33 ; 0 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[0] ; G18 ; 6 ; 81 ; 63 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[10] ; P22 ; 5 ; 81 ; 16 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[11] ; V21 ; 5 ; 81 ; 6 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[12] ; N20 ; 5 ; 81 ; 20 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[13] ; A18 ; 7 ; 65 ; 67 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[14] ; D19 ; 6 ; 81 ; 59 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[15] ; AA19 ; 4 ; 58 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[16] ; F17 ; 7 ; 70 ; 67 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[17] ; M21 ; 5 ; 81 ; 34 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[18] ; L22 ; 6 ; 81 ; 34 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[19] ; B21 ; 6 ; 81 ; 59 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[1] ; T20 ; 5 ; 81 ; 8 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[20] ; K17 ; 6 ; 81 ; 62 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[21] ; J16 ; 6 ; 81 ; 62 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[22] ; C19 ; 6 ; 81 ; 61 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[23] ; F20 ; 6 ; 81 ; 50 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[24] ; C20 ; 6 ; 81 ; 61 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[25] ; R16 ; 5 ; 81 ; 2 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[26] ; T16 ; 4 ; 63 ; 0 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[27] ; M17 ; 5 ; 81 ; 17 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[28] ; AB21 ; 4 ; 65 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[29] ; P13 ; 5 ; 81 ; 6 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[2] ; J15 ; 6 ; 81 ; 41 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[30] ; L14 ; 5 ; 81 ; 16 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[31] ; V22 ; 5 ; 81 ; 9 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[3] ; V20 ; 5 ; 81 ; 7 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[4] ; L13 ; 5 ; 81 ; 19 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[5] ; H21 ; 6 ; 81 ; 47 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[6] ; M15 ; 5 ; 81 ; 12 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[7] ; P20 ; 5 ; 81 ; 11 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[8] ; A20 ; 6 ; 81 ; 61 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr1_i[9] ; E20 ; 6 ; 81 ; 49 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[0] ; A22 ; 6 ; 81 ; 56 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[10] ; C12 ; 7 ; 54 ; 67 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[11] ; H17 ; 6 ; 81 ; 55 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[12] ; A15 ; 7 ; 58 ; 67 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[13] ; B19 ; 6 ; 81 ; 62 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[14] ; B22 ; 6 ; 81 ; 55 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[15] ; A14 ; 7 ; 54 ; 67 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[16] ; D22 ; 6 ; 81 ; 53 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[17] ; N21 ; 5 ; 81 ; 23 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[18] ; N17 ; 5 ; 81 ; 19 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[19] ; L21 ; 6 ; 81 ; 34 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[1] ; H13 ; 7 ; 44 ; 67 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[20] ; C10 ; 7 ; 47 ; 67 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[21] ; W20 ; 5 ; 81 ; 5 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[22] ; D20 ; 6 ; 81 ; 58 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[23] ; N15 ; 5 ; 81 ; 4 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[24] ; T21 ; 5 ; 81 ; 11 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[25] ; B16 ; 7 ; 63 ; 67 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[26] ; R21 ; 5 ; 81 ; 10 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[27] ; P14 ; 5 ; 81 ; 6 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[28] ; N22 ; 5 ; 81 ; 21 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[29] ; R19 ; 5 ; 81 ; 8 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[2] ; H14 ; 7 ; 49 ; 67 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[30] ; AA21 ; 4 ; 65 ; 0 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[31] ; U22 ; 5 ; 81 ; 9 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[3] ; J12 ; 7 ; 49 ; 67 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[4] ; K12 ; 7 ; 49 ; 67 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[5] ; D13 ; 7 ; 54 ; 67 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[6] ; B20 ; 6 ; 81 ; 59 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[7] ; A11 ; 7 ; 44 ; 67 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[8] ; D14 ; 7 ; 56 ; 67 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr2_i[9] ; C13 ; 7 ; 54 ; 67 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[0] ; C11 ; 7 ; 47 ; 67 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[10] ; N14 ; 5 ; 81 ; 12 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[11] ; U18 ; 5 ; 81 ; 3 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[12] ; D16 ; 7 ; 63 ; 67 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[13] ; G15 ; 7 ; 52 ; 67 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[14] ; R22 ; 5 ; 81 ; 17 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[15] ; A17 ; 7 ; 58 ; 67 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[16] ; W14 ; 4 ; 44 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[17] ; AA13 ; 4 ; 42 ; 0 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[18] ; A13 ; 7 ; 56 ; 67 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[19] ; Y17 ; 4 ; 56 ; 0 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[1] ; G14 ; 7 ; 52 ; 67 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[20] ; R17 ; 5 ; 81 ; 2 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[21] ; E22 ; 6 ; 81 ; 52 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[22] ; U20 ; 5 ; 81 ; 7 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[23] ; AA18 ; 4 ; 58 ; 0 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[24] ; AB13 ; 4 ; 42 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[25] ; T15 ; 4 ; 58 ; 0 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[26] ; M14 ; 5 ; 81 ; 14 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[27] ; T22 ; 5 ; 81 ; 10 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[28] ; D15 ; 7 ; 58 ; 67 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[29] ; T18 ; 5 ; 81 ; 2 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[2] ; T14 ; 4 ; 49 ; 0 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[30] ; R15 ; 4 ; 58 ; 0 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[31] ; AB16 ; 4 ; 54 ; 0 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[3] ; Y22 ; 5 ; 81 ; 4 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[4] ; P15 ; 5 ; 81 ; 4 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[5] ; N13 ; 5 ; 81 ; 14 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[6] ; AB14 ; 4 ; 44 ; 0 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[7] ; W21 ; 5 ; 81 ; 4 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[8] ; T19 ; 5 ; 81 ; 7 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_addr3_i[9] ; F22 ; 6 ; 81 ; 50 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_cmd0_i[0] ; AA16 ; 4 ; 54 ; 0 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_cmd0_i[1] ; U15 ; 4 ; 52 ; 0 ; 14 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_cmd0_i[2] ; W16 ; 4 ; 52 ; 0 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_cmd1_i[0] ; AB22 ; 4 ; 70 ; 0 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_cmd1_i[1] ; W19 ; 4 ; 70 ; 0 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_cmd1_i[2] ; Y20 ; 4 ; 70 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_cmd2_i[0] ; G21 ; 6 ; 81 ; 49 ; 14 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_cmd2_i[1] ; K19 ; 6 ; 81 ; 46 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_cmd2_i[2] ; K20 ; 6 ; 81 ; 46 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_cmd3_i[0] ; L16 ; 5 ; 81 ; 25 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_cmd3_i[1] ; N19 ; 5 ; 81 ; 21 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; mbus_cmd3_i[2] ; M20 ; 5 ; 81 ; 25 ; 14 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -; rst ; M11 ; 3A ; 38 ; 0 ; 21 ; 640 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; -+------------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Output Pins ; -+-----------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; -+-----------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ -; cbus_addr_o[0] ; AB20 ; 4 ; 65 ; 0 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[10] ; M19 ; 5 ; 81 ; 26 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[11] ; W13 ; 4 ; 40 ; 0 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[12] ; A21 ; 6 ; 81 ; 58 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[13] ; D17 ; 7 ; 65 ; 67 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[14] ; H20 ; 6 ; 81 ; 47 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[15] ; D21 ; 6 ; 81 ; 53 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[16] ; M13 ; 5 ; 81 ; 20 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[17] ; R14 ; 4 ; 47 ; 0 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[18] ; J14 ; 7 ; 49 ; 67 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[19] ; Y13 ; 4 ; 42 ; 0 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[1] ; M18 ; 5 ; 81 ; 26 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[20] ; B13 ; 7 ; 52 ; 67 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[21] ; C14 ; 7 ; 56 ; 67 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[22] ; AB19 ; 4 ; 61 ; 0 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[23] ; AB17 ; 4 ; 54 ; 0 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[24] ; C15 ; 7 ; 58 ; 67 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[25] ; T17 ; 5 ; 81 ; 2 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[26] ; B15 ; 7 ; 56 ; 67 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[27] ; AA20 ; 4 ; 63 ; 0 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[28] ; AB15 ; 4 ; 44 ; 0 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[29] ; A19 ; 7 ; 65 ; 67 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[2] ; B12 ; 7 ; 52 ; 67 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[30] ; J22 ; 6 ; 81 ; 44 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[31] ; T13 ; 4 ; 40 ; 0 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[3] ; Y15 ; 4 ; 49 ; 0 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[4] ; C16 ; 7 ; 61 ; 67 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[5] ; E17 ; 7 ; 63 ; 67 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[6] ; A16 ; 7 ; 61 ; 67 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[7] ; H22 ; 6 ; 81 ; 43 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[8] ; G20 ; 6 ; 81 ; 49 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_addr_o[9] ; Y18 ; 4 ; 56 ; 0 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_cmd0_o[0] ; C18 ; 7 ; 70 ; 67 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_cmd0_o[1] ; E21 ; 6 ; 81 ; 52 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_cmd0_o[2] ; L20 ; 6 ; 81 ; 39 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_cmd1_o[0] ; F16 ; 7 ; 70 ; 67 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_cmd1_o[1] ; G22 ; 6 ; 81 ; 52 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_cmd1_o[2] ; J21 ; 6 ; 81 ; 44 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_cmd2_o[0] ; C22 ; 6 ; 81 ; 56 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_cmd2_o[1] ; C17 ; 7 ; 70 ; 67 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_cmd2_o[2] ; AA22 ; 4 ; 68 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_cmd3_o[0] ; B18 ; 7 ; 68 ; 67 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_cmd3_o[1] ; J20 ; 6 ; 81 ; 42 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; cbus_cmd3_o[2] ; L19 ; 6 ; 81 ; 39 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; mbus_ack0_o ; AA15 ; 4 ; 52 ; 0 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; mbus_ack1_o ; Y19 ; 4 ; 68 ; 0 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; mbus_ack2_o ; K22 ; 6 ; 81 ; 46 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; mbus_ack3_o ; M16 ; 5 ; 81 ; 25 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -+-----------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ - - -+---------------------------------------------------------------------------------------------------------------+ -; Dual Purpose and Dedicated Pins ; -+----------+-----------------------+--------------------------+---------------------+---------------------------+ -; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; -+----------+-----------------------+--------------------------+---------------------+---------------------------+ -; P4 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; -; R5 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; -; P5 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; -; T6 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; -; U5 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; -; R8 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; -; AB3 ; DIFFIO_B3n, NCEO ; Use as programming pin ; ~ALTERA_NCEO~ ; Dual Purpose Pin ; -; P14 ; DIFFIO_R44n, DEV_OE ; Use as regular IO ; mbus_addr2_i[27] ; Dual Purpose Pin ; -; P13 ; DIFFIO_R44p, DEV_CLRn ; Use as regular IO ; mbus_addr1_i[29] ; Dual Purpose Pin ; -; K4 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; -; D1 ; DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; -; J4 ; NCSO ; As input tri-stated ; ~ALTERA_NCSO~ ; Dual Purpose Pin ; -; D3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; -; H4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; -; D2 ; nCE ; - ; - ; Dedicated Programming Pin ; -+----------+-----------------------+--------------------------+---------------------+---------------------------+ - - -+--------------------------------------------------------------------------------+ -; I/O Bank Usage ; -+----------+-------------------+---------------+--------------+------------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCCLKIN Voltage ; -+----------+-------------------+---------------+--------------+------------------+ -; QL1 ; 0 / 0 ( -- ) ; -- ; -- ; -- ; -; QL0 ; 0 / 16 ( 0 % ) ; -- ; -- ; -- ; -; 3 ; 21 / 46 ( 46 % ) ; 2.5V ; -- ; -- ; -; 3B ; 0 / 4 ( 0 % ) ; -- ; -- ; 2.5V ; -; 3A ; 2 / 2 ( 100 % ) ; -- ; -- ; 2.5V ; -; 4 ; 45 / 45 ( 100 % ) ; 2.5V ; -- ; -- ; -; 5 ; 49 / 49 ( 100 % ) ; 2.5V ; -- ; -- ; -; 6 ; 41 / 49 ( 84 % ) ; 2.5V ; -- ; -- ; -; 7 ; 37 / 46 ( 80 % ) ; 2.5V ; -- ; -- ; -; 8A ; 0 / 2 ( 0 % ) ; -- ; -- ; 2.5V ; -; 8 ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; -- ; -; 8B ; 0 / 0 ( -- ) ; -- ; -- ; -- ; -; 9 ; 4 / 4 ( 100 % ) ; 2.5V ; -- ; -- ; -+----------+-------------------+---------------+--------------+------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; All Package Pins ; -+----------+------------+----------+-------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; -+----------+------------+----------+-------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; A1 ; 306 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A2 ; 300 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A3 ; 301 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A4 ; 297 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A5 ; 298 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A6 ; 295 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A7 ; 296 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A8 ; 293 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A9 ; 289 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; A10 ; 285 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A11 ; 283 ; 7 ; mbus_addr2_i[7] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; A12 ; 284 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A13 ; 265 ; 7 ; mbus_addr3_i[18] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; A14 ; 266 ; 7 ; mbus_addr2_i[15] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; A15 ; 261 ; 7 ; mbus_addr2_i[12] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; A16 ; 257 ; 7 ; cbus_addr_o[6] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; A17 ; 258 ; 7 ; mbus_addr3_i[15] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; A18 ; 250 ; 7 ; mbus_addr1_i[13] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; A19 ; 251 ; 7 ; cbus_addr_o[29] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; A20 ; 230 ; 6 ; mbus_addr1_i[8] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; A21 ; 223 ; 6 ; cbus_addr_o[12] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; A22 ; 222 ; 6 ; mbus_addr2_i[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AA3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; -; AA4 ; 53 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AA6 ; 68 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA7 ; 70 ; 3 ; mbus_addr0_i[30] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AA8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AA9 ; 76 ; 3 ; mbus_addr0_i[15] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AA10 ; 82 ; 3 ; mbus_addr0_i[4] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AA11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AA12 ; 90 ; 4 ; cbus_ack3_i ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AA13 ; 96 ; 4 ; mbus_addr3_i[17] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AA14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AA15 ; 110 ; 4 ; mbus_ack0_o ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AA16 ; 113 ; 4 ; mbus_cmd0_i[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AA17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AA18 ; 119 ; 4 ; mbus_addr3_i[23] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AA19 ; 122 ; 4 ; mbus_addr1_i[15] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AA20 ; 125 ; 4 ; cbus_addr_o[27] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AA21 ; 127 ; 4 ; mbus_addr2_i[30] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AA22 ; 131 ; 4 ; cbus_cmd2_o[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB1 ; ; ; RREF ; ; ; ; -- ; ; -- ; -- ; -; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AB3 ; 54 ; 3 ; ~ALTERA_NCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB4 ; 66 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB5 ; 67 ; 3 ; mbus_addr0_i[25] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB6 ; 69 ; 3 ; mbus_addr0_i[28] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB7 ; 71 ; 3 ; mbus_addr0_i[26] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB8 ; 77 ; 3 ; mbus_addr0_i[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB9 ; 78 ; 3 ; mbus_addr0_i[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB10 ; 86 ; 3 ; mbus_addr0_i[6] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB11 ; 87 ; 3 ; mbus_addr0_i[19] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB12 ; 91 ; 4 ; cbus_ack2_i ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB13 ; 97 ; 4 ; mbus_addr3_i[24] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB14 ; 99 ; 4 ; mbus_addr3_i[6] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB15 ; 100 ; 4 ; cbus_addr_o[28] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB16 ; 111 ; 4 ; mbus_addr3_i[31] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB17 ; 114 ; 4 ; cbus_addr_o[23] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB18 ; 115 ; 4 ; mbus_addr0_i[21] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB19 ; 123 ; 4 ; cbus_addr_o[22] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB20 ; 126 ; 4 ; cbus_addr_o[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB21 ; 128 ; 4 ; mbus_addr1_i[28] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB22 ; 132 ; 4 ; mbus_cmd1_i[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; B1 ; 307 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B3 ; 302 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B4 ; 303 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B6 ; 304 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B7 ; 294 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B9 ; 290 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; B10 ; 286 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B12 ; 270 ; 7 ; cbus_addr_o[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; B13 ; 271 ; 7 ; cbus_addr_o[20] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; B14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B15 ; 262 ; 7 ; cbus_addr_o[26] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; B16 ; 255 ; 7 ; mbus_addr2_i[25] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; B17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B18 ; 249 ; 7 ; cbus_cmd3_o[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; B19 ; 231 ; 6 ; mbus_addr2_i[13] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; B20 ; 227 ; 6 ; mbus_addr2_i[6] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; B21 ; 226 ; 6 ; mbus_addr1_i[19] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; B22 ; 220 ; 6 ; mbus_addr2_i[14] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; C1 ; 311 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C2 ; 312 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C3 ; 315 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C4 ; 316 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C5 ; 319 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C6 ; 305 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C7 ; 313 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C8 ; 308 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C9 ; 324 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C10 ; 278 ; 7 ; mbus_addr2_i[20] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; C11 ; 279 ; 7 ; mbus_addr3_i[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; C12 ; 268 ; 7 ; mbus_addr2_i[10] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; C13 ; 269 ; 7 ; mbus_addr2_i[9] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; C14 ; 263 ; 7 ; cbus_addr_o[21] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; C15 ; 259 ; 7 ; cbus_addr_o[24] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; C16 ; 256 ; 7 ; cbus_addr_o[4] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; C17 ; 247 ; 7 ; cbus_cmd2_o[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; C18 ; 248 ; 7 ; cbus_cmd0_o[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; C19 ; 229 ; 6 ; mbus_addr1_i[22] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; C20 ; 228 ; 6 ; mbus_addr1_i[24] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; C22 ; 221 ; 6 ; cbus_cmd2_o[0] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; D1 ; 346 ; 9 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Column I/O ; N ; no ; On ; -; D2 ; 350 ; 9 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; -; D3 ; 348 ; 9 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Column I/O ; N ; no ; On ; -; D4 ; 320 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D5 ; 321 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D6 ; 326 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D7 ; 314 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D8 ; 309 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D9 ; 325 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D10 ; 323 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D11 ; 310 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D12 ; 299 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D13 ; 267 ; 7 ; mbus_addr2_i[5] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; D14 ; 264 ; 7 ; mbus_addr2_i[8] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; D15 ; 260 ; 7 ; mbus_addr3_i[28] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; D16 ; 254 ; 7 ; mbus_addr3_i[12] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; D17 ; 252 ; 7 ; cbus_addr_o[13] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; D18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; D19 ; 225 ; 6 ; mbus_addr1_i[14] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; D20 ; 224 ; 6 ; mbus_addr2_i[22] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; D21 ; 216 ; 6 ; cbus_addr_o[15] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; D22 ; 215 ; 6 ; mbus_addr2_i[16] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; E1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; E3 ; 354 ; 9 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; -; E4 ; 352 ; 9 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; -; E5 ; 322 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E6 ; 327 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; E8 ; 317 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E10 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E12 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E15 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E17 ; 253 ; 7 ; cbus_addr_o[5] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; E18 ; ; ; VCCD_PLL ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; E19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; E20 ; 209 ; 6 ; mbus_addr1_i[9] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; E21 ; 214 ; 6 ; cbus_cmd0_o[1] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; E22 ; 213 ; 6 ; mbus_addr3_i[21] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; F1 ; 17 ; QL0 ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -; F2 ; 16 ; QL0 ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F4 ; ; -- ; VCCA ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; F5 ; 351 ; 9 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; -; F6 ; 330 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; F8 ; 318 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F10 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; F11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F12 ; 280 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; F15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F16 ; 245 ; 7 ; cbus_cmd1_o[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; F17 ; 246 ; 7 ; mbus_addr1_i[16] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; F18 ; 244 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F19 ; ; -- ; VCCA ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; F20 ; 210 ; 6 ; mbus_addr1_i[23] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; F21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F22 ; 211 ; 6 ; mbus_addr3_i[9] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; G1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; G2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; G3 ; ; ; VCCD_PLL ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; G4 ; ; 9 ; VCCIO9 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; G5 ; 353 ; 9 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; -; G6 ; 331 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G7 ; 328 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G8 ; 332 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; G10 ; 334 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G11 ; 340 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G12 ; 287 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; G14 ; 272 ; 7 ; mbus_addr3_i[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; G15 ; 273 ; 7 ; mbus_addr3_i[13] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; G16 ; 242 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G17 ; 241 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G18 ; 236 ; 6 ; mbus_addr1_i[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; G19 ; 243 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G20 ; 208 ; 6 ; cbus_addr_o[8] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; G21 ; 207 ; 6 ; mbus_cmd2_i[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; G22 ; 212 ; 6 ; cbus_cmd1_o[1] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; H1 ; 19 ; QL0 ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -; H2 ; 18 ; QL0 ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -; H3 ; ; -- ; VCCH_GXB ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; H4 ; 349 ; 9 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; -; H5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; H6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; H7 ; 329 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H8 ; 333 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H9 ; 335 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H10 ; ; 8A ; VCC_CLKIN8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; H11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; H12 ; 288 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H13 ; 281 ; 7 ; mbus_addr2_i[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; H14 ; 274 ; 7 ; mbus_addr2_i[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; H15 ; 240 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H16 ; 239 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H17 ; 219 ; 6 ; mbus_addr2_i[11] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; H18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; H19 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; H20 ; 206 ; 6 ; cbus_addr_o[14] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; H21 ; 205 ; 6 ; mbus_addr1_i[5] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; H22 ; 199 ; 6 ; cbus_addr_o[7] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; J3 ; ; -- ; VCCA_GXB ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; J4 ; 347 ; 9 ; ~ALTERA_NCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Column I/O ; N ; no ; On ; -; J5 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; J7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; J9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J10 ; 291 ; 8A ; GXB_GND* ; ; ; ; Column I/O ; ; -- ; -- ; -; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J12 ; 276 ; 7 ; mbus_addr2_i[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; J13 ; 282 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; J14 ; 275 ; 7 ; cbus_addr_o[18] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; J15 ; 196 ; 6 ; mbus_addr1_i[2] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; J16 ; 233 ; 6 ; mbus_addr1_i[21] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; J17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J18 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; J19 ; 198 ; 6 ; cbus_ack1_i ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; J20 ; 197 ; 6 ; cbus_cmd3_o[1] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; J21 ; 200 ; 6 ; cbus_cmd1_o[2] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; J22 ; 201 ; 6 ; cbus_addr_o[30] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; K1 ; 21 ; QL0 ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -; K2 ; 20 ; QL0 ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -; K3 ; ; -- ; VCCL_GXB ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K4 ; 345 ; 9 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Column I/O ; N ; no ; On ; -; K5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K10 ; 292 ; 8A ; GXB_GND* ; ; ; ; Column I/O ; ; -- ; -- ; -; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K12 ; 277 ; 7 ; mbus_addr2_i[4] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; K13 ; 238 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K14 ; 237 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K17 ; 232 ; 6 ; mbus_addr1_i[20] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; K18 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; K19 ; 204 ; 6 ; mbus_cmd2_i[1] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; K20 ; 203 ; 6 ; mbus_cmd2_i[2] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; K21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K22 ; 202 ; 6 ; mbus_ack2_o ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L3 ; ; -- ; VCCL_GXB ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L4 ; ; -- ; VCCA ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; L5 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L13 ; 175 ; 5 ; mbus_addr1_i[4] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; L14 ; 170 ; 5 ; mbus_addr1_i[30] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; L15 ; 169 ; 5 ; mbus_addr0_i[11] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; L16 ; 184 ; 5 ; mbus_cmd3_i[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; L17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L19 ; 193 ; 6 ; cbus_cmd3_o[2] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; L20 ; 192 ; 6 ; cbus_cmd0_o[2] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; L21 ; 191 ; 6 ; mbus_addr2_i[19] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; L22 ; 190 ; 6 ; mbus_addr1_i[18] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; M1 ; 23 ; QL0 ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -; M2 ; 22 ; QL0 ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -; M3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M4 ; ; ; VCCD_PLL ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M7 ; 38 ; 3B ; GXB_GND* ; ; ; ; Column I/O ; ; -- ; -- ; -; M8 ; 40 ; 3B ; GXB_GND* ; ; ; ; Column I/O ; ; -- ; -- ; -; M9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M11 ; 88 ; 3A ; rst ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; M12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M13 ; 176 ; 5 ; cbus_addr_o[16] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; M14 ; 167 ; 5 ; mbus_addr3_i[26] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; M15 ; 165 ; 5 ; mbus_addr1_i[6] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; M16 ; 185 ; 5 ; mbus_ack3_o ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; M17 ; 173 ; 5 ; mbus_addr1_i[27] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; M18 ; 187 ; 5 ; cbus_addr_o[1] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; M19 ; 186 ; 5 ; cbus_addr_o[10] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; M20 ; 183 ; 5 ; mbus_cmd3_i[2] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; M21 ; 189 ; 5 ; mbus_addr1_i[17] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; M22 ; 188 ; 5 ; mbus_addr0_i[17] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N3 ; ; -- ; VCCL_GXB ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N5 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N7 ; 39 ; 3B ; GXB_GND* ; ; ; ; Column I/O ; ; -- ; -- ; -; N8 ; 41 ; 3B ; GXB_GND* ; ; ; ; Column I/O ; ; -- ; -- ; -; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N11 ; 89 ; 3A ; clk ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; N12 ; ; 3A ; VCC_CLKIN3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; N13 ; 168 ; 5 ; mbus_addr3_i[5] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; N14 ; 166 ; 5 ; mbus_addr3_i[10] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; N15 ; 144 ; 5 ; mbus_addr2_i[23] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; N17 ; 174 ; 5 ; mbus_addr2_i[18] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; N18 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; N19 ; 178 ; 5 ; mbus_cmd3_i[1] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; N20 ; 177 ; 5 ; mbus_addr1_i[12] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; N21 ; 180 ; 5 ; mbus_addr2_i[17] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; N22 ; 179 ; 5 ; mbus_addr2_i[28] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; P1 ; 25 ; QL0 ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -; P2 ; 24 ; QL0 ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -; P3 ; ; -- ; VCCH_GXB ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; P4 ; 32 ; 3 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; -; P5 ; 34 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; -; P6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P7 ; ; 3B ; VCC_CLKIN3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; P8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P10 ; 55 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; P11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P13 ; 149 ; 5 ; mbus_addr1_i[29] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; P14 ; 148 ; 5 ; mbus_addr2_i[27] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; P15 ; 145 ; 5 ; mbus_addr3_i[4] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; P20 ; 164 ; 5 ; mbus_addr1_i[7] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; P21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P22 ; 171 ; 5 ; mbus_addr1_i[10] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R3 ; ; -- ; VCCA_GXB ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; R4 ; ; ; VCCD_PLL ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; R5 ; 33 ; 3 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; -; R6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; R8 ; 37 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; -; R9 ; 51 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; R10 ; 56 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; R11 ; 60 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; R12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R13 ; 92 ; 4 ; mbus_addr0_i[27] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; R14 ; 103 ; 4 ; cbus_addr_o[17] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; R15 ; 120 ; 4 ; mbus_addr3_i[30] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; R16 ; 138 ; 5 ; mbus_addr1_i[25] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; R17 ; 137 ; 5 ; mbus_addr3_i[20] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; R18 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; R19 ; 155 ; 5 ; mbus_addr2_i[29] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; R20 ; 159 ; 5 ; mbus_addr0_i[13] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; R21 ; 158 ; 5 ; mbus_addr2_i[26] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; R22 ; 172 ; 5 ; mbus_addr3_i[14] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; T1 ; 27 ; QL0 ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -; T2 ; 26 ; QL0 ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -; T3 ; ; -- ; VCCL_GXB ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; T4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T5 ; ; -- ; VCCA ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; T6 ; 35 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; -; T7 ; 42 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; T8 ; 43 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; T9 ; 52 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; T10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; T11 ; 61 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; T12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; T13 ; 93 ; 4 ; cbus_addr_o[31] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; T14 ; 104 ; 4 ; mbus_addr3_i[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; T15 ; 121 ; 4 ; mbus_addr3_i[25] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; T16 ; 124 ; 4 ; mbus_addr1_i[26] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; T17 ; 135 ; 5 ; cbus_addr_o[25] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; T18 ; 136 ; 5 ; mbus_addr3_i[29] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; T19 ; 153 ; 5 ; mbus_addr3_i[8] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; T20 ; 154 ; 5 ; mbus_addr1_i[1] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; T21 ; 161 ; 5 ; mbus_addr2_i[24] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; T22 ; 160 ; 5 ; mbus_addr3_i[27] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; U4 ; ; ; VCCD_PLL ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; U5 ; 36 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; -; U6 ; 44 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U7 ; 46 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U8 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; U9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; U10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; U11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; U12 ; 83 ; 3 ; mbus_addr0_i[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; U13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; U14 ; 107 ; 4 ; mbus_addr0_i[8] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; U15 ; 108 ; 4 ; mbus_cmd0_i[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; U18 ; 141 ; 5 ; mbus_addr3_i[11] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; U19 ; ; -- ; VCCA ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; U20 ; 152 ; 5 ; mbus_addr3_i[22] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; U21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; U22 ; 156 ; 5 ; mbus_addr2_i[31] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; V1 ; 29 ; QL0 ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -; V2 ; 28 ; QL0 ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; -; V3 ; ; -- ; VCCL_GXB ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; V4 ; ; -- ; VCCA ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V6 ; 45 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V7 ; 47 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V9 ; 59 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V10 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; V11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V12 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; V13 ; 98 ; 4 ; mbus_addr0_i[31] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V15 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; V16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; V17 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; V18 ; ; ; VCCD_PLL ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V20 ; 151 ; 5 ; mbus_addr1_i[3] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; V21 ; 150 ; 5 ; mbus_addr1_i[11] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; V22 ; 157 ; 5 ; mbus_addr1_i[31] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W3 ; ; -- ; VCCA_GXB ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; W4 ; 49 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; W5 ; 57 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; W6 ; 62 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; W7 ; 64 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; W8 ; 48 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; W9 ; 73 ; 3 ; mbus_addr0_i[5] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; W10 ; 72 ; 3 ; mbus_addr0_i[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; W11 ; 79 ; 3 ; mbus_addr0_i[7] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; W12 ; 84 ; 3 ; mbus_addr0_i[23] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; W13 ; 94 ; 4 ; cbus_addr_o[11] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; W14 ; 101 ; 4 ; mbus_addr3_i[16] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; W15 ; 105 ; 4 ; mbus_addr0_i[12] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; W16 ; 109 ; 4 ; mbus_cmd0_i[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; W17 ; 116 ; 4 ; mbus_addr0_i[29] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; W18 ; 129 ; 4 ; cbus_ack0_i ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; W19 ; 133 ; 4 ; mbus_cmd1_i[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; W20 ; 147 ; 5 ; mbus_addr2_i[21] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; W21 ; 146 ; 5 ; mbus_addr3_i[7] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; W22 ; 142 ; 5 ; mbus_addr0_i[24] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; Y1 ; 31 ; QL0 ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -; Y2 ; 30 ; QL0 ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; -; Y3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; -; Y4 ; 50 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y5 ; 58 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y6 ; 63 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y7 ; 65 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y8 ; 74 ; 3 ; mbus_addr0_i[16] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; Y9 ; 75 ; 3 ; mbus_addr0_i[18] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; Y10 ; 81 ; 3 ; mbus_addr0_i[20] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; Y11 ; 80 ; 3 ; mbus_addr0_i[14] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; Y12 ; 85 ; 3 ; mbus_addr0_i[9] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; Y13 ; 95 ; 4 ; cbus_addr_o[19] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; Y14 ; 102 ; 4 ; mbus_addr0_i[22] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; Y15 ; 106 ; 4 ; cbus_addr_o[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; Y16 ; 112 ; 4 ; mbus_addr0_i[10] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; Y17 ; 117 ; 4 ; mbus_addr3_i[19] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; Y18 ; 118 ; 4 ; cbus_addr_o[9] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; Y19 ; 130 ; 4 ; mbus_ack1_o ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; Y20 ; 134 ; 4 ; mbus_cmd1_i[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; Y21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y22 ; 143 ; 5 ; mbus_addr3_i[3] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -+----------+------------+----------+-------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -Note: Pin directions (input, output or bidir) are based on device operating in user mode. - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+-----------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------------------------------------------------------------------------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; -+-----------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------------------------------------------------------------------------------+--------------+ -; |mesi_isc ; 827 (0) ; 604 (0) ; 36 (36) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 194 ; 0 ; 223 (0) ; 346 (0) ; 258 (0) ; |mesi_isc ; ; -; |mesi_isc_breq_fifos:mesi_isc_breq_fifos| ; 597 (0) ; 440 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 124 (0) ; 285 (0) ; 188 (0) ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos ; ; -; |mesi_isc_basic_fifo:fifo_0| ; 109 (109) ; 106 (106) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 68 (68) ; 38 (38) ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0 ; ; -; |mesi_isc_basic_fifo:fifo_1| ; 110 (110) ; 106 (106) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 69 (69) ; 38 (38) ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1 ; ; -; |mesi_isc_basic_fifo:fifo_2| ; 109 (109) ; 106 (106) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 68 (68) ; 38 (38) ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2 ; ; -; |mesi_isc_basic_fifo:fifo_3| ; 109 (109) ; 106 (106) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 68 (68) ; 38 (38) ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3 ; ; -; |mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl| ; 160 (160) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 112 (112) ; 12 (12) ; 36 (36) ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl ; ; -; |mesi_isc_broad:mesi_isc_broad| ; 263 (0) ; 164 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 99 (0) ; 61 (0) ; 103 (0) ; |mesi_isc|mesi_isc_broad:mesi_isc_broad ; ; -; |mesi_isc_basic_fifo:broad_fifo| ; 218 (218) ; 154 (154) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 64 (64) ; 61 (61) ; 93 (93) ; |mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo ; ; -; |mesi_isc_broad_cntl:mesi_isc_broad_cntl| ; 45 (45) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 35 (35) ; 0 (0) ; 10 (10) ; |mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl ; ; -+-----------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------------------------------------------------------------------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+-------------------------------------------------------------------------------------------------------+ -; Delay Chain Summary ; -+------------------+----------+---------------+---------------+-----------------------+----------+------+ -; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; -+------------------+----------+---------------+---------------+-----------------------+----------+------+ -; cbus_addr_o[0] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[1] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[2] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[3] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[4] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[5] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[6] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[7] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[8] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[9] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[10] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[11] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[12] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[13] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[14] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[15] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[16] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[17] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[18] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[19] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[20] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[21] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[22] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[23] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[24] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[25] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[26] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[27] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[28] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[29] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[30] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_addr_o[31] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; cbus_cmd3_o[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; cbus_cmd3_o[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; cbus_cmd3_o[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; cbus_cmd2_o[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; cbus_cmd2_o[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; cbus_cmd2_o[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; cbus_cmd1_o[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; cbus_cmd1_o[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; cbus_cmd1_o[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; cbus_cmd0_o[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; cbus_cmd0_o[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; cbus_cmd0_o[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; mbus_ack3_o ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; mbus_ack2_o ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; mbus_ack1_o ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; mbus_ack0_o ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; clk ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; rst ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; cbus_ack3_i ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; cbus_ack2_i ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; cbus_ack1_i ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; cbus_ack0_i ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_cmd3_i[0] ; Input ; (3) 738 ps ; (1) 379 ps ; -- ; -- ; -- ; -; mbus_cmd3_i[2] ; Input ; (2) 552 ps ; (1) 379 ps ; -- ; -- ; -- ; -; mbus_cmd3_i[1] ; Input ; (0) 0 ps ; (1) 379 ps ; -- ; -- ; -- ; -; mbus_cmd2_i[0] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_cmd2_i[1] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_cmd2_i[2] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_cmd1_i[2] ; Input ; (1) 361 ps ; (1) 361 ps ; -- ; -- ; -- ; -; mbus_cmd1_i[0] ; Input ; (1) 361 ps ; -- ; -- ; -- ; -- ; -; mbus_cmd1_i[1] ; Input ; (2) 554 ps ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_cmd0_i[0] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_cmd0_i[1] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_cmd0_i[2] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr2_i[0] ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr3_i[0] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[0] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr1_i[0] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[1] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[1] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[1] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr1_i[1] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[2] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[2] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr0_i[2] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr1_i[2] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[3] ; Input ; (1) 361 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[3] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[3] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr1_i[3] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[4] ; Input ; (1) 361 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[4] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[4] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr1_i[4] ; Input ; -- ; (1) 379 ps ; -- ; -- ; -- ; -; mbus_addr2_i[5] ; Input ; (1) 361 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[5] ; Input ; (1) 379 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[5] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr1_i[5] ; Input ; -- ; (1) 379 ps ; -- ; -- ; -- ; -; mbus_addr2_i[6] ; Input ; -- ; (1) 379 ps ; -- ; -- ; -- ; -; mbus_addr3_i[6] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[6] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr1_i[6] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[7] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[7] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr0_i[7] ; Input ; -- ; (1) 361 ps ; -- ; -- ; -- ; -; mbus_addr1_i[7] ; Input ; (2) 552 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[8] ; Input ; (1) 361 ps ; (1) 361 ps ; -- ; -- ; -- ; -; mbus_addr3_i[8] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[8] ; Input ; (1) 361 ps ; -- ; -- ; -- ; -- ; -; mbus_addr1_i[8] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[9] ; Input ; -- ; (1) 361 ps ; -- ; -- ; -- ; -; mbus_addr3_i[9] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr0_i[9] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr1_i[9] ; Input ; -- ; (1) 379 ps ; -- ; -- ; -- ; -; mbus_addr2_i[10] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[10] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr0_i[10] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr1_i[10] ; Input ; (3) 738 ps ; (3) 738 ps ; -- ; -- ; -- ; -; mbus_addr2_i[11] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[11] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[11] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr1_i[11] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[12] ; Input ; (1) 361 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[12] ; Input ; (1) 361 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[12] ; Input ; -- ; (1) 361 ps ; -- ; -- ; -- ; -; mbus_addr1_i[12] ; Input ; (3) 738 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[13] ; Input ; (1) 379 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[13] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[13] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr1_i[13] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[14] ; Input ; (1) 379 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[14] ; Input ; -- ; (1) 379 ps ; -- ; -- ; -- ; -; mbus_addr0_i[14] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr1_i[14] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[15] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[15] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[15] ; Input ; (3) 742 ps ; (1) 361 ps ; -- ; -- ; -- ; -; mbus_addr1_i[15] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[16] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr3_i[16] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[16] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr1_i[16] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[17] ; Input ; (1) 379 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[17] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[17] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr1_i[17] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[18] ; Input ; (1) 379 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[18] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[18] ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr1_i[18] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[19] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[19] ; Input ; (1) 361 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[19] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr1_i[19] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[20] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[20] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[20] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr1_i[20] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[21] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr3_i[21] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[21] ; Input ; (1) 361 ps ; -- ; -- ; -- ; -- ; -; mbus_addr1_i[21] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr2_i[22] ; Input ; (1) 379 ps ; (2) 552 ps ; -- ; -- ; -- ; -; mbus_addr3_i[22] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[22] ; Input ; (1) 361 ps ; -- ; -- ; -- ; -- ; -; mbus_addr1_i[22] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[23] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr3_i[23] ; Input ; (1) 361 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[23] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr1_i[23] ; Input ; (1) 379 ps ; (1) 379 ps ; -- ; -- ; -- ; -; mbus_addr2_i[24] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr3_i[24] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[24] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr1_i[24] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr2_i[25] ; Input ; (2) 554 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[25] ; Input ; (1) 361 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[25] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr1_i[25] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[26] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[26] ; Input ; -- ; (1) 379 ps ; -- ; -- ; -- ; -; mbus_addr0_i[26] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr1_i[26] ; Input ; (1) 361 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[27] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[27] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr0_i[27] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr1_i[27] ; Input ; (1) 379 ps ; -- ; -- ; -- ; -- ; -; mbus_addr2_i[28] ; Input ; -- ; (1) 379 ps ; -- ; -- ; -- ; -; mbus_addr3_i[28] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[28] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr1_i[28] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr2_i[29] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr3_i[29] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr0_i[29] ; Input ; (1) 361 ps ; (1) 361 ps ; -- ; -- ; -- ; -; mbus_addr1_i[29] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr2_i[30] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[30] ; Input ; -- ; (1) 361 ps ; -- ; -- ; -- ; -; mbus_addr0_i[30] ; Input ; (1) 361 ps ; (2) 554 ps ; -- ; -- ; -- ; -; mbus_addr1_i[30] ; Input ; (1) 379 ps ; (1) 379 ps ; -- ; -- ; -- ; -; mbus_addr2_i[31] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; mbus_addr3_i[31] ; Input ; -- ; (1) 361 ps ; -- ; -- ; -- ; -; mbus_addr0_i[31] ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; mbus_addr1_i[31] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -+------------------+----------+---------------+---------------+-----------------------+----------+------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Pad To Core Delay Chain Fanout ; -+-------------------------------------------------------------------------------------------------------------------+-------------------+---------+ -; Source Pin / Fanout ; Pad To Core Index ; Setting ; -+-------------------------------------------------------------------------------------------------------------------+-------------------+---------+ -; clk ; ; ; -; rst ; ; ; -; cbus_ack3_i ; ; ; -; cbus_ack2_i ; ; ; -; cbus_ack1_i ; ; ; -; - mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array~7 ; 0 ; 0 ; -; - mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o~0 ; 0 ; 0 ; -; cbus_ack0_i ; ; ; -; - mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array~10 ; 0 ; 0 ; -; - mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o~1 ; 0 ; 0 ; -; mbus_cmd3_i[0] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array~1 ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal1~0 ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal0~0 ; 0 ; 3 ; -; mbus_cmd3_i[2] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array~0 ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array~1 ; 0 ; 2 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal1~0 ; 0 ; 2 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal0~0 ; 0 ; 2 ; -; mbus_cmd3_i[1] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array~0 ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal1~0 ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal0~0 ; 1 ; 1 ; -; mbus_cmd2_i[0] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal2~0 ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal3~0 ; 1 ; 0 ; -; mbus_cmd2_i[1] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal2~0 ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal3~0 ; 0 ; 0 ; -; mbus_cmd2_i[2] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal2~0 ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal3~0 ; 1 ; 0 ; -; mbus_cmd1_i[2] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array~4 ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal5~0 ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal4~0 ; 0 ; 1 ; -; mbus_cmd1_i[0] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array~4 ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal5~0 ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal4~0 ; 0 ; 1 ; -; mbus_cmd1_i[1] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array~4 ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal5~0 ; 0 ; 2 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal4~0 ; 0 ; 2 ; -; mbus_cmd0_i[0] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal6~0 ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal7~0 ; 0 ; 0 ; -; mbus_cmd0_i[1] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal6~0 ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal7~0 ; 1 ; 0 ; -; mbus_cmd0_i[2] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal6~0 ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal7~0 ; 1 ; 0 ; -; mbus_addr2_i[0] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[9] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][9]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][9]~feeder ; 1 ; 0 ; -; mbus_addr3_i[0] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[9] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][9]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][9]~feeder ; 0 ; 0 ; -; mbus_addr0_i[0] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[9] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][9]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][9]~feeder ; 0 ; 0 ; -; mbus_addr1_i[0] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[9] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][9]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][9]~feeder ; 0 ; 0 ; -; mbus_addr2_i[1] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[10] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][10]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][10]~feeder ; 0 ; 0 ; -; mbus_addr3_i[1] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[10] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][10]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][10]~feeder ; 0 ; 0 ; -; mbus_addr0_i[1] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[10] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][10]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][10]~feeder ; 0 ; 0 ; -; mbus_addr1_i[1] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[10] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][10]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][10]~feeder ; 0 ; 0 ; -; mbus_addr2_i[2] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[11] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][11]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][11]~feeder ; 0 ; 0 ; -; mbus_addr3_i[2] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[11] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][11]~feeder ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][11]~feeder ; 1 ; 0 ; -; mbus_addr0_i[2] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[11] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][11]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][11]~feeder ; 0 ; 0 ; -; mbus_addr1_i[2] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][11] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[11] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][11]~feeder ; 0 ; 0 ; -; mbus_addr2_i[3] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][12] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[12] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][12]~feeder ; 0 ; 1 ; -; mbus_addr3_i[3] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[12] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][12]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][12]~feeder ; 0 ; 0 ; -; mbus_addr0_i[3] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[12] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][12]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][12]~feeder ; 0 ; 0 ; -; mbus_addr1_i[3] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[12] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][12]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][12]~feeder ; 0 ; 0 ; -; mbus_addr2_i[4] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[13] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][13]~feeder ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][13]~feeder ; 0 ; 1 ; -; mbus_addr3_i[4] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[13] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][13]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][13]~feeder ; 0 ; 0 ; -; mbus_addr0_i[4] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[13] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][13]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][13]~feeder ; 0 ; 0 ; -; mbus_addr1_i[4] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[13] ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][13]~feeder ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][13]~feeder ; 1 ; 1 ; -; mbus_addr2_i[5] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][14] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[14] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][14]~feeder ; 0 ; 1 ; -; mbus_addr3_i[5] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[14] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][14]~feeder ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][14]~feeder ; 0 ; 1 ; -; mbus_addr0_i[5] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[14] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][14]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][14]~feeder ; 0 ; 0 ; -; mbus_addr1_i[5] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[14] ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][14]~feeder ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][14]~feeder ; 1 ; 1 ; -; mbus_addr2_i[6] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[15] ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][15]~feeder ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][15]~feeder ; 1 ; 1 ; -; mbus_addr3_i[6] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[15] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][15]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][15]~feeder ; 0 ; 0 ; -; mbus_addr0_i[6] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[15] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][15]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][15]~feeder ; 0 ; 0 ; -; mbus_addr1_i[6] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[15] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][15]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][15]~feeder ; 0 ; 0 ; -; mbus_addr2_i[7] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[16] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][16]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][16]~feeder ; 0 ; 0 ; -; mbus_addr3_i[7] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[16] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][16]~feeder ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][16]~feeder ; 1 ; 0 ; -; mbus_addr0_i[7] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[16] ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][16]~feeder ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][16]~feeder ; 1 ; 1 ; -; mbus_addr1_i[7] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[16] ; 0 ; 2 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][16]~feeder ; 0 ; 2 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][16]~feeder ; 0 ; 2 ; -; mbus_addr2_i[8] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[17] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][17]~feeder ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][17]~feeder ; 1 ; 1 ; -; mbus_addr3_i[8] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[17] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][17]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][17]~feeder ; 0 ; 0 ; -; mbus_addr0_i[8] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[17] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][17]~feeder ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][17]~feeder ; 0 ; 1 ; -; mbus_addr1_i[8] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[17] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][17]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][17]~feeder ; 0 ; 0 ; -; mbus_addr2_i[9] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][18] ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[18] ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][18]~feeder ; 1 ; 1 ; -; mbus_addr3_i[9] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[18] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][18]~feeder ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][18]~feeder ; 1 ; 0 ; -; mbus_addr0_i[9] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[18] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][18]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][18]~feeder ; 0 ; 0 ; -; mbus_addr1_i[9] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[18] ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][18]~feeder ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][18]~feeder ; 1 ; 1 ; -; mbus_addr2_i[10] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[19] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][19]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][19]~feeder ; 0 ; 0 ; -; mbus_addr3_i[10] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[19] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][19]~feeder ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][19]~feeder ; 1 ; 0 ; -; mbus_addr0_i[10] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][19] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[19] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][19]~feeder ; 1 ; 0 ; -; mbus_addr1_i[10] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][19] ; 1 ; 3 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[19] ; 0 ; 3 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][19]~feeder ; 0 ; 3 ; -; mbus_addr2_i[11] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[20] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][20]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][20]~feeder ; 0 ; 0 ; -; mbus_addr3_i[11] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[20] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][20]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][20]~feeder ; 0 ; 0 ; -; mbus_addr0_i[11] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][20] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[20] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][20]~feeder ; 0 ; 0 ; -; mbus_addr1_i[11] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[20] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][20]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][20]~feeder ; 0 ; 0 ; -; mbus_addr2_i[12] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[21] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][21]~feeder ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][21]~feeder ; 0 ; 1 ; -; mbus_addr3_i[12] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[21] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][21]~feeder ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][21]~feeder ; 0 ; 1 ; -; mbus_addr0_i[12] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[21] ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][21]~feeder ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][21]~feeder ; 1 ; 1 ; -; mbus_addr1_i[12] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[21] ; 0 ; 3 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][21]~feeder ; 0 ; 3 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][21]~feeder ; 0 ; 3 ; -; mbus_addr2_i[13] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[22] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][22]~feeder ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][22]~feeder ; 0 ; 1 ; -; mbus_addr3_i[13] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[22] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][22]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][22]~feeder ; 0 ; 0 ; -; mbus_addr0_i[13] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[22] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][22]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][22]~feeder ; 0 ; 0 ; -; mbus_addr1_i[13] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][22] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[22] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][22]~feeder ; 0 ; 0 ; -; mbus_addr2_i[14] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][23] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[23] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][23]~feeder ; 0 ; 1 ; -; mbus_addr3_i[14] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[23] ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][23]~feeder ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][23]~feeder ; 1 ; 1 ; -; mbus_addr0_i[14] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[23] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][23]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][23]~feeder ; 0 ; 0 ; -; mbus_addr1_i[14] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[23] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][23]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][23]~feeder ; 0 ; 0 ; -; mbus_addr2_i[15] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][24] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[24] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][24]~feeder ; 0 ; 0 ; -; mbus_addr3_i[15] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[24] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][24]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][24]~feeder ; 0 ; 0 ; -; mbus_addr0_i[15] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[24] ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][24]~feeder ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][24]~feeder ; 0 ; 3 ; -; mbus_addr1_i[15] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[24] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][24]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][24]~feeder ; 0 ; 0 ; -; mbus_addr2_i[16] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[25] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][25]~feeder ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][25]~feeder ; 1 ; 0 ; -; mbus_addr3_i[16] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[25] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][25]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][25]~feeder ; 0 ; 0 ; -; mbus_addr0_i[16] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[25] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][25]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][25]~feeder ; 0 ; 0 ; -; mbus_addr1_i[16] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][25] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[25] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][25]~feeder ; 0 ; 0 ; -; mbus_addr2_i[17] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[26] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][26]~feeder ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][26]~feeder ; 0 ; 1 ; -; mbus_addr3_i[17] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[26] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][26]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][26]~feeder ; 0 ; 0 ; -; mbus_addr0_i[17] ; ; ; -; mbus_addr1_i[17] ; ; ; -; mbus_addr2_i[18] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[27] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][27]~feeder ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][27]~feeder ; 0 ; 1 ; -; mbus_addr3_i[18] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[27] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][27]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][27]~feeder ; 0 ; 0 ; -; mbus_addr0_i[18] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[27] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][27]~feeder ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][27]~feeder ; 0 ; 0 ; -; mbus_addr1_i[18] ; ; ; -; mbus_addr2_i[19] ; ; ; -; mbus_addr3_i[19] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][28] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[28] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][28]~feeder ; 0 ; 1 ; -; mbus_addr0_i[19] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[28] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][28]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][28]~feeder ; 0 ; 0 ; -; mbus_addr1_i[19] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[28] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][28]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][28]~feeder ; 0 ; 0 ; -; mbus_addr2_i[20] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[29] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][29]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][29]~feeder ; 0 ; 0 ; -; mbus_addr3_i[20] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[29] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][29]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][29]~feeder ; 0 ; 0 ; -; mbus_addr0_i[20] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[29] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][29]~feeder ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][29]~feeder ; 1 ; 0 ; -; mbus_addr1_i[20] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[29] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][29]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][29]~feeder ; 0 ; 0 ; -; mbus_addr2_i[21] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][30] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[30] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][30]~feeder ; 1 ; 0 ; -; mbus_addr3_i[21] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[30] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][30]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][30]~feeder ; 0 ; 0 ; -; mbus_addr0_i[21] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[30] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][30]~feeder ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][30]~feeder ; 0 ; 1 ; -; mbus_addr1_i[21] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][30] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[30] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][30]~feeder ; 1 ; 0 ; -; mbus_addr2_i[22] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[31] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][31]~feeder ; 1 ; 2 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][31]~feeder ; 0 ; 1 ; -; mbus_addr3_i[22] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[31] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][31]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][31]~feeder ; 0 ; 0 ; -; mbus_addr0_i[22] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[31] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][31]~feeder ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][31]~feeder ; 0 ; 1 ; -; mbus_addr1_i[22] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[31] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][31]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][31]~feeder ; 0 ; 0 ; -; mbus_addr2_i[23] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[32] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][32]~feeder ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][32]~feeder ; 1 ; 0 ; -; mbus_addr3_i[23] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[32] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][32]~feeder ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][32]~feeder ; 0 ; 1 ; -; mbus_addr0_i[23] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[32] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][32]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][32]~feeder ; 0 ; 0 ; -; mbus_addr1_i[23] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[32] ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][32]~feeder ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][32]~feeder ; 1 ; 1 ; -; mbus_addr2_i[24] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[33] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][33]~feeder ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][33]~feeder ; 1 ; 0 ; -; mbus_addr3_i[24] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[33] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][33]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][33]~feeder ; 0 ; 0 ; -; mbus_addr0_i[24] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[33] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][33]~feeder ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][33]~feeder ; 1 ; 0 ; -; mbus_addr1_i[24] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[33] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][33]~feeder ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][33]~feeder ; 1 ; 0 ; -; mbus_addr2_i[25] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[34] ; 0 ; 2 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][34]~feeder ; 0 ; 2 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][34]~feeder ; 0 ; 2 ; -; mbus_addr3_i[25] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][34] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[34] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][34]~feeder ; 0 ; 1 ; -; mbus_addr0_i[25] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[34] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][34]~feeder ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][34]~feeder ; 1 ; 0 ; -; mbus_addr1_i[25] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[34] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][34]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][34]~feeder ; 0 ; 0 ; -; mbus_addr2_i[26] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][35] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[35] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][35]~feeder ; 0 ; 0 ; -; mbus_addr3_i[26] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[35] ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][35]~feeder ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][35]~feeder ; 1 ; 1 ; -; mbus_addr0_i[26] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[35] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][35]~feeder ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][35]~feeder ; 1 ; 0 ; -; mbus_addr1_i[26] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[35] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][35]~feeder ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][35]~feeder ; 0 ; 1 ; -; mbus_addr2_i[27] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[36] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][36]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][36]~feeder ; 0 ; 0 ; -; mbus_addr3_i[27] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[36] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][36]~feeder ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][36]~feeder ; 1 ; 0 ; -; mbus_addr0_i[27] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[36] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][36]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][36]~feeder ; 0 ; 0 ; -; mbus_addr1_i[27] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[36] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][36]~feeder ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][36]~feeder ; 0 ; 1 ; -; mbus_addr2_i[28] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][37] ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[37] ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][37]~feeder ; 1 ; 1 ; -; mbus_addr3_i[28] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[37] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][37]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][37]~feeder ; 0 ; 0 ; -; mbus_addr0_i[28] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[37] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][37]~feeder ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][37]~feeder ; 1 ; 0 ; -; mbus_addr1_i[28] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][37] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[37] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][37]~feeder ; 1 ; 0 ; -; mbus_addr2_i[29] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[38] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][38]~feeder ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][38]~feeder ; 1 ; 0 ; -; mbus_addr3_i[29] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[38] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][38]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][38]~feeder ; 0 ; 0 ; -; mbus_addr0_i[29] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[38] ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][38]~feeder ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][38]~feeder ; 1 ; 1 ; -; mbus_addr1_i[29] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[38] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][38]~feeder ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][38]~feeder ; 1 ; 0 ; -; mbus_addr2_i[30] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[39] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][39]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][39]~feeder ; 0 ; 0 ; -; mbus_addr3_i[30] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[39] ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][39]~feeder ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][39]~feeder ; 1 ; 1 ; -; mbus_addr0_i[30] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[39] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][39]~feeder ; 1 ; 2 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][39]~feeder ; 1 ; 2 ; -; mbus_addr1_i[30] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[39] ; 0 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][39]~feeder ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][39]~feeder ; 0 ; 1 ; -; mbus_addr2_i[31] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[40] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][40]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][40]~feeder ; 0 ; 0 ; -; mbus_addr3_i[31] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][40] ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[40] ; 1 ; 1 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][40]~feeder ; 1 ; 1 ; -; mbus_addr0_i[31] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][40] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[40] ; 1 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][40]~feeder ; 1 ; 0 ; -; mbus_addr1_i[31] ; ; ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[40] ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][40]~feeder ; 0 ; 0 ; -; - mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][40]~feeder ; 0 ; 0 ; -+-------------------------------------------------------------------------------------------------------------------+-------------------+---------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Control Signals ; -+--------------------------------------------------------------------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ -; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; -+--------------------------------------------------------------------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ -; clk ; PIN_N11 ; 640 ; Clock ; yes ; Global Clock ; GCLK29 ; -- ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][7]~1 ; LCCOMB_X57_Y14_N30 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][7]~0 ; LCCOMB_X57_Y14_N24 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|status_empty ; FF_X64_Y26_N21 ; 39 ; Sync. load ; no ; -- ; -- ; -- ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][22]~1 ; LCCOMB_X65_Y20_N26 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][26]~0 ; LCCOMB_X65_Y20_N24 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|status_empty ; FF_X64_Y26_N1 ; 39 ; Sync. load ; no ; -- ; -- ; -- ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][25]~1 ; LCCOMB_X65_Y26_N4 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][26]~0 ; LCCOMB_X65_Y26_N2 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|status_empty ; FF_X64_Y26_N25 ; 39 ; Sync. load ; no ; -- ; -- ; -- ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][26]~1 ; LCCOMB_X61_Y22_N28 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][7]~0 ; LCCOMB_X61_Y22_N10 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|status_empty ; FF_X64_Y26_N27 ; 39 ; Sync. load ; no ; -- ; -- ; -- ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|WideOr0 ; LCCOMB_X64_Y26_N28 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|Decoder0~0 ; LCCOMB_X62_Y26_N28 ; 36 ; Clock enable ; no ; -- ; -- ; -- ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|Decoder0~2 ; LCCOMB_X62_Y26_N16 ; 36 ; Clock enable ; no ; -- ; -- ; -- ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|Decoder0~3 ; LCCOMB_X63_Y26_N26 ; 36 ; Clock enable ; no ; -- ; -- ; -- ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|Decoder0~4 ; LCCOMB_X62_Y26_N30 ; 36 ; Clock enable ; no ; -- ; -- ; -- ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; FF_X68_Y28_N23 ; 26 ; Clock enable ; no ; -- ; -- ; -- ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[3]~1 ; LCCOMB_X68_Y28_N30 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; rst ; PIN_M11 ; 640 ; Async. clear ; yes ; Global Clock ; GCLK28 ; -- ; -+--------------------------------------------------------------------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------+ -; Global & Other Fast Signals ; -+------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+ -; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; -+------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+ -; clk ; PIN_N11 ; 640 ; 21 ; Global Clock ; GCLK29 ; -- ; -; rst ; PIN_M11 ; 640 ; 0 ; Global Clock ; GCLK28 ; -- ; -+------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------+ -; Non-Global High Fan-Out Signals ; -+--------------------------------------------------------------------------------------------------------------------------+---------+ -; Name ; Fan-Out ; -+--------------------------------------------------------------------------------------------------------------------------+---------+ -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[21]~1 ; 54 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[21]~0 ; 54 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|status_empty ; 47 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifo_select_oh[1] ; 41 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifo_select_oh[3] ; 41 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifo_select_oh[2] ; 40 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifo_select_oh[0] ; 39 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|status_empty ; 39 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|status_empty ; 39 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|status_empty ; 39 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|status_empty ; 39 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|Decoder0~4 ; 36 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|Decoder0~3 ; 36 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|Decoder0~2 ; 36 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|Decoder0~0 ; 36 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[33]~0 ; 35 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[27]~0 ; 35 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[25]~0 ; 35 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[29]~0 ; 35 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][22]~1 ; 34 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][26]~0 ; 34 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][7]~1 ; 34 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][7]~0 ; 34 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][26]~1 ; 34 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][7]~0 ; 34 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][25]~1 ; 34 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][26]~0 ; 34 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; 26 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|WideOr0~0 ; 19 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|status_full ; 14 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|always0~0 ; 13 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|Equal0~0 ; 11 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|ptr_wr[0] ; 9 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifos_priority[3] ; 9 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifos_priority[2] ; 9 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifos_priority[1] ; 9 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifos_priority[0] ; 9 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[5] ; 8 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[6] ; 8 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|WideOr0 ; 7 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broadcast_in_progress ; 7 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|ptr_rd[0] ; 7 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|ptr_wr[1] ; 6 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[0]~_Duplicate_1 ; 6 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[1]~_Duplicate_1 ; 6 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[2]~_Duplicate_1 ; 6 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[3]~_Duplicate_1 ; 6 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|WideOr0~1 ; 5 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifo_rd_array_o[3] ; 5 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifo_select_oh[0]~2 ; 5 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; 5 ; -; mbus_cmd3_i[2]~input ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_cpu_id_o[0] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_type_o[0] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_type_o[1] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[31] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[30] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[29] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[28] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[27] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[26] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[25] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[24] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[23] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[22] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[21] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[20] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[19] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[18] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[17] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[16] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[15] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[14] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[13] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[12] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[11] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[10] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[9] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[8] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[7] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[6] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[5] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[4] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[3] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[2] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[1] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|ptr_wr[0] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|ptr_wr[0] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|ptr_wr[0] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|ptr_wr[0] ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[0] ; 4 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[3]~1 ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifo_select_oh[0]~10 ; 4 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifo_select_oh[0]~9 ; 4 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[0] ; 4 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[1] ; 4 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[2] ; 4 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[3] ; 4 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; 4 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; 4 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; 4 ; -; mbus_addr1_i[31]~input ; 3 ; -; mbus_addr0_i[31]~input ; 3 ; -; mbus_addr3_i[31]~input ; 3 ; -; mbus_addr2_i[31]~input ; 3 ; -; mbus_addr1_i[30]~input ; 3 ; -; mbus_addr0_i[30]~input ; 3 ; -; mbus_addr3_i[30]~input ; 3 ; -; mbus_addr2_i[30]~input ; 3 ; -; mbus_addr1_i[29]~input ; 3 ; -; mbus_addr0_i[29]~input ; 3 ; -; mbus_addr3_i[29]~input ; 3 ; -; mbus_addr2_i[29]~input ; 3 ; -; mbus_addr1_i[28]~input ; 3 ; -; mbus_addr0_i[28]~input ; 3 ; -; mbus_addr3_i[28]~input ; 3 ; -; mbus_addr2_i[28]~input ; 3 ; -; mbus_addr1_i[27]~input ; 3 ; -; mbus_addr0_i[27]~input ; 3 ; -; mbus_addr3_i[27]~input ; 3 ; -; mbus_addr2_i[27]~input ; 3 ; -; mbus_addr1_i[26]~input ; 3 ; -; mbus_addr0_i[26]~input ; 3 ; -; mbus_addr3_i[26]~input ; 3 ; -; mbus_addr2_i[26]~input ; 3 ; -; mbus_addr1_i[25]~input ; 3 ; -; mbus_addr0_i[25]~input ; 3 ; -; mbus_addr3_i[25]~input ; 3 ; -; mbus_addr2_i[25]~input ; 3 ; -; mbus_addr1_i[24]~input ; 3 ; -; mbus_addr0_i[24]~input ; 3 ; -; mbus_addr3_i[24]~input ; 3 ; -; mbus_addr2_i[24]~input ; 3 ; -; mbus_addr1_i[23]~input ; 3 ; -; mbus_addr0_i[23]~input ; 3 ; -; mbus_addr3_i[23]~input ; 3 ; -; mbus_addr2_i[23]~input ; 3 ; -; mbus_addr1_i[22]~input ; 3 ; -; mbus_addr0_i[22]~input ; 3 ; -; mbus_addr3_i[22]~input ; 3 ; -; mbus_addr2_i[22]~input ; 3 ; -; mbus_addr1_i[21]~input ; 3 ; -; mbus_addr0_i[21]~input ; 3 ; -; mbus_addr3_i[21]~input ; 3 ; -; mbus_addr2_i[21]~input ; 3 ; -; mbus_addr1_i[20]~input ; 3 ; -; mbus_addr0_i[20]~input ; 3 ; -; mbus_addr3_i[20]~input ; 3 ; -; mbus_addr2_i[20]~input ; 3 ; -; mbus_addr1_i[19]~input ; 3 ; -; mbus_addr0_i[19]~input ; 3 ; -; mbus_addr3_i[19]~input ; 3 ; -; mbus_addr2_i[19]~input ; 3 ; -; mbus_addr1_i[18]~input ; 3 ; -; mbus_addr0_i[18]~input ; 3 ; -; mbus_addr3_i[18]~input ; 3 ; -; mbus_addr2_i[18]~input ; 3 ; -; mbus_addr1_i[17]~input ; 3 ; -; mbus_addr0_i[17]~input ; 3 ; -; mbus_addr3_i[17]~input ; 3 ; -; mbus_addr2_i[17]~input ; 3 ; -; mbus_addr1_i[16]~input ; 3 ; -; mbus_addr0_i[16]~input ; 3 ; -; mbus_addr3_i[16]~input ; 3 ; -; mbus_addr2_i[16]~input ; 3 ; -; mbus_addr1_i[15]~input ; 3 ; -; mbus_addr0_i[15]~input ; 3 ; -; mbus_addr3_i[15]~input ; 3 ; -; mbus_addr2_i[15]~input ; 3 ; -; mbus_addr1_i[14]~input ; 3 ; -; mbus_addr0_i[14]~input ; 3 ; -; mbus_addr3_i[14]~input ; 3 ; -; mbus_addr2_i[14]~input ; 3 ; -; mbus_addr1_i[13]~input ; 3 ; -; mbus_addr0_i[13]~input ; 3 ; -; mbus_addr3_i[13]~input ; 3 ; -; mbus_addr2_i[13]~input ; 3 ; -; mbus_addr1_i[12]~input ; 3 ; -; mbus_addr0_i[12]~input ; 3 ; -; mbus_addr3_i[12]~input ; 3 ; -; mbus_addr2_i[12]~input ; 3 ; -; mbus_addr1_i[11]~input ; 3 ; -; mbus_addr0_i[11]~input ; 3 ; -; mbus_addr3_i[11]~input ; 3 ; -; mbus_addr2_i[11]~input ; 3 ; -; mbus_addr1_i[10]~input ; 3 ; -; mbus_addr0_i[10]~input ; 3 ; -; mbus_addr3_i[10]~input ; 3 ; -; mbus_addr2_i[10]~input ; 3 ; -; mbus_addr1_i[9]~input ; 3 ; -; mbus_addr0_i[9]~input ; 3 ; -; mbus_addr3_i[9]~input ; 3 ; -; mbus_addr2_i[9]~input ; 3 ; -; mbus_addr1_i[8]~input ; 3 ; -; mbus_addr0_i[8]~input ; 3 ; -; mbus_addr3_i[8]~input ; 3 ; -; mbus_addr2_i[8]~input ; 3 ; -; mbus_addr1_i[7]~input ; 3 ; -; mbus_addr0_i[7]~input ; 3 ; -; mbus_addr3_i[7]~input ; 3 ; -; mbus_addr2_i[7]~input ; 3 ; -; mbus_addr1_i[6]~input ; 3 ; -; mbus_addr0_i[6]~input ; 3 ; -; mbus_addr3_i[6]~input ; 3 ; -; mbus_addr2_i[6]~input ; 3 ; -; mbus_addr1_i[5]~input ; 3 ; -; mbus_addr0_i[5]~input ; 3 ; -; mbus_addr3_i[5]~input ; 3 ; -; mbus_addr2_i[5]~input ; 3 ; -; mbus_addr1_i[4]~input ; 3 ; -; mbus_addr0_i[4]~input ; 3 ; -; mbus_addr3_i[4]~input ; 3 ; -; mbus_addr2_i[4]~input ; 3 ; -; mbus_addr1_i[3]~input ; 3 ; -; mbus_addr0_i[3]~input ; 3 ; -; mbus_addr3_i[3]~input ; 3 ; -; mbus_addr2_i[3]~input ; 3 ; -; mbus_addr1_i[2]~input ; 3 ; -; mbus_addr0_i[2]~input ; 3 ; -; mbus_addr3_i[2]~input ; 3 ; -; mbus_addr2_i[2]~input ; 3 ; -; mbus_addr1_i[1]~input ; 3 ; -; mbus_addr0_i[1]~input ; 3 ; -; mbus_addr3_i[1]~input ; 3 ; -; mbus_addr2_i[1]~input ; 3 ; -; mbus_addr1_i[0]~input ; 3 ; -; mbus_addr0_i[0]~input ; 3 ; -; mbus_addr3_i[0]~input ; 3 ; -; mbus_addr2_i[0]~input ; 3 ; -; mbus_cmd1_i[1]~input ; 3 ; -; mbus_cmd1_i[0]~input ; 3 ; -; mbus_cmd1_i[2]~input ; 3 ; -; mbus_cmd3_i[1]~input ; 3 ; -; mbus_cmd3_i[0]~input ; 3 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[2] ; 3 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[0] ; 3 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[6] ; 3 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[4] ; 3 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[3] ; 3 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[1] ; 3 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[7] ; 3 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[5] ; 3 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|WideOr0~0 ; 3 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|ptr_rd[1] ; 3 ; -; mbus_cmd0_i[2]~input ; 2 ; -; mbus_cmd0_i[1]~input ; 2 ; -; mbus_cmd0_i[0]~input ; 2 ; -; mbus_cmd2_i[2]~input ; 2 ; -; mbus_cmd2_i[1]~input ; 2 ; -; mbus_cmd2_i[0]~input ; 2 ; -; cbus_ack0_i~input ; 2 ; -; cbus_ack1_i~input ; 2 ; -; cbus_ack2_i~input ; 2 ; -; cbus_ack3_i~input ; 2 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|Add2~0 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|Add2~0 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|ptr_rd[0] ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifo_rd_array_o[0] ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|Add2~0 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|ptr_rd[0] ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|Add2~0 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|ptr_rd[0] ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifo_rd_array_o[2] ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|Add2~0 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|ptr_rd[0] ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifo_rd_array_o[1] ; 2 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|Decoder0~1 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array~5 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|status_full ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal7~0 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal6~0 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array~4 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|status_full ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array~2 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|status_full ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal3~0 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal2~0 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array~1 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|status_full ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_type_o[0]~3 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_type_o[0]~2 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_type_o[1]~1 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_type_o[1]~0 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[31]~63 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[31]~62 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[30]~61 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[30]~60 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[29]~59 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[29]~58 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[28]~57 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[28]~56 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[27]~55 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[27]~54 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[26]~53 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[26]~52 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[25]~51 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[25]~50 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[24]~49 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[24]~48 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[23]~47 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[23]~46 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[22]~45 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[22]~44 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[21]~43 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[21]~42 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[20]~41 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[20]~40 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[19]~39 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[19]~38 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[18]~37 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[18]~36 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[17]~35 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[17]~34 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[16]~33 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[16]~32 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[15]~31 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[15]~30 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[14]~29 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[14]~28 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[13]~27 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[13]~26 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[12]~25 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[12]~24 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[11]~23 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[11]~22 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[10]~21 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[10]~20 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[9]~19 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[9]~18 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[8]~17 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[8]~16 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[7]~15 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[7]~14 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[6]~13 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[6]~12 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[5]~11 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[5]~10 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[4]~9 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[4]~8 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[3]~7 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[3]~6 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[2]~5 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[2]~4 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[1]~3 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[1]~2 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[0]~1 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|broad_addr_o[0]~0 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|WideOr1 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifo_select_oh[0]~5 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|WideOr1~1 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|WideOr1~0 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifo_select_oh[0]~1 ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifo_select_oh[0]~0 ; 2 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; 2 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; 2 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[0] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[1] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[2] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[3] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|ptr_wr[0]~1 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifos_priority[1]~1 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifos_priority[0]~0 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|ptr_rd[0]~0 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal4~0 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal0~0 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal5~0 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|Equal1~0 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|ptr_wr[0]~0 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|ptr_wr[0]~0 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|ptr_wr[0]~0 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|ptr_wr[0]~0 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|status_full~1 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|status_full~0 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|ptr_wr[1]~0 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|status_full~0 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|status_full~0 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|status_full~0 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|status_full~0 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broadcast_in_progress~0 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~110 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~109 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][5] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~108 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][5] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][5] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][5] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~107 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~106 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][6] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~105 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][6] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][6] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][6] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~34 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][7] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][7] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~34 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][7] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][7] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~34 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][7] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][7] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~34 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][7] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][7] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~33 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][8] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][8] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~33 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][8] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][8] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~33 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][8] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][8] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~33 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][8] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][8] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~32 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][40] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][40] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~32 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][40] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][40] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~32 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][40] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][40] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~32 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][40] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][40] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~31 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][39] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][39] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~31 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][39] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][39] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~31 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][39] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][39] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~31 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][39] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][39] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~30 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][38] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][38] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~30 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][38] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][38] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~30 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][38] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][38] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~30 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][38] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][38] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~29 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][37] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][37] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~29 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][37] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][37] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~29 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][37] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][37] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~29 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][37] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][37] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~28 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][36] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][36] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~28 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][36] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][36] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~28 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][36] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][36] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~28 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][36] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][36] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~27 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][35] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][35] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~27 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][35] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][35] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~27 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][35] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][35] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~27 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][35] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][35] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~26 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][34] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][34] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~26 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][34] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][34] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~26 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][34] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][34] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~26 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][34] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][34] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~25 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][33] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][33] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~25 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][33] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][33] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~25 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][33] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][33] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~25 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][33] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][33] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~24 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][32] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][32] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~24 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][32] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][32] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~24 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][32] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][32] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~24 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][32] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][32] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~23 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][31] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][31] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~23 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][31] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][31] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~23 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][31] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][31] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~23 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][31] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][31] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~22 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][30] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][30] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~22 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][30] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][30] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~22 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][30] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][30] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~22 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][30] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][30] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~21 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][29] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][29] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~21 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][29] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][29] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~21 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][29] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][29] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~21 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][29] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][29] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~20 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][28] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][28] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~20 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][28] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][28] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~20 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][28] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][28] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~20 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][28] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][28] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~19 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][27] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][27] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~19 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][27] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][27] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~19 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][27] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][27] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~19 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][27] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][27] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~18 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][26] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][26] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~18 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][26] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][26] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~18 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][26] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][26] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~18 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][26] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][26] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~17 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][25] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][25] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~17 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][25] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][25] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~17 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][25] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][25] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~17 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][25] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][25] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~16 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][24] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][24] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~16 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][24] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][24] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~16 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][24] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][24] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~16 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][24] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][24] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~15 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][23] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][23] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~15 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][23] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][23] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~15 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][23] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][23] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~15 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][23] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][23] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~14 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][22] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][22] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~14 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][22] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][22] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~14 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][22] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][22] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~14 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][22] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][22] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~13 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][21] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][21] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~13 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][21] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][21] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~13 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][21] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][21] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~13 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][21] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][21] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~12 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][20] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][20] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~12 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][20] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][20] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~12 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][20] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][20] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~12 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][20] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][20] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~11 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][19] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][19] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~11 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][19] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][19] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~11 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][19] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][19] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~11 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][19] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][19] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~10 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][18] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][18] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~10 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][18] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][18] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~10 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][18] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][18] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~10 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][18] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][18] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~9 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][17] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][17] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~9 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][17] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][17] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~9 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][17] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][17] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~9 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][17] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][17] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~8 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][16] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][16] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~8 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][16] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][16] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~8 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][16] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][16] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~8 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][16] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][16] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~7 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][15] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][15] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~7 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][15] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][15] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~7 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][15] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][15] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~7 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][15] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][15] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~6 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][14] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][14] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~6 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][14] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][14] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~6 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][14] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][14] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~6 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][14] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][14] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~5 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][13] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][13] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~5 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][13] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][13] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~5 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][13] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][13] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~5 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][13] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][13] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~4 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][12] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][12] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~4 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][12] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][12] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~4 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][12] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][12] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~4 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][12] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][12] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~3 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][11] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][11] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~3 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][11] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][11] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~3 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][11] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][11] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~3 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][11] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][11] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~2 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][10] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][10] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~2 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][10] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][10] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~2 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][10] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][10] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~2 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][10] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][10] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|status_empty~1 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|status_empty~0 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o~1 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][9] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][9] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o~1 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][9] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][9] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o~1 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][9] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][9] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o~1 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][9] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][9] ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|status_empty~0 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|status_empty~0 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|status_empty~0 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|status_empty~0 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[21]~104 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array~3 ; 1 ; -; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array~0 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array~4 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array~3 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array~2 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o~2 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o~1 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o~0 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_cmd3~1 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array~0 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array~11 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array~10 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array~9 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array~8 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array~7 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array~6 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array~5 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array~4 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array~3 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array~2 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array~1 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array~0 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~103 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~102 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][7] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~101 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][7] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][7] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][7] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~100 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~99 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][8] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~98 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][8] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][8] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][8] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~97 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~96 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][40] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~95 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][40] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][40] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][40] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~94 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~93 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][39] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~92 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][39] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][39] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][39] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~91 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~90 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][38] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~89 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][38] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][38] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][38] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~88 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~87 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][37] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~86 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][37] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][37] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][37] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~85 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~84 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][36] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~83 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][36] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][36] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][36] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~82 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~81 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][35] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~80 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][35] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][35] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][35] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~79 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~78 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][34] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~77 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][34] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][34] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][34] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~76 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~75 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][33] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~74 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][33] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][33] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][33] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~73 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~72 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][32] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~71 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][32] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][32] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][32] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~70 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~69 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][31] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~68 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][31] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][31] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][31] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~67 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~66 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][30] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~65 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][30] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][30] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][30] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~64 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~63 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][29] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~62 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][29] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][29] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][29] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~61 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~60 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][28] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~59 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][28] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][28] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][28] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~58 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~57 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][27] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~56 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][27] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][27] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][27] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~55 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~54 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][26] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~53 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][26] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][26] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][26] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~52 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~51 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][25] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~50 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][25] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][25] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][25] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~49 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~48 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][24] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~47 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][24] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][24] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][24] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~46 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~45 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][23] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~44 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][23] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][23] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][23] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~43 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~42 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][22] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~41 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][22] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][22] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][22] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~40 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~39 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][21] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~38 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][21] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][21] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][21] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~37 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~36 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][20] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~35 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][20] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][20] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][20] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~34 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~33 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[3][19] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~32 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[0][19] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[1][19] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|entry[2][19] ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~31 ; 1 ; -; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o~30 ; 1 ; -+--------------------------------------------------------------------------------------------------------------------------+---------+ - - -+---------------------------------------------------------------+ -; Interconnect Usage Summary ; -+-----------------------------------+---------------------------+ -; Interconnect Resource Type ; Usage ; -+-----------------------------------+---------------------------+ -; Block interconnects ; 1,490 / 232,464 ( < 1 % ) ; -; C16 interconnects ; 367 / 6,642 ( 6 % ) ; -; C4 interconnects ; 1,140 / 136,080 ( < 1 % ) ; -; Direct links ; 241 / 232,464 ( < 1 % ) ; -; GXB block output buffers ; 0 / 2,640 ( 0 % ) ; -; Global clocks ; 2 / 30 ( 7 % ) ; -; Interquad Reference Clock Outputs ; 0 / 2 ( 0 % ) ; -; Interquad TXRX Clocks ; 0 / 16 ( 0 % ) ; -; Interquad TXRX PCSRX outputs ; 0 / 8 ( 0 % ) ; -; Interquad TXRX PCSTX outputs ; 0 / 8 ( 0 % ) ; -; Local interconnects ; 345 / 73,920 ( < 1 % ) ; -; R24 interconnects ; 193 / 6,930 ( 3 % ) ; -; R4 interconnects ; 1,187 / 190,740 ( < 1 % ) ; -+-----------------------------------+---------------------------+ - - -+----------------------------------------------------------------------------+ -; LAB Logic Elements ; -+--------------------------------------------+-------------------------------+ -; Number of Logic Elements (Average = 5.70) ; Number of LABs (Total = 145) ; -+--------------------------------------------+-------------------------------+ -; 1 ; 26 ; -; 2 ; 34 ; -; 3 ; 13 ; -; 4 ; 15 ; -; 5 ; 3 ; -; 6 ; 6 ; -; 7 ; 5 ; -; 8 ; 5 ; -; 9 ; 1 ; -; 10 ; 8 ; -; 11 ; 3 ; -; 12 ; 0 ; -; 13 ; 6 ; -; 14 ; 5 ; -; 15 ; 2 ; -; 16 ; 13 ; -+--------------------------------------------+-------------------------------+ - - -+--------------------------------------------------------------------+ -; LAB-wide Signals ; -+------------------------------------+-------------------------------+ -; LAB-wide Signals (Average = 3.22) ; Number of LABs (Total = 145) ; -+------------------------------------+-------------------------------+ -; 1 Async. clear ; 142 ; -; 1 Clock ; 142 ; -; 1 Clock enable ; 102 ; -; 1 Sync. load ; 56 ; -; 2 Clock enables ; 25 ; -+------------------------------------+-------------------------------+ - - -+-----------------------------------------------------------------------------+ -; LAB Signals Sourced ; -+---------------------------------------------+-------------------------------+ -; Number of Signals Sourced (Average = 9.72) ; Number of LABs (Total = 145) ; -+---------------------------------------------+-------------------------------+ -; 0 ; 0 ; -; 1 ; 7 ; -; 2 ; 19 ; -; 3 ; 6 ; -; 4 ; 31 ; -; 5 ; 4 ; -; 6 ; 9 ; -; 7 ; 1 ; -; 8 ; 12 ; -; 9 ; 1 ; -; 10 ; 4 ; -; 11 ; 4 ; -; 12 ; 4 ; -; 13 ; 1 ; -; 14 ; 5 ; -; 15 ; 1 ; -; 16 ; 4 ; -; 17 ; 2 ; -; 18 ; 1 ; -; 19 ; 4 ; -; 20 ; 5 ; -; 21 ; 4 ; -; 22 ; 3 ; -; 23 ; 0 ; -; 24 ; 1 ; -; 25 ; 0 ; -; 26 ; 4 ; -; 27 ; 1 ; -; 28 ; 2 ; -; 29 ; 1 ; -; 30 ; 1 ; -; 31 ; 2 ; -; 32 ; 1 ; -+---------------------------------------------+-------------------------------+ - - -+---------------------------------------------------------------------------------+ -; LAB Signals Sourced Out ; -+-------------------------------------------------+-------------------------------+ -; Number of Signals Sourced Out (Average = 4.14) ; Number of LABs (Total = 145) ; -+-------------------------------------------------+-------------------------------+ -; 0 ; 0 ; -; 1 ; 39 ; -; 2 ; 33 ; -; 3 ; 16 ; -; 4 ; 12 ; -; 5 ; 7 ; -; 6 ; 9 ; -; 7 ; 5 ; -; 8 ; 6 ; -; 9 ; 1 ; -; 10 ; 2 ; -; 11 ; 4 ; -; 12 ; 3 ; -; 13 ; 2 ; -; 14 ; 2 ; -; 15 ; 1 ; -; 16 ; 2 ; -; 17 ; 0 ; -; 18 ; 1 ; -+-------------------------------------------------+-------------------------------+ - - -+------------------------------------------------------------------------------+ -; LAB Distinct Inputs ; -+----------------------------------------------+-------------------------------+ -; Number of Distinct Inputs (Average = 10.74) ; Number of LABs (Total = 145) ; -+----------------------------------------------+-------------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 24 ; -; 5 ; 18 ; -; 6 ; 14 ; -; 7 ; 20 ; -; 8 ; 3 ; -; 9 ; 12 ; -; 10 ; 3 ; -; 11 ; 4 ; -; 12 ; 5 ; -; 13 ; 4 ; -; 14 ; 3 ; -; 15 ; 5 ; -; 16 ; 1 ; -; 17 ; 0 ; -; 18 ; 4 ; -; 19 ; 2 ; -; 20 ; 2 ; -; 21 ; 1 ; -; 22 ; 2 ; -; 23 ; 2 ; -; 24 ; 0 ; -; 25 ; 4 ; -; 26 ; 3 ; -; 27 ; 2 ; -; 28 ; 4 ; -; 29 ; 2 ; -; 30 ; 0 ; -; 31 ; 0 ; -; 32 ; 0 ; -; 33 ; 1 ; -+----------------------------------------------+-------------------------------+ - - -+------------------------------------------+ -; I/O Rules Summary ; -+----------------------------------+-------+ -; I/O Rules Statistic ; Total ; -+----------------------------------+-------+ -; Total I/O Rules ; 30 ; -; Number of I/O Rules Passed ; 10 ; -; Number of I/O Rules Failed ; 0 ; -; Number of I/O Rules Unchecked ; 0 ; -; Number of I/O Rules Inapplicable ; 20 ; -+----------------------------------+-------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; I/O Rules Details ; -+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ -; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; -+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ -; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; -; Pass ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; -; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; -; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; -; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ; -; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; -; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; -; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; -; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; -; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; -; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; -; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; -; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; -; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; -; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; -; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; -; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; -; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; -; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; -; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; -; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; -+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; I/O Rules Matrix ; -+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ -; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; -+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ -; Total Pass ; 0 ; 36 ; 0 ; 0 ; 0 ; 194 ; 0 ; 0 ; 194 ; 194 ; 0 ; 48 ; 0 ; 0 ; 146 ; 0 ; 48 ; 146 ; 0 ; 0 ; 0 ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; 194 ; 0 ; 0 ; -; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; Total Inapplicable ; 194 ; 158 ; 194 ; 194 ; 194 ; 0 ; 194 ; 194 ; 0 ; 0 ; 194 ; 146 ; 194 ; 194 ; 48 ; 194 ; 146 ; 48 ; 194 ; 194 ; 194 ; 146 ; 194 ; 194 ; 194 ; 194 ; 194 ; 0 ; 194 ; 194 ; -; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; cbus_addr_o[0] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[1] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[2] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[3] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[4] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[5] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[6] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[7] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[8] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[9] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[10] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[11] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[12] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[13] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[14] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[15] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[16] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[17] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[18] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[19] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[20] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[21] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[22] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[23] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[24] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[25] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[26] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[27] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[28] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[29] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[30] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_addr_o[31] ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_cmd3_o[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_cmd3_o[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_cmd3_o[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_cmd2_o[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_cmd2_o[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_cmd2_o[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_cmd1_o[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_cmd1_o[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_cmd1_o[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_cmd0_o[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_cmd0_o[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_cmd0_o[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_ack3_o ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_ack2_o ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_ack1_o ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_ack0_o ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; clk ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; rst ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_ack3_i ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_ack2_i ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_ack1_i ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; cbus_ack0_i ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_cmd3_i[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_cmd3_i[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_cmd3_i[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_cmd2_i[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_cmd2_i[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_cmd2_i[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_cmd1_i[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_cmd1_i[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_cmd1_i[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_cmd0_i[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_cmd0_i[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_cmd0_i[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[16] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[16] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[16] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[16] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[17] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[17] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[17] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[17] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[18] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[18] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[18] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[18] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[19] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[19] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[19] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[19] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[20] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[20] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[20] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[20] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[21] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[21] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[21] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[21] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[22] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[22] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[22] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[22] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[23] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[23] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[23] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[23] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[24] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[24] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[24] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[24] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[25] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[25] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[25] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[25] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[26] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[26] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[26] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[26] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[27] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[27] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[27] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[27] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[28] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[28] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[28] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[28] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[29] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[29] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[29] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[29] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[30] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[30] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[30] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[30] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr2_i[31] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr3_i[31] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr0_i[31] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; mbus_addr1_i[31] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ - - -+-----------------------------------------------------------------------------------------------+ -; Fitter Device Options ; -+------------------------------------------------------------------+----------------------------+ -; Option ; Setting ; -+------------------------------------------------------------------+----------------------------+ -; Enable user-supplied start-up clock (CLKUSR) ; Off ; -; Enable device-wide reset (DEV_CLRn) ; Off ; -; Enable device-wide output enable (DEV_OE) ; Off ; -; Enable INIT_DONE output ; Off ; -; Configuration scheme ; Active Serial ; -; Error detection CRC ; Off ; -; Enable input tri-state on active configuration pins in user mode ; Off ; -; Active Serial clock source ; 40 MHz Internal Oscillator ; -; Configuration Voltage Level ; Auto ; -; Force Configuration Voltage Level ; Off ; -; nCEO ; As output driving ground ; -; Data[0] ; As input tri-stated ; -; Data[1]/ASDO ; As input tri-stated ; -; Data[7..2] ; Unreserved ; -; FLASH_nCE/nCSO ; As input tri-stated ; -; DCLK ; As output driving ground ; -; Base pin-out file on sameframe device ; Off ; -+------------------------------------------------------------------+----------------------------+ - - -+------------------------------------+ -; Operating Settings and Conditions ; -+---------------------------+--------+ -; Setting ; Value ; -+---------------------------+--------+ -; Nominal Core Voltage ; 1.20 V ; -; Low Junction Temperature ; 0 °C ; -; High Junction Temperature ; 85 °C ; -+---------------------------+--------+ - - -+------------------------------------------------------------+ -; Estimated Delay Added for Hold Timing Summary ; -+-----------------+----------------------+-------------------+ -; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; -+-----------------+----------------------+-------------------+ -; I/O ; clk ; 350.9 ; -+-----------------+----------------------+-------------------+ -Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. -This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer. - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Estimated Delay Added for Hold Timing Details ; -+------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+ -; Source Register ; Destination Register ; Delay Added in ns ; -+------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+ -; mbus_addr1_i[7] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][16] ; 1.871 ; -; mbus_addr1_i[17] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][26] ; 1.691 ; -; mbus_addr1_i[18] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][27] ; 1.662 ; -; mbus_cmd3_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[7] ; 1.604 ; -; mbus_cmd3_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[3]~_Duplicate_1 ; 1.590 ; -; mbus_cmd2_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[5] ; 1.568 ; -; mbus_cmd2_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[4] ; 1.568 ; -; mbus_addr0_i[30] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][39] ; 1.566 ; -; mbus_addr1_i[17] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][26] ; 1.565 ; -; mbus_addr1_i[17] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[26] ; 1.561 ; -; mbus_addr2_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][31] ; 1.558 ; -; mbus_addr0_i[15] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][24] ; 1.536 ; -; mbus_cmd3_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[6] ; 1.514 ; -; mbus_addr0_i[30] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][39] ; 1.500 ; -; mbus_addr1_i[18] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][27] ; 1.427 ; -; mbus_addr1_i[18] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[27] ; 1.423 ; -; mbus_cmd2_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[4] ; 1.418 ; -; mbus_cmd2_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[5] ; 1.417 ; -; mbus_addr0_i[7] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][16] ; 1.394 ; -; mbus_addr1_i[4] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][13] ; 1.390 ; -; mbus_cmd1_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[1]~_Duplicate_1 ; 1.388 ; -; mbus_cmd1_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[1]~_Duplicate_1 ; 1.369 ; -; mbus_addr2_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][21] ; 1.321 ; -; mbus_addr2_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][14] ; 1.317 ; -; mbus_cmd1_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[3] ; 1.315 ; -; mbus_cmd2_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[4] ; 1.312 ; -; mbus_cmd1_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[2] ; 1.306 ; -; mbus_cmd1_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[1]~_Duplicate_1 ; 1.302 ; -; mbus_cmd3_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[6] ; 1.300 ; -; mbus_addr2_i[19] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][28] ; 1.283 ; -; mbus_cmd2_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[2]~_Duplicate_1 ; 1.280 ; -; mbus_cmd0_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[1] ; 1.275 ; -; mbus_addr1_i[9] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][18] ; 1.274 ; -; mbus_cmd0_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[0] ; 1.260 ; -; mbus_addr1_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][14] ; 1.259 ; -; mbus_cmd0_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[0] ; 1.259 ; -; mbus_addr0_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][31] ; 1.236 ; -; mbus_addr0_i[8] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][17] ; 1.236 ; -; mbus_cmd1_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[2] ; 1.231 ; -; mbus_addr2_i[18] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][27] ; 1.223 ; -; mbus_addr3_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][14] ; 1.211 ; -; mbus_addr1_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][21] ; 1.211 ; -; mbus_addr1_i[10] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][19] ; 1.210 ; -; mbus_cmd3_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[3] ; 1.209 ; -; mbus_addr1_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][14] ; 1.208 ; -; mbus_addr3_i[31] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][40] ; 1.197 ; -; mbus_addr3_i[26] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][35] ; 1.184 ; -; mbus_cmd1_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[2] ; 1.178 ; -; mbus_addr2_i[13] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][22] ; 1.176 ; -; mbus_cmd2_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[5] ; 1.171 ; -; mbus_cmd3_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[7] ; 1.170 ; -; mbus_addr0_i[17] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][26] ; 1.170 ; -; mbus_addr3_i[25] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][34] ; 1.166 ; -; mbus_addr3_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][14] ; 1.164 ; -; mbus_cmd1_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[3] ; 1.161 ; -; mbus_addr3_i[25] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[34] ; 1.153 ; -; mbus_addr0_i[17] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][26] ; 1.143 ; -; mbus_addr0_i[17] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[26] ; 1.139 ; -; mbus_cmd2_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[2]~_Duplicate_1 ; 1.130 ; -; mbus_cmd0_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[1] ; 1.125 ; -; mbus_cmd0_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[1] ; 1.125 ; -; mbus_cmd0_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[0] ; 1.120 ; -; mbus_addr1_i[26] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][35] ; 1.118 ; -; mbus_addr0_i[11] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][20] ; 1.117 ; -; mbus_addr0_i[11] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[20] ; 1.112 ; -; mbus_addr1_i[9] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[18] ; 1.110 ; -; mbus_addr2_i[3] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][12] ; 1.107 ; -; mbus_addr3_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][21] ; 1.099 ; -; mbus_addr1_i[9] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][18] ; 1.085 ; -; mbus_addr1_i[25] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][34] ; 1.084 ; -; mbus_cmd1_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[3] ; 1.082 ; -; mbus_addr2_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][11] ; 1.081 ; -; mbus_addr1_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][9] ; 1.067 ; -; mbus_addr1_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][9] ; 1.066 ; -; mbus_addr2_i[4] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][13] ; 1.061 ; -; mbus_addr1_i[15] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][24] ; 1.057 ; -; mbus_addr1_i[16] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][25] ; 1.056 ; -; mbus_addr2_i[30] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][39] ; 1.055 ; -; mbus_addr1_i[28] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][37] ; 1.050 ; -; mbus_addr2_i[19] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][28] ; 1.049 ; -; mbus_addr2_i[20] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][29] ; 1.045 ; -; mbus_addr0_i[13] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][22] ; 1.038 ; -; mbus_addr3_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[21] ; 1.038 ; -; mbus_addr0_i[11] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][20] ; 1.036 ; -; mbus_addr3_i[25] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][34] ; 1.036 ; -; mbus_addr0_i[10] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][19] ; 1.035 ; -; mbus_addr3_i[15] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][24] ; 1.033 ; -; mbus_addr1_i[26] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][35] ; 1.030 ; -; mbus_cmd3_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[3]~_Duplicate_1 ; 1.030 ; -; mbus_addr2_i[29] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][38] ; 1.029 ; -; mbus_addr1_i[4] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][13] ; 1.028 ; -; mbus_addr3_i[7] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][16] ; 1.028 ; -; mbus_addr1_i[28] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[37] ; 1.025 ; -; mbus_addr1_i[26] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[35] ; 1.025 ; -; mbus_addr1_i[16] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][25] ; 1.024 ; -; mbus_cmd2_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[2]~_Duplicate_1 ; 1.024 ; -; mbus_addr1_i[19] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][28] ; 1.024 ; -; mbus_addr1_i[4] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[13] ; 1.023 ; -; mbus_addr1_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][11] ; 1.021 ; -; mbus_addr0_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[31] ; 1.021 ; -+------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+ - - -+-----------------+ -; Fitter Messages ; -+-----------------+ -Info: ******************************************************************* -Info: Running Quartus II 32-bit Fitter - Info: Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition - Info: Processing started: Tue Dec 25 13:54:15 2012 -Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off mesi_isc -c mesi_isc -Warning (20028): Parallel compilation is not licensed and has been disabled -Info (119004): Automatically selected device EP4CGX30CF23C6 for design mesi_isc -Info (119005): Fitting design with smaller device may be possible, but smaller device must be specified -Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'. -Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'. -Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time -Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. -Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices - Info (176445): Device EP4CGX75CF23C6 is compatible - Info (176445): Device EP4CGX50CF23C6 is compatible -Info (169124): Fitter converted 5 user pins into dedicated programming pins - Info (169125): Pin ~ALTERA_NCEO~ is reserved at location AB3 - Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K4 - Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1 - Info (169125): Pin ~ALTERA_NCSO~ is reserved at location J4 - Info (169125): Pin ~ALTERA_DCLK~ is reserved at location D3 -Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details -Critical Warning (169085): No exact pin location assignment(s) for 194 pins of 194 total pins - Info (169086): Pin cbus_addr_o[0] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[1] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[2] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[3] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[4] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[5] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[6] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[7] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[8] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[9] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[10] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[11] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[12] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[13] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[14] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[15] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[16] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[17] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[18] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[19] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[20] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[21] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[22] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[23] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[24] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[25] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[26] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[27] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[28] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[29] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[30] not assigned to an exact location on the device - Info (169086): Pin cbus_addr_o[31] not assigned to an exact location on the device - Info (169086): Pin cbus_cmd3_o[0] not assigned to an exact location on the device - Info (169086): Pin cbus_cmd3_o[1] not assigned to an exact location on the device - Info (169086): Pin cbus_cmd3_o[2] not assigned to an exact location on the device - Info (169086): Pin cbus_cmd2_o[0] not assigned to an exact location on the device - Info (169086): Pin cbus_cmd2_o[1] not assigned to an exact location on the device - Info (169086): Pin cbus_cmd2_o[2] not assigned to an exact location on the device - Info (169086): Pin cbus_cmd1_o[0] not assigned to an exact location on the device - Info (169086): Pin cbus_cmd1_o[1] not assigned to an exact location on the device - Info (169086): Pin cbus_cmd1_o[2] not assigned to an exact location on the device - Info (169086): Pin cbus_cmd0_o[0] not assigned to an exact location on the device - Info (169086): Pin cbus_cmd0_o[1] not assigned to an exact location on the device - Info (169086): Pin cbus_cmd0_o[2] not assigned to an exact location on the device - Info (169086): Pin mbus_ack3_o not assigned to an exact location on the device - Info (169086): Pin mbus_ack2_o not assigned to an exact location on the device - Info (169086): Pin mbus_ack1_o not assigned to an exact location on the device - Info (169086): Pin mbus_ack0_o not assigned to an exact location on the device - Info (169086): Pin clk not assigned to an exact location on the device - Info (169086): Pin rst not assigned to an exact location on the device - Info (169086): Pin cbus_ack3_i not assigned to an exact location on the device - Info (169086): Pin cbus_ack2_i not assigned to an exact location on the device - Info (169086): Pin cbus_ack1_i not assigned to an exact location on the device - Info (169086): Pin cbus_ack0_i not assigned to an exact location on the device - Info (169086): Pin mbus_cmd3_i[0] not assigned to an exact location on the device - Info (169086): Pin mbus_cmd3_i[2] not assigned to an exact location on the device - Info (169086): Pin mbus_cmd3_i[1] not assigned to an exact location on the device - Info (169086): Pin mbus_cmd2_i[0] not assigned to an exact location on the device - Info (169086): Pin mbus_cmd2_i[1] not assigned to an exact location on the device - Info (169086): Pin mbus_cmd2_i[2] not assigned to an exact location on the device - Info (169086): Pin mbus_cmd1_i[2] not assigned to an exact location on the device - Info (169086): Pin mbus_cmd1_i[0] not assigned to an exact location on the device - Info (169086): Pin mbus_cmd1_i[1] not assigned to an exact location on the device - Info (169086): Pin mbus_cmd0_i[0] not assigned to an exact location on the device - Info (169086): Pin mbus_cmd0_i[1] not assigned to an exact location on the device - Info (169086): Pin mbus_cmd0_i[2] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[0] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[0] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[0] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[0] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[1] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[1] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[1] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[1] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[2] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[2] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[2] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[2] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[3] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[3] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[3] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[3] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[4] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[4] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[4] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[4] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[5] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[5] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[5] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[5] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[6] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[6] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[6] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[6] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[7] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[7] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[7] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[7] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[8] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[8] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[8] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[8] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[9] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[9] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[9] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[9] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[10] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[10] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[10] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[10] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[11] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[11] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[11] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[11] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[12] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[12] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[12] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[12] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[13] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[13] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[13] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[13] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[14] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[14] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[14] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[14] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[15] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[15] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[15] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[15] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[16] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[16] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[16] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[16] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[17] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[17] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[17] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[17] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[18] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[18] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[18] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[18] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[19] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[19] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[19] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[19] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[20] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[20] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[20] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[20] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[21] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[21] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[21] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[21] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[22] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[22] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[22] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[22] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[23] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[23] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[23] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[23] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[24] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[24] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[24] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[24] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[25] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[25] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[25] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[25] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[26] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[26] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[26] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[26] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[27] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[27] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[27] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[27] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[28] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[28] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[28] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[28] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[29] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[29] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[29] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[29] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[30] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[30] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[30] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[30] not assigned to an exact location on the device - Info (169086): Pin mbus_addr2_i[31] not assigned to an exact location on the device - Info (169086): Pin mbus_addr3_i[31] not assigned to an exact location on the device - Info (169086): Pin mbus_addr0_i[31] not assigned to an exact location on the device - Info (169086): Pin mbus_addr1_i[31] not assigned to an exact location on the device -Info (332104): Reading SDC File: 'mesi_isc.sdc' -Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. -Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements -Info (332111): Found 1 clocks - Info (332111): Period Clock Name - Info (332111): ======== ============ - Info (332111): 1.000 clk -Info (176353): Automatically promoted node clk~input (placed in PIN N11 (CLKIO13, DIFFCLK_7n, REFCLK2n)) - Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G29 -Info (176353): Automatically promoted node rst~input (placed in PIN M11 (CLKIO12, DIFFCLK_7p, REFCLK2p)) - Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G28 -Info (176233): Starting register packing -Extra Info (176273): Performing register packing on registers with non-logic cell location assignments -Extra Info (176274): Completed register packing on registers with non-logic cell location assignments -Extra Info (176236): Started Fast Input/Output/OE register processing -Extra Info (176237): Finished Fast Input/Output/OE register processing -Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density -Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks -Info (176235): Finished register packing - Extra Info (176218): Packed 36 registers into blocks of type I/O Output Buffer - Extra Info (176220): Created 4 register duplicates -Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement - Info (176211): Number of I/O pins in group: 192 (unused VREF, 2.5V VCCIO, 144 input, 48 output, 0 bidirectional) - Info (176212): I/O standards used: 2.5 V. -Info (176215): I/O bank details before I/O pin placement - Info (176214): Statistics of I/O banks - Info (176213): I/O bank number QL1 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 0 pins available - Info (176213): I/O bank number QL0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 0 pins available - Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 45 pins available - Info (176213): I/O bank number 3B does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 2 pins available - Info (176213): I/O bank number 3A does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 0 pins available - Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 45 pins available - Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 49 pins available - Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 49 pins available - Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 46 pins available - Info (176213): I/O bank number 8A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 2 pins available - Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 44 pins available - Info (176213): I/O bank number 8B does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 0 pins available - Info (176213): I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 0 pins available -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:04 -Info (170189): Fitter placement preparation operations beginning -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 -Info (170191): Fitter placement operations beginning -Info (170137): Fitter placement was successful -Info (170192): Fitter placement operations ending: elapsed time is 00:00:11 -Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 1% of the available device resources - Info (170196): Router estimated peak interconnect usage is 9% of the available device resources in the region that extends from location X58_Y22 to location X69_Y33 -Info (170194): Fitter routing operations ending: elapsed time is 00:00:05 -Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. - Info (170201): Optimizations that may affect the design's routability were skipped -Info (334003): Started post-fitting delay annotation -Info (334004): Delay annotation completed successfully -Info (334003): Started post-fitting delay annotation -Info (334004): Delay annotation completed successfully -Warning (169177): 2 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV GX Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. - Info (169178): Pin clk uses I/O standard 2.5 V at N11 - Info (169178): Pin rst uses I/O standard 2.5 V at M11 -Info: Quartus II 32-bit Fitter was successful. 0 errors, 5 warnings - Info: Peak virtual memory: 574 megabytes - Info: Processing ended: Tue Dec 25 13:54:52 2012 - Info: Elapsed time: 00:00:37 - Info: Total CPU time (on all processors): 00:00:37 - - Index: syn/mesi_isc.qpf =================================================================== --- syn/mesi_isc.qpf (revision 4) +++ syn/mesi_isc.qpf (nonexistent) @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2012 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 32-bit -# Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition -# Date created = 09:58:58 November 06, 2012 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "12.0" -DATE = "09:58:58 November 06, 2012" - -# Revisions - -PROJECT_REVISION = "mesi_isc" Index: syn/mesi_isc.pin =================================================================== --- syn/mesi_isc.pin (revision 4) +++ syn/mesi_isc.pin (nonexistent) @@ -1,561 +0,0 @@ - -- Copyright (C) 1991-2012 Altera Corporation - -- Your use of Altera Corporation's design tools, logic functions - -- and other software and tools, and its AMPP partner logic - -- functions, and any output files from any of the foregoing - -- (including device programming or simulation files), and any - -- associated documentation or information are expressly subject - -- to the terms and conditions of the Altera Program License - -- Subscription Agreement, Altera MegaCore Function License - -- Agreement, or other applicable license agreement, including, - -- without limitation, that your use is for the sole purpose of - -- programming logic devices manufactured by Altera and sold by - -- Altera or its authorized distributors. Please refer to the - -- applicable agreement for further details. - -- - -- This is a Quartus II output file. It is for reporting purposes only, and is - -- not intended for use as a Quartus II input file. This file cannot be used - -- to make Quartus II pin assignments - for instructions on how to make pin - -- assignments, please see Quartus II help. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- NC : No Connect. This pin has no internal connection to the device. - -- DNU : Do Not Use. This pin MUST NOT be connected. - -- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V or 3.0V depending on the requirements of the configuration device. - -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). - -- VCCIO : Dedicated power pin, which MUST be connected to VCC - -- of its bank. - -- Bank 3: 2.5V - -- Bank 4: 2.5V - -- Bank 5: 2.5V - -- Bank 6: 2.5V - -- Bank 7: 2.5V - -- Bank 8: 2.5V - -- Bank 9: 2.5V - -- RREF : External reference resistor for the quad, MUST be connected to - -- GND via a 2k Ohm resistor. - -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. - -- It can also be used to report unused dedicated pins. The connection - -- on the board for unused dedicated pins depends on whether this will - -- be used in a future design. One example is device migration. When - -- using device migration, refer to the device pin-tables. If it is a - -- GND pin in the pin table or if it will not be used in a future design - -- for another purpose the it MUST be connected to GND. If it is an unused - -- dedicated pin, then it can be connected to a valid signal on the board - -- (low, high, or toggling) if that signal is required for a different - -- revision of the design. - -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. - -- This pin should be connected to GND. It may also be connected to a - -- valid signal on the board (low, high, or toggling) if that signal - -- is required for a different revision of the design. - -- GND* : Unused I/O pin. For transceiver I/O banks, connect each pin marked GND* - -- either individually through a 10k Ohm resistor to GND or tie all pins - -- together and connect through a single 10k Ohm resistor to GND. - -- RESERVED : Unused I/O pin, which MUST be left unconnected. - -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. - -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. - -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. - -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. - -- GXB_GND* : Unused GXB Receiver or dedicated reference clock pin. This pin - -- must be connected to GXB_GND through a 10k Ohm resistor. - -- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin - -- must not be connected. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- Pin directions (input, output or bidir) are based on device operating in user mode. - --------------------------------------------------------------------------------- - -Quartus II 32-bit Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition -CHIP "mesi_isc" ASSIGNED TO AN: EP4CGX30CF23C6 - -Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment -------------------------------------------------------------------------------------------------------------- -RESERVED_INPUT_WITH_WEAK_PULLUP : A1 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 : -GND+ : A9 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 : -mbus_addr2_i[7] : A11 : input : 2.5 V : : 7 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7 : -mbus_addr3_i[18] : A13 : input : 2.5 V : : 7 : N -mbus_addr2_i[15] : A14 : input : 2.5 V : : 7 : N -mbus_addr2_i[12] : A15 : input : 2.5 V : : 7 : N -cbus_addr_o[6] : A16 : output : 2.5 V : : 7 : N -mbus_addr3_i[15] : A17 : input : 2.5 V : : 7 : N -mbus_addr1_i[13] : A18 : input : 2.5 V : : 7 : N -cbus_addr_o[29] : A19 : output : 2.5 V : : 7 : N -mbus_addr1_i[8] : A20 : input : 2.5 V : : 6 : N -cbus_addr_o[12] : A21 : output : 2.5 V : : 6 : N -mbus_addr2_i[0] : A22 : input : 2.5 V : : 6 : N -GND : AA1 : gnd : : : : -GND : AA2 : gnd : : : : -NC : AA3 : : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 3 : -GND : AA5 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3 : -mbus_addr0_i[30] : AA7 : input : 2.5 V : : 3 : N -GND : AA8 : gnd : : : : -mbus_addr0_i[15] : AA9 : input : 2.5 V : : 3 : N -mbus_addr0_i[4] : AA10 : input : 2.5 V : : 3 : N -GND : AA11 : gnd : : : : -cbus_ack3_i : AA12 : input : 2.5 V : : 4 : N -mbus_addr3_i[17] : AA13 : input : 2.5 V : : 4 : N -GND : AA14 : gnd : : : : -mbus_ack0_o : AA15 : output : 2.5 V : : 4 : N -mbus_cmd0_i[0] : AA16 : input : 2.5 V : : 4 : N -GND : AA17 : gnd : : : : -mbus_addr3_i[23] : AA18 : input : 2.5 V : : 4 : N -mbus_addr1_i[15] : AA19 : input : 2.5 V : : 4 : N -cbus_addr_o[27] : AA20 : output : 2.5 V : : 4 : N -mbus_addr2_i[30] : AA21 : input : 2.5 V : : 4 : N -cbus_cmd2_o[2] : AA22 : output : 2.5 V : : 4 : N -RREF : AB1 : : : : : -GND : AB2 : gnd : : : : -~ALTERA_NCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : AB3 : output : 2.5 V : : 3 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 : -mbus_addr0_i[25] : AB5 : input : 2.5 V : : 3 : N -mbus_addr0_i[28] : AB6 : input : 2.5 V : : 3 : N -mbus_addr0_i[26] : AB7 : input : 2.5 V : : 3 : N -mbus_addr0_i[3] : AB8 : input : 2.5 V : : 3 : N -mbus_addr0_i[2] : AB9 : input : 2.5 V : : 3 : N -mbus_addr0_i[6] : AB10 : input : 2.5 V : : 3 : N -mbus_addr0_i[19] : AB11 : input : 2.5 V : : 3 : N -cbus_ack2_i : AB12 : input : 2.5 V : : 4 : N -mbus_addr3_i[24] : AB13 : input : 2.5 V : : 4 : N -mbus_addr3_i[6] : AB14 : input : 2.5 V : : 4 : N -cbus_addr_o[28] : AB15 : output : 2.5 V : : 4 : N -mbus_addr3_i[31] : AB16 : input : 2.5 V : : 4 : N -cbus_addr_o[23] : AB17 : output : 2.5 V : : 4 : N -mbus_addr0_i[21] : AB18 : input : 2.5 V : : 4 : N -cbus_addr_o[22] : AB19 : output : 2.5 V : : 4 : N -cbus_addr_o[0] : AB20 : output : 2.5 V : : 4 : N -mbus_addr1_i[28] : AB21 : input : 2.5 V : : 4 : N -mbus_cmd1_i[0] : AB22 : input : 2.5 V : : 4 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8 : -GND : B2 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : -GND : B5 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : -GND : B8 : gnd : : : : -GND+ : B9 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 : -GND : B11 : gnd : : : : -cbus_addr_o[2] : B12 : output : 2.5 V : : 7 : N -cbus_addr_o[20] : B13 : output : 2.5 V : : 7 : N -GND : B14 : gnd : : : : -cbus_addr_o[26] : B15 : output : 2.5 V : : 7 : N -mbus_addr2_i[25] : B16 : input : 2.5 V : : 7 : N -GND : B17 : gnd : : : : -cbus_cmd3_o[0] : B18 : output : 2.5 V : : 7 : N -mbus_addr2_i[13] : B19 : input : 2.5 V : : 6 : N -mbus_addr2_i[6] : B20 : input : 2.5 V : : 6 : N -mbus_addr1_i[19] : B21 : input : 2.5 V : : 6 : N -mbus_addr2_i[14] : B22 : input : 2.5 V : : 6 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 : -mbus_addr2_i[20] : C10 : input : 2.5 V : : 7 : N -mbus_addr3_i[0] : C11 : input : 2.5 V : : 7 : N -mbus_addr2_i[10] : C12 : input : 2.5 V : : 7 : N -mbus_addr2_i[9] : C13 : input : 2.5 V : : 7 : N -cbus_addr_o[21] : C14 : output : 2.5 V : : 7 : N -cbus_addr_o[24] : C15 : output : 2.5 V : : 7 : N -cbus_addr_o[4] : C16 : output : 2.5 V : : 7 : N -cbus_cmd2_o[1] : C17 : output : 2.5 V : : 7 : N -cbus_cmd0_o[0] : C18 : output : 2.5 V : : 7 : N -mbus_addr1_i[22] : C19 : input : 2.5 V : : 6 : N -mbus_addr1_i[24] : C20 : input : 2.5 V : : 6 : N -GND : C21 : gnd : : : : -cbus_cmd2_o[0] : C22 : output : 2.5 V : : 6 : N -~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : input : 2.5 V : : 9 : N -nCE : D2 : : : : 9 : -~ALTERA_DCLK~ : D3 : output : 2.5 V : : 9 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 : -mbus_addr2_i[5] : D13 : input : 2.5 V : : 7 : N -mbus_addr2_i[8] : D14 : input : 2.5 V : : 7 : N -mbus_addr3_i[28] : D15 : input : 2.5 V : : 7 : N -mbus_addr3_i[12] : D16 : input : 2.5 V : : 7 : N -cbus_addr_o[13] : D17 : output : 2.5 V : : 7 : N -GND : D18 : gnd : : : : -mbus_addr1_i[14] : D19 : input : 2.5 V : : 6 : N -mbus_addr2_i[22] : D20 : input : 2.5 V : : 6 : N -cbus_addr_o[15] : D21 : output : 2.5 V : : 6 : N -mbus_addr2_i[16] : D22 : input : 2.5 V : : 6 : N -GND : E1 : gnd : : : : -GND : E2 : gnd : : : : -TDO : E3 : output : : : 9 : -TCK : E4 : input : : : 9 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : -GND : E7 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : -VCCIO8 : E9 : power : : 2.5V : 8 : -VCCIO8 : E10 : power : : 2.5V : 8 : -VCCIO8 : E11 : power : : 2.5V : 8 : -VCCIO8 : E12 : power : : 2.5V : 8 : -VCCIO7 : E13 : power : : 2.5V : 7 : -VCCIO7 : E14 : power : : 2.5V : 7 : -VCCIO7 : E15 : power : : 2.5V : 7 : -VCCIO7 : E16 : power : : 2.5V : 7 : -cbus_addr_o[5] : E17 : output : 2.5 V : : 7 : N -VCCD_PLL : E18 : power : : 1.2V : : -GND : E19 : gnd : : : : -mbus_addr1_i[9] : E20 : input : 2.5 V : : 6 : N -cbus_cmd0_o[1] : E21 : output : 2.5 V : : 6 : N -mbus_addr3_i[21] : E22 : input : 2.5 V : : 6 : N -GXB_NC : F1 : : : : QL0 : -GXB_NC : F2 : : : : QL0 : -GND : F3 : gnd : : : : -VCCA : F4 : power : : 2.5V : : -TDI : F5 : input : : : 9 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8 : -VCCINT : F7 : power : : 1.2V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 : -GND : F9 : gnd : : : : -VCCIO8 : F10 : power : : 2.5V : 8 : -GND : F11 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 7 : -GND : F13 : gnd : : : : -VCCIO7 : F14 : power : : 2.5V : 7 : -GND : F15 : gnd : : : : -cbus_cmd1_o[0] : F16 : output : 2.5 V : : 7 : N -mbus_addr1_i[16] : F17 : input : 2.5 V : : 7 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 6 : -VCCA : F19 : power : : 2.5V : : -mbus_addr1_i[23] : F20 : input : 2.5 V : : 6 : N -GND : F21 : gnd : : : : -mbus_addr3_i[9] : F22 : input : 2.5 V : : 6 : N -GND : G1 : gnd : : : : -GND : G2 : gnd : : : : -VCCD_PLL : G3 : power : : 1.2V : : -VCCIO9 : G4 : power : : 2.5V : 9 : -TMS : G5 : input : : : 9 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 : -VCCINT : G9 : power : : 1.2V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 7 : -VCCINT : G13 : power : : 1.2V : : -mbus_addr3_i[1] : G14 : input : 2.5 V : : 7 : N -mbus_addr3_i[13] : G15 : input : 2.5 V : : 7 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 : -mbus_addr1_i[0] : G18 : input : 2.5 V : : 6 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 6 : -cbus_addr_o[8] : G20 : output : 2.5 V : : 6 : N -mbus_cmd2_i[0] : G21 : input : 2.5 V : : 6 : N -cbus_cmd1_o[1] : G22 : output : 2.5 V : : 6 : N -GXB_GND* : H1 : : : : QL0 : -GXB_GND* : H2 : : : : QL0 : -VCCH_GXB : H3 : power : : 2.5V : : -nCONFIG : H4 : : : : 9 : -GND : H5 : gnd : : : : -VCCINT : H6 : power : : 1.2V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H9 : : : : 8 : -VCC_CLKIN8A : H10 : power : : 2.5V : 8A : -GND : H11 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7 : -mbus_addr2_i[1] : H13 : input : 2.5 V : : 7 : N -mbus_addr2_i[2] : H14 : input : 2.5 V : : 7 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 6 : -mbus_addr2_i[11] : H17 : input : 2.5 V : : 6 : N -GND : H18 : gnd : : : : -VCCIO6 : H19 : power : : 2.5V : 6 : -cbus_addr_o[14] : H20 : output : 2.5 V : : 6 : N -mbus_addr1_i[5] : H21 : input : 2.5 V : : 6 : N -cbus_addr_o[7] : H22 : output : 2.5 V : : 6 : N -GND : J1 : gnd : : : : -GND : J2 : gnd : : : : -VCCA_GXB : J3 : power : : 2.5V : : -~ALTERA_NCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : input : 2.5 V : : 9 : N -VCCINT : J5 : power : : 1.2V : : -GND : J6 : gnd : : : : -VCCINT : J7 : power : : 1.2V : : -GND : J8 : gnd : : : : -VCCINT : J9 : power : : 1.2V : : -GXB_GND* : J10 : : : : 8A : -VCCINT : J11 : power : : 1.2V : : -mbus_addr2_i[3] : J12 : input : 2.5 V : : 7 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 7 : -cbus_addr_o[18] : J14 : output : 2.5 V : : 7 : N -mbus_addr1_i[2] : J15 : input : 2.5 V : : 6 : N -mbus_addr1_i[21] : J16 : input : 2.5 V : : 6 : N -VCCINT : J17 : power : : 1.2V : : -VCCIO6 : J18 : power : : 2.5V : 6 : -cbus_ack1_i : J19 : input : 2.5 V : : 6 : N -cbus_cmd3_o[1] : J20 : output : 2.5 V : : 6 : N -cbus_cmd1_o[2] : J21 : output : 2.5 V : : 6 : N -cbus_addr_o[30] : J22 : output : 2.5 V : : 6 : N -GXB_NC : K1 : : : : QL0 : -GXB_NC : K2 : : : : QL0 : -VCCL_GXB : K3 : power : : 1.2V : : -~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : input : 2.5 V : : 9 : N -GND : K5 : gnd : : : : -VCCINT : K6 : power : : 1.2V : : -GND : K7 : gnd : : : : -VCCINT : K8 : power : : 1.2V : : -GND : K9 : gnd : : : : -GXB_GND* : K10 : : : : 8A : -GND : K11 : gnd : : : : -mbus_addr2_i[4] : K12 : input : 2.5 V : : 7 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : K13 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 6 : -GND : K15 : gnd : : : : -VCCINT : K16 : power : : 1.2V : : -mbus_addr1_i[20] : K17 : input : 2.5 V : : 6 : N -VCCIO6 : K18 : power : : 2.5V : 6 : -mbus_cmd2_i[1] : K19 : input : 2.5 V : : 6 : N -mbus_cmd2_i[2] : K20 : input : 2.5 V : : 6 : N -GND : K21 : gnd : : : : -mbus_ack2_o : K22 : output : 2.5 V : : 6 : N -GND : L1 : gnd : : : : -GND : L2 : gnd : : : : -VCCL_GXB : L3 : power : : 1.2V : : -VCCA : L4 : power : : 2.5V : : -VCCINT : L5 : power : : 1.2V : : -GND : L6 : gnd : : : : -VCCINT : L7 : power : : 1.2V : : -GND : L8 : gnd : : : : -VCCINT : L9 : power : : 1.2V : : -GND : L10 : gnd : : : : -VCCINT : L11 : power : : 1.2V : : -GND : L12 : gnd : : : : -mbus_addr1_i[4] : L13 : input : 2.5 V : : 5 : N -mbus_addr1_i[30] : L14 : input : 2.5 V : : 5 : N -mbus_addr0_i[11] : L15 : input : 2.5 V : : 5 : N -mbus_cmd3_i[0] : L16 : input : 2.5 V : : 5 : N -VCCINT : L17 : power : : 1.2V : : -GND : L18 : gnd : : : : -cbus_cmd3_o[2] : L19 : output : 2.5 V : : 6 : N -cbus_cmd0_o[2] : L20 : output : 2.5 V : : 6 : N -mbus_addr2_i[19] : L21 : input : 2.5 V : : 6 : N -mbus_addr1_i[18] : L22 : input : 2.5 V : : 6 : N -GXB_GND* : M1 : : : : QL0 : -GXB_GND* : M2 : : : : QL0 : -GND : M3 : gnd : : : : -VCCD_PLL : M4 : power : : 1.2V : : -GND : M5 : gnd : : : : -VCCINT : M6 : power : : 1.2V : : -GXB_GND* : M7 : : : : 3B : -GXB_GND* : M8 : : : : 3B : -GND : M9 : gnd : : : : -VCCINT : M10 : power : : 1.2V : : -rst : M11 : input : 2.5 V : : 3A : N -VCCINT : M12 : power : : 1.2V : : -cbus_addr_o[16] : M13 : output : 2.5 V : : 5 : N -mbus_addr3_i[26] : M14 : input : 2.5 V : : 5 : N -mbus_addr1_i[6] : M15 : input : 2.5 V : : 5 : N -mbus_ack3_o : M16 : output : 2.5 V : : 5 : N -mbus_addr1_i[27] : M17 : input : 2.5 V : : 5 : N -cbus_addr_o[1] : M18 : output : 2.5 V : : 5 : N -cbus_addr_o[10] : M19 : output : 2.5 V : : 5 : N -mbus_cmd3_i[2] : M20 : input : 2.5 V : : 5 : N -mbus_addr1_i[17] : M21 : input : 2.5 V : : 5 : N -mbus_addr0_i[17] : M22 : input : 2.5 V : : 5 : N -GND : N1 : gnd : : : : -GND : N2 : gnd : : : : -VCCL_GXB : N3 : power : : 1.2V : : -GND : N4 : gnd : : : : -VCCINT : N5 : power : : 1.2V : : -GND : N6 : gnd : : : : -GXB_GND* : N7 : : : : 3B : -GXB_GND* : N8 : : : : 3B : -VCCINT : N9 : power : : 1.2V : : -GND : N10 : gnd : : : : -clk : N11 : input : 2.5 V : : 3A : N -VCC_CLKIN3A : N12 : power : : 2.5V : 3A : -mbus_addr3_i[5] : N13 : input : 2.5 V : : 5 : N -mbus_addr3_i[10] : N14 : input : 2.5 V : : 5 : N -mbus_addr2_i[23] : N15 : input : 2.5 V : : 5 : N -VCCINT : N16 : power : : 1.2V : : -mbus_addr2_i[18] : N17 : input : 2.5 V : : 5 : N -VCCIO5 : N18 : power : : 2.5V : 5 : -mbus_cmd3_i[1] : N19 : input : 2.5 V : : 5 : N -mbus_addr1_i[12] : N20 : input : 2.5 V : : 5 : N -mbus_addr2_i[17] : N21 : input : 2.5 V : : 5 : N -mbus_addr2_i[28] : N22 : input : 2.5 V : : 5 : N -GXB_NC : P1 : : : : QL0 : -GXB_NC : P2 : : : : QL0 : -VCCH_GXB : P3 : power : : 2.5V : : -MSEL3 : P4 : : : : 3 : -MSEL1 : P5 : : : : 3 : -VCCINT : P6 : power : : 1.2V : : -VCC_CLKIN3B : P7 : power : : 2.5V : 3B : -VCCINT : P8 : power : : 1.2V : : -GND : P9 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3 : -GND : P11 : gnd : : : : -VCCINT : P12 : power : : 1.2V : : -mbus_addr1_i[29] : P13 : input : 2.5 V : : 5 : N -mbus_addr2_i[27] : P14 : input : 2.5 V : : 5 : N -mbus_addr3_i[4] : P15 : input : 2.5 V : : 5 : N -GND : P16 : gnd : : : : -VCCINT : P17 : power : : 1.2V : : -GND : P18 : gnd : : : : -VCCIO5 : P19 : power : : 2.5V : 5 : -mbus_addr1_i[7] : P20 : input : 2.5 V : : 5 : N -GND : P21 : gnd : : : : -mbus_addr1_i[10] : P22 : input : 2.5 V : : 5 : N -GND : R1 : gnd : : : : -GND : R2 : gnd : : : : -VCCA_GXB : R3 : power : : 2.5V : : -VCCD_PLL : R4 : power : : 1.2V : : -MSEL2 : R5 : : : : 3 : -GND : R6 : gnd : : : : -VCCINT : R7 : power : : 1.2V : : -nSTATUS : R8 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 : -GND : R12 : gnd : : : : -mbus_addr0_i[27] : R13 : input : 2.5 V : : 4 : N -cbus_addr_o[17] : R14 : output : 2.5 V : : 4 : N -mbus_addr3_i[30] : R15 : input : 2.5 V : : 4 : N -mbus_addr1_i[25] : R16 : input : 2.5 V : : 5 : N -mbus_addr3_i[20] : R17 : input : 2.5 V : : 5 : N -VCCIO5 : R18 : power : : 2.5V : 5 : -mbus_addr2_i[29] : R19 : input : 2.5 V : : 5 : N -mbus_addr0_i[13] : R20 : input : 2.5 V : : 5 : N -mbus_addr2_i[26] : R21 : input : 2.5 V : : 5 : N -mbus_addr3_i[14] : R22 : input : 2.5 V : : 5 : N -GXB_GND* : T1 : : : : QL0 : -GXB_GND* : T2 : : : : QL0 : -VCCL_GXB : T3 : power : : 1.2V : : -GND : T4 : gnd : : : : -VCCA : T5 : power : : 2.5V : : -MSEL0 : T6 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T9 : : : : 3 : -VCCINT : T10 : power : : 1.2V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 3 : -VCCINT : T12 : power : : 1.2V : : -cbus_addr_o[31] : T13 : output : 2.5 V : : 4 : N -mbus_addr3_i[2] : T14 : input : 2.5 V : : 4 : N -mbus_addr3_i[25] : T15 : input : 2.5 V : : 4 : N -mbus_addr1_i[26] : T16 : input : 2.5 V : : 4 : N -cbus_addr_o[25] : T17 : output : 2.5 V : : 5 : N -mbus_addr3_i[29] : T18 : input : 2.5 V : : 5 : N -mbus_addr3_i[8] : T19 : input : 2.5 V : : 5 : N -mbus_addr1_i[1] : T20 : input : 2.5 V : : 5 : N -mbus_addr2_i[24] : T21 : input : 2.5 V : : 5 : N -mbus_addr3_i[27] : T22 : input : 2.5 V : : 5 : N -GND : U1 : gnd : : : : -GND : U2 : gnd : : : : -GND : U3 : gnd : : : : -VCCD_PLL : U4 : power : : 1.2V : : -CONF_DONE : U5 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 : -VCCIO3 : U8 : power : : 2.5V : 3 : -VCCIO3 : U9 : power : : 2.5V : 3 : -GND : U10 : gnd : : : : -VCCIO3 : U11 : power : : 2.5V : 3 : -mbus_addr0_i[0] : U12 : input : 2.5 V : : 3 : N -VCCIO4 : U13 : power : : 2.5V : 4 : -mbus_addr0_i[8] : U14 : input : 2.5 V : : 4 : N -mbus_cmd0_i[1] : U15 : input : 2.5 V : : 4 : N -VCCINT : U16 : power : : 1.2V : : -GND : U17 : gnd : : : : -mbus_addr3_i[11] : U18 : input : 2.5 V : : 5 : N -VCCA : U19 : power : : 2.5V : : -mbus_addr3_i[22] : U20 : input : 2.5 V : : 5 : N -GND : U21 : gnd : : : : -mbus_addr2_i[31] : U22 : input : 2.5 V : : 5 : N -GXB_NC : V1 : : : : QL0 : -GXB_NC : V2 : : : : QL0 : -VCCL_GXB : V3 : power : : 1.2V : : -VCCA : V4 : power : : 2.5V : : -GND : V5 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 : -GND : V8 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 : -VCCIO3 : V10 : power : : 2.5V : 3 : -GND : V11 : gnd : : : : -VCCIO3 : V12 : power : : 2.5V : 3 : -mbus_addr0_i[31] : V13 : input : 2.5 V : : 4 : N -GND : V14 : gnd : : : : -VCCIO4 : V15 : power : : 2.5V : 4 : -VCCIO4 : V16 : power : : 2.5V : 4 : -VCCIO4 : V17 : power : : 2.5V : 4 : -VCCD_PLL : V18 : power : : 1.2V : : -GND : V19 : gnd : : : : -mbus_addr1_i[3] : V20 : input : 2.5 V : : 5 : N -mbus_addr1_i[11] : V21 : input : 2.5 V : : 5 : N -mbus_addr1_i[31] : V22 : input : 2.5 V : : 5 : N -GND : W1 : gnd : : : : -GND : W2 : gnd : : : : -VCCA_GXB : W3 : power : : 2.5V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : W5 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 : -mbus_addr0_i[5] : W9 : input : 2.5 V : : 3 : N -mbus_addr0_i[1] : W10 : input : 2.5 V : : 3 : N -mbus_addr0_i[7] : W11 : input : 2.5 V : : 3 : N -mbus_addr0_i[23] : W12 : input : 2.5 V : : 3 : N -cbus_addr_o[11] : W13 : output : 2.5 V : : 4 : N -mbus_addr3_i[16] : W14 : input : 2.5 V : : 4 : N -mbus_addr0_i[12] : W15 : input : 2.5 V : : 4 : N -mbus_cmd0_i[2] : W16 : input : 2.5 V : : 4 : N -mbus_addr0_i[29] : W17 : input : 2.5 V : : 4 : N -cbus_ack0_i : W18 : input : 2.5 V : : 4 : N -mbus_cmd1_i[1] : W19 : input : 2.5 V : : 4 : N -mbus_addr2_i[21] : W20 : input : 2.5 V : : 5 : N -mbus_addr3_i[7] : W21 : input : 2.5 V : : 5 : N -mbus_addr0_i[24] : W22 : input : 2.5 V : : 5 : N -GXB_GND* : Y1 : : : : QL0 : -GXB_GND* : Y2 : : : : QL0 : -NC : Y3 : : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 : -mbus_addr0_i[16] : Y8 : input : 2.5 V : : 3 : N -mbus_addr0_i[18] : Y9 : input : 2.5 V : : 3 : N -mbus_addr0_i[20] : Y10 : input : 2.5 V : : 3 : N -mbus_addr0_i[14] : Y11 : input : 2.5 V : : 3 : N -mbus_addr0_i[9] : Y12 : input : 2.5 V : : 3 : N -cbus_addr_o[19] : Y13 : output : 2.5 V : : 4 : N -mbus_addr0_i[22] : Y14 : input : 2.5 V : : 4 : N -cbus_addr_o[3] : Y15 : output : 2.5 V : : 4 : N -mbus_addr0_i[10] : Y16 : input : 2.5 V : : 4 : N -mbus_addr3_i[19] : Y17 : input : 2.5 V : : 4 : N -cbus_addr_o[9] : Y18 : output : 2.5 V : : 4 : N -mbus_ack1_o : Y19 : output : 2.5 V : : 4 : N -mbus_cmd1_i[2] : Y20 : input : 2.5 V : : 4 : N -GND : Y21 : gnd : : : : -mbus_addr3_i[3] : Y22 : input : 2.5 V : : 5 : N Index: syn/mesi_isc.sof =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/mesi_isc.sof =================================================================== --- syn/mesi_isc.sof (revision 4) +++ syn/mesi_isc.sof (nonexistent)
syn/mesi_isc.sof Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/mesi_isc.tis_db_list.ddb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/mesi_isc.tis_db_list.ddb =================================================================== --- syn/mesi_isc.tis_db_list.ddb (revision 4) +++ syn/mesi_isc.tis_db_list.ddb (nonexistent)
syn/mesi_isc.tis_db_list.ddb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/mesi_isc.qsf =================================================================== --- syn/mesi_isc.qsf (revision 4) +++ syn/mesi_isc.qsf (nonexistent) @@ -1,55 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2012 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 32-bit -# Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition -# Date created = 09:58:58 November 06, 2012 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# mesi_isc_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "Cyclone IV GX" -set_global_assignment -name DEVICE auto -set_global_assignment -name TOP_LEVEL_ENTITY mesi_isc -set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.0 SP2" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:58:58 NOVEMBER 06, 2012" -set_global_assignment -name LAST_QUARTUS_VERSION "12.0 SP2" -set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_define.v -set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_broad_cntl.v -set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_broad.v -set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_breq_fifos_cntl.v -set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_breq_fifos.v -set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_basic_fifo.v -set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc.v -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file Index: syn/db/mesi_isc.tiscmp.fast_1200mv_0c.ddb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.tiscmp.fast_1200mv_0c.ddb =================================================================== --- syn/db/mesi_isc.tiscmp.fast_1200mv_0c.ddb (revision 4) +++ syn/db/mesi_isc.tiscmp.fast_1200mv_0c.ddb (nonexistent)
syn/db/mesi_isc.tiscmp.fast_1200mv_0c.ddb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.pre_map.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.pre_map.cdb =================================================================== --- syn/db/mesi_isc.pre_map.cdb (revision 4) +++ syn/db/mesi_isc.pre_map.cdb (nonexistent)
syn/db/mesi_isc.pre_map.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.(0).cnf.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.(0).cnf.cdb =================================================================== --- syn/db/mesi_isc.(0).cnf.cdb (revision 4) +++ syn/db/mesi_isc.(0).cnf.cdb (nonexistent)
syn/db/mesi_isc.(0).cnf.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.(4).cnf.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.(4).cnf.cdb =================================================================== --- syn/db/mesi_isc.(4).cnf.cdb (revision 4) +++ syn/db/mesi_isc.(4).cnf.cdb (nonexistent)
syn/db/mesi_isc.(4).cnf.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.(2).cnf.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.(2).cnf.hdb =================================================================== --- syn/db/mesi_isc.(2).cnf.hdb (revision 4) +++ syn/db/mesi_isc.(2).cnf.hdb (nonexistent)
syn/db/mesi_isc.(2).cnf.hdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.ace_cmp.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.ace_cmp.hdb =================================================================== --- syn/db/mesi_isc.ace_cmp.hdb (revision 4) +++ syn/db/mesi_isc.ace_cmp.hdb (nonexistent)
syn/db/mesi_isc.ace_cmp.hdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.asm.rdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.asm.rdb =================================================================== --- syn/db/mesi_isc.asm.rdb (revision 4) +++ syn/db/mesi_isc.asm.rdb (nonexistent)
syn/db/mesi_isc.asm.rdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.(6).cnf.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.(6).cnf.hdb =================================================================== --- syn/db/mesi_isc.(6).cnf.hdb (revision 4) +++ syn/db/mesi_isc.(6).cnf.hdb (nonexistent)
syn/db/mesi_isc.(6).cnf.hdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.lpc.txt =================================================================== --- syn/db/mesi_isc.lpc.txt (revision 4) +++ syn/db/mesi_isc.lpc.txt (nonexistent) @@ -1,15 +0,0 @@ -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Legal Partition Candidates ; -+----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; -+----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; mesi_isc_breq_fifos|fifo_0 ; 45 ; 0 ; 0 ; 0 ; 43 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; mesi_isc_breq_fifos|fifo_1 ; 45 ; 0 ; 0 ; 0 ; 43 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; mesi_isc_breq_fifos|fifo_2 ; 45 ; 0 ; 0 ; 0 ; 43 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; mesi_isc_breq_fifos|fifo_3 ; 45 ; 0 ; 0 ; 0 ; 43 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl ; 179 ; 16 ; 0 ; 16 ; 90 ; 16 ; 16 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; mesi_isc_breq_fifos ; 143 ; 0 ; 0 ; 0 ; 46 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; mesi_isc_broad|broad_fifo ; 45 ; 0 ; 0 ; 0 ; 43 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; mesi_isc_broad|mesi_isc_broad_cntl ; 17 ; 0 ; 6 ; 0 ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; mesi_isc_broad ; 48 ; 0 ; 0 ; 0 ; 45 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -+----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ Index: syn/db/mesi_isc.routing.rdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.routing.rdb =================================================================== --- syn/db/mesi_isc.routing.rdb (revision 4) +++ syn/db/mesi_isc.routing.rdb (nonexistent)
syn/db/mesi_isc.routing.rdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.eda.qmsg =================================================================== --- syn/db/mesi_isc.eda.qmsg (revision 4) +++ syn/db/mesi_isc.eda.qmsg (nonexistent) @@ -1,5 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1356436965225 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition " "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1356436965225 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 25 14:02:45 2012 " "Processing started: Tue Dec 25 14:02:45 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1356436965225 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1356436965225 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=on --write_settings_files=off mesi_isc -c mesi_isc " "Command: quartus_eda --read_settings_files=on --write_settings_files=off mesi_isc -c mesi_isc" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1356436965225 ""} -{ "Warning" "WQNETO_NO_OUTPUT_FILES" "" "Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script." { } { } 0 199027 "Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script." 0 0 "" 0 -1 1356436965724 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "344 " "Peak virtual memory: 344 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1356436965760 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 25 14:02:45 2012 " "Processing ended: Tue Dec 25 14:02:45 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1356436965760 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1356436965760 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1356436965760 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1356436965760 ""} Index: syn/db/mesi_isc.taw.rdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.taw.rdb =================================================================== --- syn/db/mesi_isc.taw.rdb (revision 4) +++ syn/db/mesi_isc.taw.rdb (nonexistent)
syn/db/mesi_isc.taw.rdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.ace_cmp.bpm =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.ace_cmp.bpm =================================================================== --- syn/db/mesi_isc.ace_cmp.bpm (revision 4) +++ syn/db/mesi_isc.ace_cmp.bpm (nonexistent)
syn/db/mesi_isc.ace_cmp.bpm Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.map_bb.logdb =================================================================== --- syn/db/mesi_isc.map_bb.logdb (revision 4) +++ syn/db/mesi_isc.map_bb.logdb (nonexistent) @@ -1 +0,0 @@ -v1 Index: syn/db/mesi_isc.asm_labs.ddb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.asm_labs.ddb =================================================================== --- syn/db/mesi_isc.asm_labs.ddb (revision 4) +++ syn/db/mesi_isc.asm_labs.ddb (nonexistent)
syn/db/mesi_isc.asm_labs.ddb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.map.kpt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.map.kpt =================================================================== --- syn/db/mesi_isc.map.kpt (revision 4) +++ syn/db/mesi_isc.map.kpt (nonexistent)
syn/db/mesi_isc.map.kpt Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.cbx.xml =================================================================== --- syn/db/mesi_isc.cbx.xml (revision 4) +++ syn/db/mesi_isc.cbx.xml (nonexistent) @@ -1,5 +0,0 @@ - - - - - Index: syn/db/mesi_isc.cmp.kpt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.cmp.kpt =================================================================== --- syn/db/mesi_isc.cmp.kpt (revision 4) +++ syn/db/mesi_isc.cmp.kpt (nonexistent)
syn/db/mesi_isc.cmp.kpt Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.map_bb.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.map_bb.hdb =================================================================== --- syn/db/mesi_isc.map_bb.hdb (revision 4) +++ syn/db/mesi_isc.map_bb.hdb (nonexistent)
syn/db/mesi_isc.map_bb.hdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.(1).cnf.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.(1).cnf.cdb =================================================================== --- syn/db/mesi_isc.(1).cnf.cdb (revision 4) +++ syn/db/mesi_isc.(1).cnf.cdb (nonexistent)
syn/db/mesi_isc.(1).cnf.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.(5).cnf.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.(5).cnf.cdb =================================================================== --- syn/db/mesi_isc.(5).cnf.cdb (revision 4) +++ syn/db/mesi_isc.(5).cnf.cdb (nonexistent)
syn/db/mesi_isc.(5).cnf.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.lpc.html =================================================================== --- syn/db/mesi_isc.lpc.html (revision 4) +++ syn/db/mesi_isc.lpc.html (nonexistent) @@ -1,162 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
mesi_isc_breq_fifos|fifo_0450004300000000
mesi_isc_breq_fifos|fifo_1450004300000000
mesi_isc_breq_fifos|fifo_2450004300000000
mesi_isc_breq_fifos|fifo_3450004300000000
mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl179160169016161600000
mesi_isc_breq_fifos1430004600000000
mesi_isc_broad|broad_fifo450004300000000
mesi_isc_broad|mesi_isc_broad_cntl170601300000000
mesi_isc_broad480004500000000
Index: syn/db/mesi_isc.rtlv.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.rtlv.hdb =================================================================== --- syn/db/mesi_isc.rtlv.hdb (revision 4) +++ syn/db/mesi_isc.rtlv.hdb (nonexistent)
syn/db/mesi_isc.rtlv.hdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.(3).cnf.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.(3).cnf.hdb =================================================================== --- syn/db/mesi_isc.(3).cnf.hdb (revision 4) +++ syn/db/mesi_isc.(3).cnf.hdb (nonexistent)
syn/db/mesi_isc.(3).cnf.hdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.fit.qmsg =================================================================== --- syn/db/mesi_isc.fit.qmsg (revision 4) +++ syn/db/mesi_isc.fit.qmsg (nonexistent) @@ -1,46 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1356436455390 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition " "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1356436455391 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 25 13:54:15 2012 " "Processing started: Tue Dec 25 13:54:15 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1356436455391 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1356436455391 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off mesi_isc -c mesi_isc " "Command: quartus_fit --read_settings_files=off --write_settings_files=off mesi_isc -c mesi_isc" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1356436455391 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "" 0 -1 1356436455496 ""} -{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "mesi_isc EP4CGX30CF23C6 " "Automatically selected device EP4CGX30CF23C6 for design mesi_isc" { } { } 0 119004 "Automatically selected device %2!s! for design %1!s!" 0 0 "" 0 -1 1356436455755 ""} -{ "Info" "IMPP_MPP_FIT_WITH_SMALLER_DEVICE" "" "Fitting design with smaller device may be possible, but smaller device must be specified" { } { } 0 119005 "Fitting design with smaller device may be possible, but smaller device must be specified" 0 0 "" 0 -1 1356436455755 ""} -{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0 -1 1356436455845 ""} -{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0 -1 1356436455846 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1 1356436456149 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "" 0 -1 1356436456168 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CGX75CF23C6 " "Device EP4CGX75CF23C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "" 0 -1 1356436456640 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CGX50CF23C6 " "Device EP4CGX50CF23C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "" 0 -1 1356436456640 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1 1356436456640 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_NCEO~ AB3 " "Pin ~ALTERA_NCEO~ is reserved at location AB3" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { ~ALTERA_NCEO~ } } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_NCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 1611 7904 8816 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1356436456649 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K4 " "Pin ~ALTERA_DATA0~ is reserved at location K4" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 1613 7904 8816 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1356436456649 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 1615 7904 8816 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1356436456649 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_NCSO~ J4 " "Pin ~ALTERA_NCSO~ is reserved at location J4" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { ~ALTERA_NCSO~ } } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_NCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 1617 7904 8816 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1356436456649 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ D3 " "Pin ~ALTERA_DCLK~ is reserved at location D3" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 1619 7904 8816 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1356436456649 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1 1356436456649 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1 1356436456652 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "194 194 " "No exact pin location assignment(s) for 194 pins of 194 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[0\] " "Pin cbus_addr_o\[0\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[0] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 165 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[1\] " "Pin cbus_addr_o\[1\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[1] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 166 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[2\] " "Pin cbus_addr_o\[2\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[2] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 167 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[3\] " "Pin cbus_addr_o\[3\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[3] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 168 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[4\] " "Pin cbus_addr_o\[4\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[4] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 169 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[5\] " "Pin cbus_addr_o\[5\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[5] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 170 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[6\] " "Pin cbus_addr_o\[6\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[6] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 171 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[7\] " "Pin cbus_addr_o\[7\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[7] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 172 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[8\] " "Pin cbus_addr_o\[8\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[8] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 173 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[9\] " "Pin cbus_addr_o\[9\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[9] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 174 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[10\] " "Pin cbus_addr_o\[10\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[10] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 175 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[11\] " "Pin cbus_addr_o\[11\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[11] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 176 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[12\] " "Pin cbus_addr_o\[12\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[12] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 177 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[13\] " "Pin cbus_addr_o\[13\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[13] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 178 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[14\] " "Pin cbus_addr_o\[14\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[14] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 179 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[15\] " "Pin cbus_addr_o\[15\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[15] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 180 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[16\] " "Pin cbus_addr_o\[16\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[16] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 181 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[17\] " "Pin cbus_addr_o\[17\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[17] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 182 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[18\] " "Pin cbus_addr_o\[18\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[18] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 183 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[19\] " "Pin cbus_addr_o\[19\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[19] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 184 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[20\] " "Pin cbus_addr_o\[20\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[20] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 185 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[21\] " "Pin cbus_addr_o\[21\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[21] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 186 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[22\] " "Pin cbus_addr_o\[22\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[22] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 187 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[23\] " "Pin cbus_addr_o\[23\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[23] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 188 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[24\] " "Pin cbus_addr_o\[24\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[24] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 189 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[25\] " "Pin cbus_addr_o\[25\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[25] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 190 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[26\] " "Pin cbus_addr_o\[26\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[26] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 191 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[27\] " "Pin cbus_addr_o\[27\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[27] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 192 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[28\] " "Pin cbus_addr_o\[28\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[28] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 193 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[29\] " "Pin cbus_addr_o\[29\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[29] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 194 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[30\] " "Pin cbus_addr_o\[30\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[30] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 195 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_addr_o\[31\] " "Pin cbus_addr_o\[31\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_addr_o[31] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 110 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_addr_o[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 196 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_cmd3_o\[0\] " "Pin cbus_cmd3_o\[0\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_cmd3_o[0] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 112 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_cmd3_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 197 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_cmd3_o\[1\] " "Pin cbus_cmd3_o\[1\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_cmd3_o[1] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 112 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_cmd3_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 198 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_cmd3_o\[2\] " "Pin cbus_cmd3_o\[2\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_cmd3_o[2] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 112 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_cmd3_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 199 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_cmd2_o\[0\] " "Pin cbus_cmd2_o\[0\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_cmd2_o[0] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 113 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_cmd2_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 200 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_cmd2_o\[1\] " "Pin cbus_cmd2_o\[1\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_cmd2_o[1] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 113 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_cmd2_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 201 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_cmd2_o\[2\] " "Pin cbus_cmd2_o\[2\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_cmd2_o[2] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 113 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_cmd2_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 202 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_cmd1_o\[0\] " "Pin cbus_cmd1_o\[0\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_cmd1_o[0] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 114 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_cmd1_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 203 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_cmd1_o\[1\] " "Pin cbus_cmd1_o\[1\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_cmd1_o[1] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 114 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_cmd1_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 204 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_cmd1_o\[2\] " "Pin cbus_cmd1_o\[2\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_cmd1_o[2] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 114 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_cmd1_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 205 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_cmd0_o\[0\] " "Pin cbus_cmd0_o\[0\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_cmd0_o[0] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 115 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_cmd0_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 206 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_cmd0_o\[1\] " "Pin cbus_cmd0_o\[1\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_cmd0_o[1] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 115 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_cmd0_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 207 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_cmd0_o\[2\] " "Pin cbus_cmd0_o\[2\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_cmd0_o[2] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 115 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_cmd0_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 208 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_ack3_o " "Pin mbus_ack3_o not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_ack3_o } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 118 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_ack3_o } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 215 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_ack2_o " "Pin mbus_ack2_o not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_ack2_o } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 119 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_ack2_o } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 216 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_ack1_o " "Pin mbus_ack1_o not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_ack1_o } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 120 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_ack1_o } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 217 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_ack0_o " "Pin mbus_ack0_o not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_ack0_o } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 121 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_ack0_o } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 218 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk " "Pin clk not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { clk } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 90 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 209 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rst " "Pin rst not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { rst } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 91 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 210 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_ack3_i " "Pin cbus_ack3_i not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_ack3_i } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 102 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_ack3_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 211 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_ack2_i " "Pin cbus_ack2_i not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_ack2_i } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 103 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_ack2_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 212 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_ack1_i " "Pin cbus_ack1_i not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_ack1_i } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 104 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_ack1_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 213 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cbus_ack0_i " "Pin cbus_ack0_i not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { cbus_ack0_i } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 105 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { cbus_ack0_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 214 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_cmd3_i\[0\] " "Pin mbus_cmd3_i\[0\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_cmd3_i[0] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 93 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_cmd3_i[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 25 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_cmd3_i\[2\] " "Pin mbus_cmd3_i\[2\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_cmd3_i[2] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 93 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_cmd3_i[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 27 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_cmd3_i\[1\] " "Pin mbus_cmd3_i\[1\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_cmd3_i[1] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 93 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_cmd3_i[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 26 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_cmd2_i\[0\] " "Pin mbus_cmd2_i\[0\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_cmd2_i[0] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 94 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_cmd2_i[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 28 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_cmd2_i\[1\] " "Pin mbus_cmd2_i\[1\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_cmd2_i[1] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 94 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_cmd2_i[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 29 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_cmd2_i\[2\] " "Pin mbus_cmd2_i\[2\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_cmd2_i[2] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 94 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_cmd2_i[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 30 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_cmd1_i\[2\] " "Pin mbus_cmd1_i\[2\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_cmd1_i[2] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 95 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_cmd1_i[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 33 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_cmd1_i\[0\] " "Pin mbus_cmd1_i\[0\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_cmd1_i[0] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 95 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_cmd1_i[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 31 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_cmd1_i\[1\] " "Pin mbus_cmd1_i\[1\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_cmd1_i[1] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 95 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_cmd1_i[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 32 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_cmd0_i\[0\] " "Pin mbus_cmd0_i\[0\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_cmd0_i[0] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 96 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_cmd0_i[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 34 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_cmd0_i\[1\] " "Pin mbus_cmd0_i\[1\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_cmd0_i[1] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 96 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_cmd0_i[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 35 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_cmd0_i\[2\] " "Pin mbus_cmd0_i\[2\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_cmd0_i[2] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 96 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_cmd0_i[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 36 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[0\] " "Pin mbus_addr2_i\[0\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[0] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 69 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[0\] " "Pin mbus_addr3_i\[0\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[0] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 37 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[0\] " "Pin mbus_addr0_i\[0\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[0] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 133 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[0\] " "Pin mbus_addr1_i\[0\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[0] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 101 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[1\] " "Pin mbus_addr2_i\[1\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[1] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 70 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[1\] " "Pin mbus_addr3_i\[1\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[1] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 38 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[1\] " "Pin mbus_addr0_i\[1\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[1] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 134 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[1\] " "Pin mbus_addr1_i\[1\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[1] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 102 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[2\] " "Pin mbus_addr2_i\[2\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[2] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 71 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[2\] " "Pin mbus_addr3_i\[2\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[2] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 39 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[2\] " "Pin mbus_addr0_i\[2\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[2] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 135 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[2\] " "Pin mbus_addr1_i\[2\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[2] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 103 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[3\] " "Pin mbus_addr2_i\[3\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[3] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 72 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[3\] " "Pin mbus_addr3_i\[3\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[3] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 40 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[3\] " "Pin mbus_addr0_i\[3\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[3] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 136 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[3\] " "Pin mbus_addr1_i\[3\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[3] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 104 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[4\] " "Pin mbus_addr2_i\[4\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[4] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 73 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[4\] " "Pin mbus_addr3_i\[4\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[4] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 41 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[4\] " "Pin mbus_addr0_i\[4\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[4] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 137 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[4\] " "Pin mbus_addr1_i\[4\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[4] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 105 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[5\] " "Pin mbus_addr2_i\[5\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[5] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 74 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[5\] " "Pin mbus_addr3_i\[5\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[5] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 42 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[5\] " "Pin mbus_addr0_i\[5\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[5] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 138 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[5\] " "Pin mbus_addr1_i\[5\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[5] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 106 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[6\] " "Pin mbus_addr2_i\[6\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[6] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 75 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[6\] " "Pin mbus_addr3_i\[6\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[6] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 43 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[6\] " "Pin mbus_addr0_i\[6\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[6] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 139 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[6\] " "Pin mbus_addr1_i\[6\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[6] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 107 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[7\] " "Pin mbus_addr2_i\[7\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[7] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 76 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[7\] " "Pin mbus_addr3_i\[7\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[7] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 44 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[7\] " "Pin mbus_addr0_i\[7\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[7] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 140 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[7\] " "Pin mbus_addr1_i\[7\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[7] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 108 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[8\] " "Pin mbus_addr2_i\[8\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[8] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 77 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[8\] " "Pin mbus_addr3_i\[8\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[8] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 45 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[8\] " "Pin mbus_addr0_i\[8\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[8] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 141 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[8\] " "Pin mbus_addr1_i\[8\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[8] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 109 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[9\] " "Pin mbus_addr2_i\[9\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[9] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 78 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[9\] " "Pin mbus_addr3_i\[9\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[9] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 46 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[9\] " "Pin mbus_addr0_i\[9\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[9] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 142 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[9\] " "Pin mbus_addr1_i\[9\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[9] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 110 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[10\] " "Pin mbus_addr2_i\[10\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[10] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 79 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[10\] " "Pin mbus_addr3_i\[10\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[10] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 47 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[10\] " "Pin mbus_addr0_i\[10\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[10] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 143 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[10\] " "Pin mbus_addr1_i\[10\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[10] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 111 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[11\] " "Pin mbus_addr2_i\[11\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[11] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 80 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[11\] " "Pin mbus_addr3_i\[11\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[11] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 48 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[11\] " "Pin mbus_addr0_i\[11\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[11] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 144 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[11\] " "Pin mbus_addr1_i\[11\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[11] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 112 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[12\] " "Pin mbus_addr2_i\[12\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[12] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 81 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[12\] " "Pin mbus_addr3_i\[12\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[12] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 49 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[12\] " "Pin mbus_addr0_i\[12\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[12] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 145 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[12\] " "Pin mbus_addr1_i\[12\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[12] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 113 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[13\] " "Pin mbus_addr2_i\[13\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[13] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 82 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[13\] " "Pin mbus_addr3_i\[13\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[13] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 50 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[13\] " "Pin mbus_addr0_i\[13\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[13] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 146 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[13\] " "Pin mbus_addr1_i\[13\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[13] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 114 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[14\] " "Pin mbus_addr2_i\[14\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[14] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 83 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[14\] " "Pin mbus_addr3_i\[14\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[14] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 51 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[14\] " "Pin mbus_addr0_i\[14\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[14] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 147 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[14\] " "Pin mbus_addr1_i\[14\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[14] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 115 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[15\] " "Pin mbus_addr2_i\[15\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[15] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 84 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[15\] " "Pin mbus_addr3_i\[15\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[15] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 52 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[15\] " "Pin mbus_addr0_i\[15\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[15] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 148 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[15\] " "Pin mbus_addr1_i\[15\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[15] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 116 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[16\] " "Pin mbus_addr2_i\[16\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[16] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 85 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[16\] " "Pin mbus_addr3_i\[16\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[16] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 53 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[16\] " "Pin mbus_addr0_i\[16\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[16] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 149 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[16\] " "Pin mbus_addr1_i\[16\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[16] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 117 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[17\] " "Pin mbus_addr2_i\[17\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[17] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 86 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[17\] " "Pin mbus_addr3_i\[17\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[17] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 54 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[17\] " "Pin mbus_addr0_i\[17\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[17] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 150 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[17\] " "Pin mbus_addr1_i\[17\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[17] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 118 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[18\] " "Pin mbus_addr2_i\[18\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[18] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 87 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[18\] " "Pin mbus_addr3_i\[18\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[18] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 55 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[18\] " "Pin mbus_addr0_i\[18\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[18] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 151 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[18\] " "Pin mbus_addr1_i\[18\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[18] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 119 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[19\] " "Pin mbus_addr2_i\[19\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[19] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 88 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[19\] " "Pin mbus_addr3_i\[19\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[19] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 56 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[19\] " "Pin mbus_addr0_i\[19\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[19] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 152 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[19\] " "Pin mbus_addr1_i\[19\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[19] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 120 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[20\] " "Pin mbus_addr2_i\[20\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[20] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 89 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[20\] " "Pin mbus_addr3_i\[20\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[20] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 57 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[20\] " "Pin mbus_addr0_i\[20\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[20] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 153 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[20\] " "Pin mbus_addr1_i\[20\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[20] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 121 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[21\] " "Pin mbus_addr2_i\[21\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[21] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 90 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[21\] " "Pin mbus_addr3_i\[21\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[21] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 58 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[21\] " "Pin mbus_addr0_i\[21\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[21] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 154 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[21\] " "Pin mbus_addr1_i\[21\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[21] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 122 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[22\] " "Pin mbus_addr2_i\[22\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[22] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 91 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[22\] " "Pin mbus_addr3_i\[22\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[22] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 59 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[22\] " "Pin mbus_addr0_i\[22\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[22] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 155 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[22\] " "Pin mbus_addr1_i\[22\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[22] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 123 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[23\] " "Pin mbus_addr2_i\[23\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[23] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 92 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[23\] " "Pin mbus_addr3_i\[23\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[23] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 60 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[23\] " "Pin mbus_addr0_i\[23\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[23] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 156 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[23\] " "Pin mbus_addr1_i\[23\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[23] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 124 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[24\] " "Pin mbus_addr2_i\[24\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[24] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 93 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[24\] " "Pin mbus_addr3_i\[24\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[24] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 61 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[24\] " "Pin mbus_addr0_i\[24\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[24] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 157 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[24\] " "Pin mbus_addr1_i\[24\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[24] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 125 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[25\] " "Pin mbus_addr2_i\[25\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[25] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 94 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[25\] " "Pin mbus_addr3_i\[25\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[25] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 62 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[25\] " "Pin mbus_addr0_i\[25\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[25] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 158 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[25\] " "Pin mbus_addr1_i\[25\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[25] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 126 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[26\] " "Pin mbus_addr2_i\[26\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[26] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 95 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[26\] " "Pin mbus_addr3_i\[26\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[26] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 63 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[26\] " "Pin mbus_addr0_i\[26\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[26] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 159 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[26\] " "Pin mbus_addr1_i\[26\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[26] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 127 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[27\] " "Pin mbus_addr2_i\[27\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[27] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 96 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[27\] " "Pin mbus_addr3_i\[27\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[27] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 64 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[27\] " "Pin mbus_addr0_i\[27\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[27] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 160 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[27\] " "Pin mbus_addr1_i\[27\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[27] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 128 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[28\] " "Pin mbus_addr2_i\[28\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[28] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 97 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[28\] " "Pin mbus_addr3_i\[28\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[28] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 65 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[28\] " "Pin mbus_addr0_i\[28\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[28] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 161 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[28\] " "Pin mbus_addr1_i\[28\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[28] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 129 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[29\] " "Pin mbus_addr2_i\[29\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[29] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 98 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[29\] " "Pin mbus_addr3_i\[29\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[29] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 66 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[29\] " "Pin mbus_addr0_i\[29\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[29] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 162 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[29\] " "Pin mbus_addr1_i\[29\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[29] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 130 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[30\] " "Pin mbus_addr2_i\[30\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[30] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 99 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[30\] " "Pin mbus_addr3_i\[30\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[30] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 67 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[30\] " "Pin mbus_addr0_i\[30\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[30] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 163 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[30\] " "Pin mbus_addr1_i\[30\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[30] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 131 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr2_i\[31\] " "Pin mbus_addr2_i\[31\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr2_i[31] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 99 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr2_i[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 100 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr3_i\[31\] " "Pin mbus_addr3_i\[31\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr3_i[31] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 98 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr3_i[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 68 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr0_i\[31\] " "Pin mbus_addr0_i\[31\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr0_i[31] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 101 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr0_i[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 164 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mbus_addr1_i\[31\] " "Pin mbus_addr1_i\[31\] not assigned to an exact location on the device" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { mbus_addr1_i[31] } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 100 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { mbus_addr1_i[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 132 7904 8816 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1 1356436458197 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1 1356436458197 ""} -{ "Info" "ISTA_SDC_FOUND" "mesi_isc.sdc " "Reading SDC File: 'mesi_isc.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1356436458760 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "" 0 -1 1356436458792 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1 1356436458795 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1356436458795 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1356436458795 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 clk " " 1.000 clk" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1356436458795 ""} } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1356436458795 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN N11 (CLKIO13, DIFFCLK_7n, REFCLK2n)) " "Automatically promoted node clk~input (placed in PIN N11 (CLKIO13, DIFFCLK_7n, REFCLK2n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G29 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G29" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1356436458910 ""} } { { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 90 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 1460 7904 8816 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1356436458910 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst~input (placed in PIN M11 (CLKIO12, DIFFCLK_7p, REFCLK2p)) " "Automatically promoted node rst~input (placed in PIN M11 (CLKIO12, DIFFCLK_7p, REFCLK2p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G28 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G28" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1356436458910 ""} } { { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 91 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { rst~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 1461 7904 8816 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1356436458910 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "" 0 -1 1356436459580 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1 1356436459583 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1 1356436459583 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 0 0 "" 0 -1 1356436459587 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 0 0 "" 0 -1 1356436459593 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 0 0 "" 0 -1 1356436459595 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 0 0 "" 0 -1 1356436459713 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "36 I/O Output Buffer " "Packed 36 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1356436460316 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "4 " "Created 4 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "" 0 -1 1356436460316 ""} } { } 0 176235 "Finished register packing" 0 0 "" 0 -1 1356436460316 ""} -{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "192 unused 2.5V 144 48 0 " "Number of I/O pins in group: 192 (unused VREF, 2.5V VCCIO, 144 input, 48 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "" 0 -1 1356436460325 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1 1356436460325 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "" 0 -1 1356436460325 ""} -{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL1 does not use undetermined 0 0 " "I/O bank number QL1 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1 1356436460330 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL0 does not use undetermined 0 0 " "I/O bank number QL0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1 1356436460330 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 45 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 45 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1 1356436460330 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3B does not use undetermined 0 2 " "I/O bank number 3B does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 2 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1 1356436460330 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3A does not use undetermined 2 0 " "I/O bank number 3A does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1 1356436460330 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 45 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 45 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1 1356436460330 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 49 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 49 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1 1356436460330 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 49 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 49 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1 1356436460330 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 46 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 46 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1 1356436460330 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8A does not use undetermined 0 2 " "I/O bank number 8A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 2 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1 1356436460330 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 44 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 44 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1 1356436460330 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8B does not use undetermined 0 0 " "I/O bank number 8B does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1 1356436460330 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 4 0 " "I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1 1356436460330 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "" 0 -1 1356436460330 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1 1356436460330 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:04 " "Fitter preparation operations ending: elapsed time is 00:00:04" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1356436460551 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "" 0 -1 1356436465698 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1356436466166 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "" 0 -1 1356436466177 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "" 0 -1 1356436477038 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:11 " "Fitter placement operations ending: elapsed time is 00:00:11" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1356436477038 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "" 0 -1 1356436478165 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Router estimated average interconnect usage is 1% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "9 X58_Y22 X69_Y33 " "Router estimated peak interconnect usage is 9% of the available device resources in the region that extends from location X58_Y22 to location X69_Y33" { } { { "loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 1 { 0 "Router estimated peak interconnect usage is 9% of the available device resources in the region that extends from location X58_Y22 to location X69_Y33"} { { 11 { 0 "Router estimated peak interconnect usage is 9% of the available device resources in the region that extends from location X58_Y22 to location X69_Y33"} 58 22 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1 1356436483656 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1 1356436483656 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:05 " "Fitter routing operations ending: elapsed time is 00:00:05" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1356436487086 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1 1356436487089 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1 1356436487089 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "" 0 -1 1356436487254 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "" 0 -1 1356436488088 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "" 0 -1 1356436488193 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "" 0 -1 1356436489024 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "2 Cyclone IV GX " "2 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV GX Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "clk 2.5 V N11 " "Pin clk uses I/O standard 2.5 V at N11" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { clk } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 90 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 209 7904 8816 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1 1356436491827 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rst 2.5 V M11 " "Pin rst uses I/O standard 2.5 V at M11" { } { { "/opt/12.0sp2/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/12.0sp2/quartus/linux/pin_planner.ppl" { rst } } } { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 91 0 0 } } { "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/12.0sp2/quartus/linux/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/yair/Work/Projects/mesi_isc/syn/" { { 0 { 0 ""} 0 210 7904 8816 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0 -1 1356436491827 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "" 0 -1 1356436491827 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "574 " "Peak virtual memory: 574 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1356436492776 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 25 13:54:52 2012 " "Processing ended: Tue Dec 25 13:54:52 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1356436492776 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:37 " "Elapsed time: 00:00:37" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1356436492776 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:37 " "Total CPU time (on all processors): 00:00:37" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1356436492776 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1356436492776 ""} Index: syn/db/mesi_isc.sgdiff.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.sgdiff.cdb =================================================================== --- syn/db/mesi_isc.sgdiff.cdb (revision 4) +++ syn/db/mesi_isc.sgdiff.cdb (nonexistent)
syn/db/mesi_isc.sgdiff.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.cmp_merge.kpt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.cmp_merge.kpt =================================================================== --- syn/db/mesi_isc.cmp_merge.kpt (revision 4) +++ syn/db/mesi_isc.cmp_merge.kpt (nonexistent)
syn/db/mesi_isc.cmp_merge.kpt Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.sta.rdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.sta.rdb =================================================================== --- syn/db/mesi_isc.sta.rdb (revision 4) +++ syn/db/mesi_isc.sta.rdb (nonexistent)
syn/db/mesi_isc.sta.rdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.eco.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.eco.cdb =================================================================== --- syn/db/mesi_isc.eco.cdb (revision 4) +++ syn/db/mesi_isc.eco.cdb (nonexistent)
syn/db/mesi_isc.eco.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.tiscmp.slow_1200mv_85c.ddb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.tiscmp.slow_1200mv_85c.ddb =================================================================== --- syn/db/mesi_isc.tiscmp.slow_1200mv_85c.ddb (revision 4) +++ syn/db/mesi_isc.tiscmp.slow_1200mv_85c.ddb (nonexistent)
syn/db/mesi_isc.tiscmp.slow_1200mv_85c.ddb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.db_info =================================================================== --- syn/db/mesi_isc.db_info (revision 4) +++ syn/db/mesi_isc.db_info (nonexistent) @@ -1,3 +0,0 @@ -Quartus_Version = Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition -Version_Index = 268502786 -Creation_Time = Tue Nov 6 09:59:07 2012 Index: syn/db/mesi_isc.root_partition.map.reg_db.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.root_partition.map.reg_db.cdb =================================================================== --- syn/db/mesi_isc.root_partition.map.reg_db.cdb (revision 4) +++ syn/db/mesi_isc.root_partition.map.reg_db.cdb (nonexistent)
syn/db/mesi_isc.root_partition.map.reg_db.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/prev_cmp_mesi_isc.qmsg =================================================================== --- syn/db/prev_cmp_mesi_isc.qmsg (revision 4) +++ syn/db/prev_cmp_mesi_isc.qmsg (nonexistent) @@ -1,5 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1356436965225 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition " "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1356436965225 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 25 14:02:45 2012 " "Processing started: Tue Dec 25 14:02:45 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1356436965225 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1356436965225 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=on --write_settings_files=off mesi_isc -c mesi_isc " "Command: quartus_eda --read_settings_files=on --write_settings_files=off mesi_isc -c mesi_isc" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1356436965225 ""} -{ "Warning" "WQNETO_NO_OUTPUT_FILES" "" "Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script." { } { } 0 199027 "Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script." 0 0 "" 0 -1 1356436965724 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "344 " "Peak virtual memory: 344 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1356436965760 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 25 14:02:45 2012 " "Processing ended: Tue Dec 25 14:02:45 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1356436965760 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1356436965760 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1356436965760 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1356436965760 ""} Index: syn/db/mesi_isc.hier_info =================================================================== --- syn/db/mesi_isc.hier_info (revision 4) +++ syn/db/mesi_isc.hier_info (nonexistent) @@ -1,3979 +0,0 @@ -|mesi_isc -clk => clk.IN2 -rst => rst.IN2 -mbus_cmd3_i[0] => mbus_cmd3_i[0].IN1 -mbus_cmd3_i[1] => mbus_cmd3_i[1].IN1 -mbus_cmd3_i[2] => mbus_cmd3_i[2].IN1 -mbus_cmd2_i[0] => mbus_cmd2_i[0].IN1 -mbus_cmd2_i[1] => mbus_cmd2_i[1].IN1 -mbus_cmd2_i[2] => mbus_cmd2_i[2].IN1 -mbus_cmd1_i[0] => mbus_cmd1_i[0].IN1 -mbus_cmd1_i[1] => mbus_cmd1_i[1].IN1 -mbus_cmd1_i[2] => mbus_cmd1_i[2].IN1 -mbus_cmd0_i[0] => mbus_cmd0_i[0].IN1 -mbus_cmd0_i[1] => mbus_cmd0_i[1].IN1 -mbus_cmd0_i[2] => mbus_cmd0_i[2].IN1 -mbus_addr3_i[0] => mbus_addr3_i[0].IN1 -mbus_addr3_i[1] => mbus_addr3_i[1].IN1 -mbus_addr3_i[2] => mbus_addr3_i[2].IN1 -mbus_addr3_i[3] => mbus_addr3_i[3].IN1 -mbus_addr3_i[4] => mbus_addr3_i[4].IN1 -mbus_addr3_i[5] => mbus_addr3_i[5].IN1 -mbus_addr3_i[6] => mbus_addr3_i[6].IN1 -mbus_addr3_i[7] => mbus_addr3_i[7].IN1 -mbus_addr3_i[8] => mbus_addr3_i[8].IN1 -mbus_addr3_i[9] => mbus_addr3_i[9].IN1 -mbus_addr3_i[10] => mbus_addr3_i[10].IN1 -mbus_addr3_i[11] => mbus_addr3_i[11].IN1 -mbus_addr3_i[12] => mbus_addr3_i[12].IN1 -mbus_addr3_i[13] => mbus_addr3_i[13].IN1 -mbus_addr3_i[14] => mbus_addr3_i[14].IN1 -mbus_addr3_i[15] => mbus_addr3_i[15].IN1 -mbus_addr3_i[16] => mbus_addr3_i[16].IN1 -mbus_addr3_i[17] => mbus_addr3_i[17].IN1 -mbus_addr3_i[18] => mbus_addr3_i[18].IN1 -mbus_addr3_i[19] => mbus_addr3_i[19].IN1 -mbus_addr3_i[20] => mbus_addr3_i[20].IN1 -mbus_addr3_i[21] => mbus_addr3_i[21].IN1 -mbus_addr3_i[22] => mbus_addr3_i[22].IN1 -mbus_addr3_i[23] => mbus_addr3_i[23].IN1 -mbus_addr3_i[24] => mbus_addr3_i[24].IN1 -mbus_addr3_i[25] => mbus_addr3_i[25].IN1 -mbus_addr3_i[26] => mbus_addr3_i[26].IN1 -mbus_addr3_i[27] => mbus_addr3_i[27].IN1 -mbus_addr3_i[28] => mbus_addr3_i[28].IN1 -mbus_addr3_i[29] => mbus_addr3_i[29].IN1 -mbus_addr3_i[30] => mbus_addr3_i[30].IN1 -mbus_addr3_i[31] => mbus_addr3_i[31].IN1 -mbus_addr2_i[0] => mbus_addr2_i[0].IN1 -mbus_addr2_i[1] => mbus_addr2_i[1].IN1 -mbus_addr2_i[2] => mbus_addr2_i[2].IN1 -mbus_addr2_i[3] => mbus_addr2_i[3].IN1 -mbus_addr2_i[4] => mbus_addr2_i[4].IN1 -mbus_addr2_i[5] => mbus_addr2_i[5].IN1 -mbus_addr2_i[6] => mbus_addr2_i[6].IN1 -mbus_addr2_i[7] => mbus_addr2_i[7].IN1 -mbus_addr2_i[8] => mbus_addr2_i[8].IN1 -mbus_addr2_i[9] => mbus_addr2_i[9].IN1 -mbus_addr2_i[10] => mbus_addr2_i[10].IN1 -mbus_addr2_i[11] => mbus_addr2_i[11].IN1 -mbus_addr2_i[12] => mbus_addr2_i[12].IN1 -mbus_addr2_i[13] => mbus_addr2_i[13].IN1 -mbus_addr2_i[14] => mbus_addr2_i[14].IN1 -mbus_addr2_i[15] => mbus_addr2_i[15].IN1 -mbus_addr2_i[16] => mbus_addr2_i[16].IN1 -mbus_addr2_i[17] => mbus_addr2_i[17].IN1 -mbus_addr2_i[18] => mbus_addr2_i[18].IN1 -mbus_addr2_i[19] => mbus_addr2_i[19].IN1 -mbus_addr2_i[20] => mbus_addr2_i[20].IN1 -mbus_addr2_i[21] => mbus_addr2_i[21].IN1 -mbus_addr2_i[22] => mbus_addr2_i[22].IN1 -mbus_addr2_i[23] => mbus_addr2_i[23].IN1 -mbus_addr2_i[24] => mbus_addr2_i[24].IN1 -mbus_addr2_i[25] => mbus_addr2_i[25].IN1 -mbus_addr2_i[26] => mbus_addr2_i[26].IN1 -mbus_addr2_i[27] => mbus_addr2_i[27].IN1 -mbus_addr2_i[28] => mbus_addr2_i[28].IN1 -mbus_addr2_i[29] => mbus_addr2_i[29].IN1 -mbus_addr2_i[30] => mbus_addr2_i[30].IN1 -mbus_addr2_i[31] => mbus_addr2_i[31].IN1 -mbus_addr1_i[0] => mbus_addr1_i[0].IN1 -mbus_addr1_i[1] => mbus_addr1_i[1].IN1 -mbus_addr1_i[2] => mbus_addr1_i[2].IN1 -mbus_addr1_i[3] => mbus_addr1_i[3].IN1 -mbus_addr1_i[4] => mbus_addr1_i[4].IN1 -mbus_addr1_i[5] => mbus_addr1_i[5].IN1 -mbus_addr1_i[6] => mbus_addr1_i[6].IN1 -mbus_addr1_i[7] => mbus_addr1_i[7].IN1 -mbus_addr1_i[8] => mbus_addr1_i[8].IN1 -mbus_addr1_i[9] => mbus_addr1_i[9].IN1 -mbus_addr1_i[10] => mbus_addr1_i[10].IN1 -mbus_addr1_i[11] => mbus_addr1_i[11].IN1 -mbus_addr1_i[12] => mbus_addr1_i[12].IN1 -mbus_addr1_i[13] => mbus_addr1_i[13].IN1 -mbus_addr1_i[14] => mbus_addr1_i[14].IN1 -mbus_addr1_i[15] => mbus_addr1_i[15].IN1 -mbus_addr1_i[16] => mbus_addr1_i[16].IN1 -mbus_addr1_i[17] => mbus_addr1_i[17].IN1 -mbus_addr1_i[18] => mbus_addr1_i[18].IN1 -mbus_addr1_i[19] => mbus_addr1_i[19].IN1 -mbus_addr1_i[20] => mbus_addr1_i[20].IN1 -mbus_addr1_i[21] => mbus_addr1_i[21].IN1 -mbus_addr1_i[22] => mbus_addr1_i[22].IN1 -mbus_addr1_i[23] => mbus_addr1_i[23].IN1 -mbus_addr1_i[24] => mbus_addr1_i[24].IN1 -mbus_addr1_i[25] => mbus_addr1_i[25].IN1 -mbus_addr1_i[26] => mbus_addr1_i[26].IN1 -mbus_addr1_i[27] => mbus_addr1_i[27].IN1 -mbus_addr1_i[28] => mbus_addr1_i[28].IN1 -mbus_addr1_i[29] => mbus_addr1_i[29].IN1 -mbus_addr1_i[30] => mbus_addr1_i[30].IN1 -mbus_addr1_i[31] => mbus_addr1_i[31].IN1 -mbus_addr0_i[0] => mbus_addr0_i[0].IN1 -mbus_addr0_i[1] => mbus_addr0_i[1].IN1 -mbus_addr0_i[2] => mbus_addr0_i[2].IN1 -mbus_addr0_i[3] => mbus_addr0_i[3].IN1 -mbus_addr0_i[4] => mbus_addr0_i[4].IN1 -mbus_addr0_i[5] => mbus_addr0_i[5].IN1 -mbus_addr0_i[6] => mbus_addr0_i[6].IN1 -mbus_addr0_i[7] => mbus_addr0_i[7].IN1 -mbus_addr0_i[8] => mbus_addr0_i[8].IN1 -mbus_addr0_i[9] => mbus_addr0_i[9].IN1 -mbus_addr0_i[10] => mbus_addr0_i[10].IN1 -mbus_addr0_i[11] => mbus_addr0_i[11].IN1 -mbus_addr0_i[12] => mbus_addr0_i[12].IN1 -mbus_addr0_i[13] => mbus_addr0_i[13].IN1 -mbus_addr0_i[14] => mbus_addr0_i[14].IN1 -mbus_addr0_i[15] => mbus_addr0_i[15].IN1 -mbus_addr0_i[16] => mbus_addr0_i[16].IN1 -mbus_addr0_i[17] => mbus_addr0_i[17].IN1 -mbus_addr0_i[18] => mbus_addr0_i[18].IN1 -mbus_addr0_i[19] => mbus_addr0_i[19].IN1 -mbus_addr0_i[20] => mbus_addr0_i[20].IN1 -mbus_addr0_i[21] => mbus_addr0_i[21].IN1 -mbus_addr0_i[22] => mbus_addr0_i[22].IN1 -mbus_addr0_i[23] => mbus_addr0_i[23].IN1 -mbus_addr0_i[24] => mbus_addr0_i[24].IN1 -mbus_addr0_i[25] => mbus_addr0_i[25].IN1 -mbus_addr0_i[26] => mbus_addr0_i[26].IN1 -mbus_addr0_i[27] => mbus_addr0_i[27].IN1 -mbus_addr0_i[28] => mbus_addr0_i[28].IN1 -mbus_addr0_i[29] => mbus_addr0_i[29].IN1 -mbus_addr0_i[30] => mbus_addr0_i[30].IN1 -mbus_addr0_i[31] => mbus_addr0_i[31].IN1 -cbus_ack3_i => cbus_ack3_i.IN1 -cbus_ack2_i => cbus_ack2_i.IN1 -cbus_ack1_i => cbus_ack1_i.IN1 -cbus_ack0_i => cbus_ack0_i.IN1 -cbus_addr_o[0] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[1] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[2] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[3] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[4] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[5] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[6] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[7] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[8] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[9] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[10] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[11] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[12] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[13] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[14] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[15] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[16] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[17] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[18] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[19] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[20] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[21] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[22] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[23] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[24] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[25] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[26] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[27] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[28] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[29] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[30] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_addr_o[31] <= mesi_isc_broad:mesi_isc_broad.cbus_addr_o -cbus_cmd3_o[0] <= mesi_isc_broad:mesi_isc_broad.cbus_cmd_array_o -cbus_cmd3_o[1] <= mesi_isc_broad:mesi_isc_broad.cbus_cmd_array_o -cbus_cmd3_o[2] <= mesi_isc_broad:mesi_isc_broad.cbus_cmd_array_o -cbus_cmd2_o[0] <= mesi_isc_broad:mesi_isc_broad.cbus_cmd_array_o -cbus_cmd2_o[1] <= mesi_isc_broad:mesi_isc_broad.cbus_cmd_array_o -cbus_cmd2_o[2] <= mesi_isc_broad:mesi_isc_broad.cbus_cmd_array_o -cbus_cmd1_o[0] <= mesi_isc_broad:mesi_isc_broad.cbus_cmd_array_o -cbus_cmd1_o[1] <= mesi_isc_broad:mesi_isc_broad.cbus_cmd_array_o -cbus_cmd1_o[2] <= mesi_isc_broad:mesi_isc_broad.cbus_cmd_array_o -cbus_cmd0_o[0] <= mesi_isc_broad:mesi_isc_broad.cbus_cmd_array_o -cbus_cmd0_o[1] <= mesi_isc_broad:mesi_isc_broad.cbus_cmd_array_o -cbus_cmd0_o[2] <= mesi_isc_broad:mesi_isc_broad.cbus_cmd_array_o -mbus_ack3_o <= mesi_isc_breq_fifos:mesi_isc_breq_fifos.mbus_ack_array_o -mbus_ack2_o <= mesi_isc_breq_fifos:mesi_isc_breq_fifos.mbus_ack_array_o -mbus_ack1_o <= mesi_isc_breq_fifos:mesi_isc_breq_fifos.mbus_ack_array_o -mbus_ack0_o <= mesi_isc_breq_fifos:mesi_isc_breq_fifos.mbus_ack_array_o - - -|mesi_isc|mesi_isc_broad:mesi_isc_broad -clk => clk.IN2 -rst => rst.IN2 -cbus_ack_array_i[0] => cbus_ack_array_i[0].IN1 -cbus_ack_array_i[1] => cbus_ack_array_i[1].IN1 -cbus_ack_array_i[2] => cbus_ack_array_i[2].IN1 -cbus_ack_array_i[3] => cbus_ack_array_i[3].IN1 -broad_fifo_wr_i => broad_fifo_wr_i.IN1 -broad_addr_i[0] => broad_addr_i[0].IN1 -broad_addr_i[1] => broad_addr_i[1].IN1 -broad_addr_i[2] => broad_addr_i[2].IN1 -broad_addr_i[3] => broad_addr_i[3].IN1 -broad_addr_i[4] => broad_addr_i[4].IN1 -broad_addr_i[5] => broad_addr_i[5].IN1 -broad_addr_i[6] => broad_addr_i[6].IN1 -broad_addr_i[7] => broad_addr_i[7].IN1 -broad_addr_i[8] => broad_addr_i[8].IN1 -broad_addr_i[9] => broad_addr_i[9].IN1 -broad_addr_i[10] => broad_addr_i[10].IN1 -broad_addr_i[11] => broad_addr_i[11].IN1 -broad_addr_i[12] => broad_addr_i[12].IN1 -broad_addr_i[13] => broad_addr_i[13].IN1 -broad_addr_i[14] => broad_addr_i[14].IN1 -broad_addr_i[15] => broad_addr_i[15].IN1 -broad_addr_i[16] => broad_addr_i[16].IN1 -broad_addr_i[17] => broad_addr_i[17].IN1 -broad_addr_i[18] => broad_addr_i[18].IN1 -broad_addr_i[19] => broad_addr_i[19].IN1 -broad_addr_i[20] => broad_addr_i[20].IN1 -broad_addr_i[21] => broad_addr_i[21].IN1 -broad_addr_i[22] => broad_addr_i[22].IN1 -broad_addr_i[23] => broad_addr_i[23].IN1 -broad_addr_i[24] => broad_addr_i[24].IN1 -broad_addr_i[25] => broad_addr_i[25].IN1 -broad_addr_i[26] => broad_addr_i[26].IN1 -broad_addr_i[27] => broad_addr_i[27].IN1 -broad_addr_i[28] => broad_addr_i[28].IN1 -broad_addr_i[29] => broad_addr_i[29].IN1 -broad_addr_i[30] => broad_addr_i[30].IN1 -broad_addr_i[31] => broad_addr_i[31].IN1 -broad_type_i[0] => broad_type_i[0].IN1 -broad_type_i[1] => broad_type_i[1].IN1 -broad_cpu_id_i[0] => broad_cpu_id_i[0].IN1 -broad_cpu_id_i[1] => broad_cpu_id_i[1].IN1 -broad_id_i[0] => broad_id_i[0].IN1 -broad_id_i[1] => broad_id_i[1].IN1 -broad_id_i[2] => broad_id_i[2].IN1 -broad_id_i[3] => broad_id_i[3].IN1 -broad_id_i[4] => broad_id_i[4].IN1 -cbus_addr_o[0] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[1] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[2] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[3] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[4] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[5] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[6] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[7] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[8] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[9] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[10] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[11] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[12] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[13] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[14] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[15] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[16] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[17] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[18] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[19] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[20] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[21] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[22] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[23] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[24] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[25] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[26] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[27] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[28] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[29] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[30] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_addr_o[31] <= mesi_isc_basic_fifo:broad_fifo.data_o -cbus_cmd_array_o[0] <= mesi_isc_broad_cntl:mesi_isc_broad_cntl.cbus_cmd_array_o -cbus_cmd_array_o[1] <= mesi_isc_broad_cntl:mesi_isc_broad_cntl.cbus_cmd_array_o -cbus_cmd_array_o[2] <= mesi_isc_broad_cntl:mesi_isc_broad_cntl.cbus_cmd_array_o -cbus_cmd_array_o[3] <= mesi_isc_broad_cntl:mesi_isc_broad_cntl.cbus_cmd_array_o -cbus_cmd_array_o[4] <= mesi_isc_broad_cntl:mesi_isc_broad_cntl.cbus_cmd_array_o -cbus_cmd_array_o[5] <= mesi_isc_broad_cntl:mesi_isc_broad_cntl.cbus_cmd_array_o -cbus_cmd_array_o[6] <= mesi_isc_broad_cntl:mesi_isc_broad_cntl.cbus_cmd_array_o -cbus_cmd_array_o[7] <= mesi_isc_broad_cntl:mesi_isc_broad_cntl.cbus_cmd_array_o -cbus_cmd_array_o[8] <= mesi_isc_broad_cntl:mesi_isc_broad_cntl.cbus_cmd_array_o -cbus_cmd_array_o[9] <= mesi_isc_broad_cntl:mesi_isc_broad_cntl.cbus_cmd_array_o -cbus_cmd_array_o[10] <= mesi_isc_broad_cntl:mesi_isc_broad_cntl.cbus_cmd_array_o -cbus_cmd_array_o[11] <= mesi_isc_broad_cntl:mesi_isc_broad_cntl.cbus_cmd_array_o -fifo_status_full_o <= fifo_status_full.DB_MAX_OUTPUT_PORT_TYPE - - -|mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl -clk => broad_fifo_rd_o~reg0.CLK -clk => cbus_active_en_access_array[0].CLK -clk => cbus_active_en_access_array[1].CLK -clk => cbus_active_en_access_array[2].CLK -clk => cbus_active_en_access_array[3].CLK -clk => cbus_active_broad_array[0].CLK -clk => cbus_active_broad_array[1].CLK -clk => cbus_active_broad_array[2].CLK -clk => cbus_active_broad_array[3].CLK -clk => broadcast_in_progress.CLK -rst => broad_fifo_rd_o~reg0.ACLR -rst => cbus_active_en_access_array[0].ACLR -rst => cbus_active_en_access_array[1].ACLR -rst => cbus_active_en_access_array[2].ACLR -rst => cbus_active_en_access_array[3].ACLR -rst => cbus_active_broad_array[0].ACLR -rst => cbus_active_broad_array[1].ACLR -rst => cbus_active_broad_array[2].ACLR -rst => cbus_active_broad_array[3].ACLR -rst => broadcast_in_progress.ACLR -cbus_ack_array_i[0] => cbus_active_en_access_and_not_cbus_ack_array[0].IN1 -cbus_ack_array_i[0] => cbus_active_broad_array.IN1 -cbus_ack_array_i[1] => cbus_active_en_access_and_not_cbus_ack_array[1].IN1 -cbus_ack_array_i[1] => cbus_active_broad_array.IN1 -cbus_ack_array_i[2] => cbus_active_en_access_and_not_cbus_ack_array[2].IN1 -cbus_ack_array_i[2] => cbus_active_broad_array.IN1 -cbus_ack_array_i[3] => cbus_active_en_access_and_not_cbus_ack_array[3].IN1 -cbus_ack_array_i[3] => cbus_active_broad_array.IN1 -fifo_status_empty_i => cbus_active_broad_array.OUTPUTSELECT -fifo_status_empty_i => cbus_active_broad_array.OUTPUTSELECT -fifo_status_empty_i => cbus_active_broad_array.OUTPUTSELECT -fifo_status_empty_i => cbus_active_broad_array.OUTPUTSELECT -fifo_status_empty_i => cbus_active_en_access_array.OUTPUTSELECT -fifo_status_empty_i => cbus_active_en_access_array.OUTPUTSELECT -fifo_status_empty_i => cbus_active_en_access_array.OUTPUTSELECT -fifo_status_empty_i => cbus_active_en_access_array.OUTPUTSELECT -fifo_status_empty_i => broadcast_in_progress.DATAB -fifo_status_almost_empty_i => ~NO_FANOUT~ -fifo_status_full_i => ~NO_FANOUT~ -fifo_status_almost_full_i => ~NO_FANOUT~ -broad_snoop_type_i[0] => Equal0.IN0 -broad_snoop_type_i[1] => Equal0.IN1 -broad_snoop_cpu_id_i[0] => Decoder0.IN1 -broad_snoop_cpu_id_i[1] => Decoder0.IN0 -broad_snoop_id_i[0] => ~NO_FANOUT~ -broad_snoop_id_i[1] => ~NO_FANOUT~ -broad_snoop_id_i[2] => ~NO_FANOUT~ -broad_snoop_id_i[3] => ~NO_FANOUT~ -broad_snoop_id_i[4] => ~NO_FANOUT~ -cbus_cmd_array_o[0] <= cbus_cmd0.DB_MAX_OUTPUT_PORT_TYPE -cbus_cmd_array_o[1] <= cbus_cmd0.DB_MAX_OUTPUT_PORT_TYPE -cbus_cmd_array_o[2] <= cbus_cmd0.DB_MAX_OUTPUT_PORT_TYPE -cbus_cmd_array_o[3] <= cbus_cmd1.DB_MAX_OUTPUT_PORT_TYPE -cbus_cmd_array_o[4] <= cbus_cmd1.DB_MAX_OUTPUT_PORT_TYPE -cbus_cmd_array_o[5] <= cbus_cmd1.DB_MAX_OUTPUT_PORT_TYPE -cbus_cmd_array_o[6] <= cbus_cmd2.DB_MAX_OUTPUT_PORT_TYPE -cbus_cmd_array_o[7] <= cbus_cmd2.DB_MAX_OUTPUT_PORT_TYPE -cbus_cmd_array_o[8] <= cbus_cmd2.DB_MAX_OUTPUT_PORT_TYPE -cbus_cmd_array_o[9] <= cbus_cmd3.DB_MAX_OUTPUT_PORT_TYPE -cbus_cmd_array_o[10] <= cbus_cmd3.DB_MAX_OUTPUT_PORT_TYPE -cbus_cmd_array_o[11] <= cbus_cmd3.DB_MAX_OUTPUT_PORT_TYPE -broad_fifo_rd_o <= broad_fifo_rd_o~reg0.DB_MAX_OUTPUT_PORT_TYPE - - -|mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo -clk => status_full.CLK -clk => status_empty.CLK -clk => ptr_rd[0].CLK -clk => ptr_rd[1].CLK -clk => data_o[0]~reg0.CLK -clk => data_o[1]~reg0.CLK -clk => data_o[2]~reg0.CLK -clk => data_o[3]~reg0.CLK -clk => data_o[4]~reg0.CLK -clk => data_o[5]~reg0.CLK -clk => data_o[6]~reg0.CLK -clk => data_o[7]~reg0.CLK -clk => data_o[8]~reg0.CLK -clk => data_o[9]~reg0.CLK -clk => data_o[10]~reg0.CLK -clk => data_o[11]~reg0.CLK -clk => data_o[12]~reg0.CLK -clk => data_o[13]~reg0.CLK -clk => data_o[14]~reg0.CLK -clk => data_o[15]~reg0.CLK -clk => data_o[16]~reg0.CLK -clk => data_o[17]~reg0.CLK -clk => data_o[18]~reg0.CLK -clk => data_o[19]~reg0.CLK -clk => data_o[20]~reg0.CLK -clk => data_o[21]~reg0.CLK -clk => data_o[22]~reg0.CLK -clk => data_o[23]~reg0.CLK -clk => data_o[24]~reg0.CLK -clk => data_o[25]~reg0.CLK -clk => data_o[26]~reg0.CLK -clk => data_o[27]~reg0.CLK -clk => data_o[28]~reg0.CLK -clk => data_o[29]~reg0.CLK -clk => data_o[30]~reg0.CLK -clk => data_o[31]~reg0.CLK -clk => data_o[32]~reg0.CLK -clk => data_o[33]~reg0.CLK -clk => data_o[34]~reg0.CLK -clk => data_o[35]~reg0.CLK -clk => data_o[36]~reg0.CLK -clk => data_o[37]~reg0.CLK -clk => data_o[38]~reg0.CLK -clk => data_o[39]~reg0.CLK -clk => data_o[40]~reg0.CLK -clk => ptr_wr[0].CLK -clk => ptr_wr[1].CLK -clk => entry[0][0].CLK -clk => entry[0][1].CLK -clk => entry[0][2].CLK -clk => entry[0][3].CLK -clk => entry[0][4].CLK -clk => entry[0][5].CLK -clk => entry[0][6].CLK -clk => entry[0][7].CLK -clk => entry[0][8].CLK -clk => entry[0][9].CLK -clk => entry[0][10].CLK -clk => entry[0][11].CLK -clk => entry[0][12].CLK -clk => entry[0][13].CLK -clk => entry[0][14].CLK -clk => entry[0][15].CLK -clk => entry[0][16].CLK -clk => entry[0][17].CLK -clk => entry[0][18].CLK -clk => entry[0][19].CLK -clk => entry[0][20].CLK -clk => entry[0][21].CLK -clk => entry[0][22].CLK -clk => entry[0][23].CLK -clk => entry[0][24].CLK -clk => entry[0][25].CLK -clk => entry[0][26].CLK -clk => entry[0][27].CLK -clk => entry[0][28].CLK -clk => entry[0][29].CLK -clk => entry[0][30].CLK -clk => entry[0][31].CLK -clk => entry[0][32].CLK -clk => entry[0][33].CLK -clk => entry[0][34].CLK -clk => entry[0][35].CLK -clk => entry[0][36].CLK -clk => entry[0][37].CLK -clk => entry[0][38].CLK -clk => entry[0][39].CLK -clk => entry[0][40].CLK -clk => entry[1][0].CLK -clk => entry[1][1].CLK -clk => entry[1][2].CLK -clk => entry[1][3].CLK -clk => entry[1][4].CLK -clk => entry[1][5].CLK -clk => entry[1][6].CLK -clk => entry[1][7].CLK -clk => entry[1][8].CLK -clk => entry[1][9].CLK -clk => entry[1][10].CLK -clk => entry[1][11].CLK -clk => entry[1][12].CLK -clk => entry[1][13].CLK -clk => entry[1][14].CLK -clk => entry[1][15].CLK -clk => entry[1][16].CLK -clk => entry[1][17].CLK -clk => entry[1][18].CLK -clk => entry[1][19].CLK -clk => entry[1][20].CLK -clk => entry[1][21].CLK -clk => entry[1][22].CLK -clk => entry[1][23].CLK -clk => entry[1][24].CLK -clk => entry[1][25].CLK -clk => entry[1][26].CLK -clk => entry[1][27].CLK -clk => entry[1][28].CLK -clk => entry[1][29].CLK -clk => entry[1][30].CLK -clk => entry[1][31].CLK -clk => entry[1][32].CLK -clk => entry[1][33].CLK -clk => entry[1][34].CLK -clk => entry[1][35].CLK -clk => entry[1][36].CLK -clk => entry[1][37].CLK -clk => entry[1][38].CLK -clk => entry[1][39].CLK -clk => entry[1][40].CLK -clk => entry[2][0].CLK -clk => entry[2][1].CLK -clk => entry[2][2].CLK -clk => entry[2][3].CLK -clk => entry[2][4].CLK -clk => entry[2][5].CLK -clk => entry[2][6].CLK -clk => entry[2][7].CLK -clk => entry[2][8].CLK -clk => entry[2][9].CLK -clk => entry[2][10].CLK -clk => entry[2][11].CLK -clk => entry[2][12].CLK -clk => entry[2][13].CLK -clk => entry[2][14].CLK -clk => entry[2][15].CLK -clk => entry[2][16].CLK -clk => entry[2][17].CLK -clk => entry[2][18].CLK -clk => entry[2][19].CLK -clk => entry[2][20].CLK -clk => entry[2][21].CLK -clk => entry[2][22].CLK -clk => entry[2][23].CLK -clk => entry[2][24].CLK -clk => entry[2][25].CLK -clk => entry[2][26].CLK -clk => entry[2][27].CLK -clk => entry[2][28].CLK -clk => entry[2][29].CLK -clk => entry[2][30].CLK -clk => entry[2][31].CLK -clk => entry[2][32].CLK -clk => entry[2][33].CLK -clk => entry[2][34].CLK -clk => entry[2][35].CLK -clk => entry[2][36].CLK -clk => entry[2][37].CLK -clk => entry[2][38].CLK -clk => entry[2][39].CLK -clk => entry[2][40].CLK -clk => entry[3][0].CLK -clk => entry[3][1].CLK -clk => entry[3][2].CLK -clk => entry[3][3].CLK -clk => entry[3][4].CLK -clk => entry[3][5].CLK -clk => entry[3][6].CLK -clk => entry[3][7].CLK -clk => entry[3][8].CLK -clk => entry[3][9].CLK -clk => entry[3][10].CLK -clk => entry[3][11].CLK -clk => entry[3][12].CLK -clk => entry[3][13].CLK -clk => entry[3][14].CLK -clk => entry[3][15].CLK -clk => entry[3][16].CLK -clk => entry[3][17].CLK -clk => entry[3][18].CLK -clk => entry[3][19].CLK -clk => entry[3][20].CLK -clk => entry[3][21].CLK -clk => entry[3][22].CLK -clk => entry[3][23].CLK -clk => entry[3][24].CLK -clk => entry[3][25].CLK -clk => entry[3][26].CLK -clk => entry[3][27].CLK -clk => entry[3][28].CLK -clk => entry[3][29].CLK -clk => entry[3][30].CLK -clk => entry[3][31].CLK -clk => entry[3][32].CLK -clk => entry[3][33].CLK -clk => entry[3][34].CLK -clk => entry[3][35].CLK -clk => entry[3][36].CLK -clk => entry[3][37].CLK -clk => entry[3][38].CLK -clk => entry[3][39].CLK -clk => entry[3][40].CLK -rst => status_full.ACLR -rst => status_empty.PRESET -rst => ptr_rd[0].ACLR -rst => ptr_rd[1].ACLR -rst => data_o[0]~reg0.ACLR -rst => data_o[1]~reg0.ACLR -rst => data_o[2]~reg0.ACLR -rst => data_o[3]~reg0.ACLR -rst => data_o[4]~reg0.ACLR -rst => data_o[5]~reg0.ACLR -rst => data_o[6]~reg0.ACLR -rst => data_o[7]~reg0.ACLR -rst => data_o[8]~reg0.ACLR -rst => data_o[9]~reg0.ACLR -rst => data_o[10]~reg0.ACLR -rst => data_o[11]~reg0.ACLR -rst => data_o[12]~reg0.ACLR -rst => data_o[13]~reg0.ACLR -rst => data_o[14]~reg0.ACLR -rst => data_o[15]~reg0.ACLR -rst => data_o[16]~reg0.ACLR -rst => data_o[17]~reg0.ACLR -rst => data_o[18]~reg0.ACLR -rst => data_o[19]~reg0.ACLR -rst => data_o[20]~reg0.ACLR -rst => data_o[21]~reg0.ACLR -rst => data_o[22]~reg0.ACLR -rst => data_o[23]~reg0.ACLR -rst => data_o[24]~reg0.ACLR -rst => data_o[25]~reg0.ACLR -rst => data_o[26]~reg0.ACLR -rst => data_o[27]~reg0.ACLR -rst => data_o[28]~reg0.ACLR -rst => data_o[29]~reg0.ACLR -rst => data_o[30]~reg0.ACLR -rst => data_o[31]~reg0.ACLR -rst => data_o[32]~reg0.ACLR -rst => data_o[33]~reg0.ACLR -rst => data_o[34]~reg0.ACLR -rst => data_o[35]~reg0.ACLR -rst => data_o[36]~reg0.ACLR -rst => data_o[37]~reg0.ACLR -rst => data_o[38]~reg0.ACLR -rst => data_o[39]~reg0.ACLR -rst => data_o[40]~reg0.ACLR -rst => ptr_wr[0].ACLR -rst => ptr_wr[1].ACLR -rst => entry[0][0].ACLR -rst => entry[0][1].ACLR -rst => entry[0][2].ACLR -rst => entry[0][3].ACLR -rst => entry[0][4].ACLR -rst => entry[0][5].ACLR -rst => entry[0][6].ACLR -rst => entry[0][7].ACLR -rst => entry[0][8].ACLR -rst => entry[0][9].ACLR -rst => entry[0][10].ACLR -rst => entry[0][11].ACLR -rst => entry[0][12].ACLR -rst => entry[0][13].ACLR -rst => entry[0][14].ACLR -rst => entry[0][15].ACLR -rst => entry[0][16].ACLR -rst => entry[0][17].ACLR -rst => entry[0][18].ACLR -rst => entry[0][19].ACLR -rst => entry[0][20].ACLR -rst => entry[0][21].ACLR -rst => entry[0][22].ACLR -rst => entry[0][23].ACLR -rst => entry[0][24].ACLR -rst => entry[0][25].ACLR -rst => entry[0][26].ACLR -rst => entry[0][27].ACLR -rst => entry[0][28].ACLR -rst => entry[0][29].ACLR -rst => entry[0][30].ACLR -rst => entry[0][31].ACLR -rst => entry[0][32].ACLR -rst => entry[0][33].ACLR -rst => entry[0][34].ACLR -rst => entry[0][35].ACLR -rst => entry[0][36].ACLR -rst => entry[0][37].ACLR -rst => entry[0][38].ACLR -rst => entry[0][39].ACLR -rst => entry[0][40].ACLR -rst => entry[1][0].ACLR -rst => entry[1][1].ACLR -rst => entry[1][2].ACLR -rst => entry[1][3].ACLR -rst => entry[1][4].ACLR -rst => entry[1][5].ACLR -rst => entry[1][6].ACLR -rst => entry[1][7].ACLR -rst => entry[1][8].ACLR -rst => entry[1][9].ACLR -rst => entry[1][10].ACLR -rst => entry[1][11].ACLR -rst => entry[1][12].ACLR -rst => entry[1][13].ACLR -rst => entry[1][14].ACLR -rst => entry[1][15].ACLR -rst => entry[1][16].ACLR -rst => entry[1][17].ACLR -rst => entry[1][18].ACLR -rst => entry[1][19].ACLR -rst => entry[1][20].ACLR -rst => entry[1][21].ACLR -rst => entry[1][22].ACLR -rst => entry[1][23].ACLR -rst => entry[1][24].ACLR -rst => entry[1][25].ACLR -rst => entry[1][26].ACLR -rst => entry[1][27].ACLR -rst => entry[1][28].ACLR -rst => entry[1][29].ACLR -rst => entry[1][30].ACLR -rst => entry[1][31].ACLR -rst => entry[1][32].ACLR -rst => entry[1][33].ACLR -rst => entry[1][34].ACLR -rst => entry[1][35].ACLR -rst => entry[1][36].ACLR -rst => entry[1][37].ACLR -rst => entry[1][38].ACLR -rst => entry[1][39].ACLR -rst => entry[1][40].ACLR -rst => entry[2][0].ACLR -rst => entry[2][1].ACLR -rst => entry[2][2].ACLR -rst => entry[2][3].ACLR -rst => entry[2][4].ACLR -rst => entry[2][5].ACLR -rst => entry[2][6].ACLR -rst => entry[2][7].ACLR -rst => entry[2][8].ACLR -rst => entry[2][9].ACLR -rst => entry[2][10].ACLR -rst => entry[2][11].ACLR -rst => entry[2][12].ACLR -rst => entry[2][13].ACLR -rst => entry[2][14].ACLR -rst => entry[2][15].ACLR -rst => entry[2][16].ACLR -rst => entry[2][17].ACLR -rst => entry[2][18].ACLR -rst => entry[2][19].ACLR -rst => entry[2][20].ACLR -rst => entry[2][21].ACLR -rst => entry[2][22].ACLR -rst => entry[2][23].ACLR -rst => entry[2][24].ACLR -rst => entry[2][25].ACLR -rst => entry[2][26].ACLR -rst => entry[2][27].ACLR -rst => entry[2][28].ACLR -rst => entry[2][29].ACLR -rst => entry[2][30].ACLR -rst => entry[2][31].ACLR -rst => entry[2][32].ACLR -rst => entry[2][33].ACLR -rst => entry[2][34].ACLR -rst => entry[2][35].ACLR -rst => entry[2][36].ACLR -rst => entry[2][37].ACLR -rst => entry[2][38].ACLR -rst => entry[2][39].ACLR -rst => entry[2][40].ACLR -rst => entry[3][0].ACLR -rst => entry[3][1].ACLR -rst => entry[3][2].ACLR -rst => entry[3][3].ACLR -rst => entry[3][4].ACLR -rst => entry[3][5].ACLR -rst => entry[3][6].ACLR -rst => entry[3][7].ACLR -rst => entry[3][8].ACLR -rst => entry[3][9].ACLR -rst => entry[3][10].ACLR -rst => entry[3][11].ACLR -rst => entry[3][12].ACLR -rst => entry[3][13].ACLR -rst => entry[3][14].ACLR -rst => entry[3][15].ACLR -rst => entry[3][16].ACLR -rst => entry[3][17].ACLR -rst => entry[3][18].ACLR -rst => entry[3][19].ACLR -rst => entry[3][20].ACLR -rst => entry[3][21].ACLR -rst => entry[3][22].ACLR -rst => entry[3][23].ACLR -rst => entry[3][24].ACLR -rst => entry[3][25].ACLR -rst => entry[3][26].ACLR -rst => entry[3][27].ACLR -rst => entry[3][28].ACLR -rst => entry[3][29].ACLR -rst => entry[3][30].ACLR -rst => entry[3][31].ACLR -rst => entry[3][32].ACLR -rst => entry[3][33].ACLR -rst => entry[3][34].ACLR -rst => entry[3][35].ACLR -rst => entry[3][36].ACLR -rst => entry[3][37].ACLR -rst => entry[3][38].ACLR -rst => entry[3][39].ACLR -rst => entry[3][40].ACLR -wr_i => fifo_depth_increase.IN0 -wr_i => fifo_depth_decrease.IN0 -wr_i => entry[3][40].ENA -wr_i => entry[3][39].ENA -wr_i => entry[3][38].ENA -wr_i => entry[3][37].ENA -wr_i => entry[3][36].ENA -wr_i => entry[3][35].ENA -wr_i => entry[3][34].ENA -wr_i => entry[3][33].ENA -wr_i => entry[3][32].ENA -wr_i => entry[3][31].ENA -wr_i => entry[3][30].ENA -wr_i => entry[3][29].ENA -wr_i => entry[3][28].ENA -wr_i => entry[3][27].ENA -wr_i => entry[3][26].ENA -wr_i => entry[3][25].ENA -wr_i => entry[3][24].ENA -wr_i => entry[3][23].ENA -wr_i => entry[3][22].ENA -wr_i => entry[3][21].ENA -wr_i => entry[3][20].ENA -wr_i => entry[3][19].ENA -wr_i => entry[3][18].ENA -wr_i => entry[3][17].ENA -wr_i => entry[3][16].ENA -wr_i => entry[3][15].ENA -wr_i => entry[3][14].ENA -wr_i => entry[3][13].ENA -wr_i => entry[3][12].ENA -wr_i => entry[3][11].ENA -wr_i => entry[3][10].ENA -wr_i => entry[3][9].ENA -wr_i => entry[3][8].ENA -wr_i => entry[3][7].ENA -wr_i => entry[3][6].ENA -wr_i => entry[3][5].ENA -wr_i => entry[3][4].ENA -wr_i => entry[3][3].ENA -wr_i => entry[3][2].ENA -wr_i => entry[3][1].ENA -wr_i => entry[3][0].ENA -wr_i => entry[2][40].ENA -wr_i => entry[2][39].ENA -wr_i => entry[2][38].ENA -wr_i => entry[2][37].ENA -wr_i => entry[2][36].ENA -wr_i => entry[2][35].ENA -wr_i => entry[2][34].ENA -wr_i => entry[2][33].ENA -wr_i => entry[2][32].ENA -wr_i => entry[2][31].ENA -wr_i => entry[2][30].ENA -wr_i => entry[2][29].ENA -wr_i => entry[2][28].ENA -wr_i => entry[2][27].ENA -wr_i => entry[2][26].ENA -wr_i => entry[2][25].ENA -wr_i => entry[2][24].ENA -wr_i => entry[2][23].ENA -wr_i => entry[2][22].ENA -wr_i => entry[2][21].ENA -wr_i => entry[2][20].ENA -wr_i => entry[2][19].ENA -wr_i => entry[2][18].ENA -wr_i => entry[2][17].ENA -wr_i => entry[2][16].ENA -wr_i => entry[2][15].ENA -wr_i => entry[2][14].ENA -wr_i => entry[2][13].ENA -wr_i => entry[2][12].ENA -wr_i => entry[2][11].ENA -wr_i => entry[2][10].ENA -wr_i => entry[2][9].ENA -wr_i => entry[2][8].ENA -wr_i => entry[2][7].ENA -wr_i => entry[2][6].ENA -wr_i => entry[2][5].ENA -wr_i => entry[2][4].ENA -wr_i => entry[2][3].ENA -wr_i => entry[2][2].ENA -wr_i => entry[2][1].ENA -wr_i => entry[2][0].ENA -wr_i => entry[1][40].ENA -wr_i => entry[1][39].ENA -wr_i => entry[1][38].ENA -wr_i => entry[1][37].ENA -wr_i => entry[1][36].ENA -wr_i => entry[1][35].ENA -wr_i => entry[1][34].ENA -wr_i => entry[1][33].ENA -wr_i => entry[1][32].ENA -wr_i => entry[1][31].ENA -wr_i => entry[1][30].ENA -wr_i => entry[1][29].ENA -wr_i => entry[1][28].ENA -wr_i => entry[1][27].ENA -wr_i => entry[1][26].ENA -wr_i => entry[1][25].ENA -wr_i => entry[1][24].ENA -wr_i => entry[1][23].ENA -wr_i => entry[1][22].ENA -wr_i => entry[1][21].ENA -wr_i => entry[1][20].ENA -wr_i => entry[1][19].ENA -wr_i => entry[1][18].ENA -wr_i => entry[1][17].ENA -wr_i => entry[1][16].ENA -wr_i => entry[1][15].ENA -wr_i => entry[1][14].ENA -wr_i => entry[1][13].ENA -wr_i => entry[1][12].ENA -wr_i => entry[1][11].ENA -wr_i => entry[1][10].ENA -wr_i => entry[1][9].ENA -wr_i => entry[1][8].ENA -wr_i => entry[1][7].ENA -wr_i => entry[1][6].ENA -wr_i => entry[1][5].ENA -wr_i => entry[1][4].ENA -wr_i => entry[1][3].ENA -wr_i => entry[1][2].ENA -wr_i => entry[1][1].ENA -wr_i => entry[1][0].ENA -wr_i => entry[0][40].ENA -wr_i => entry[0][39].ENA -wr_i => entry[0][38].ENA -wr_i => entry[0][37].ENA -wr_i => entry[0][36].ENA -wr_i => entry[0][35].ENA -wr_i => entry[0][34].ENA -wr_i => entry[0][33].ENA -wr_i => entry[0][32].ENA -wr_i => entry[0][31].ENA -wr_i => entry[0][30].ENA -wr_i => entry[0][29].ENA -wr_i => entry[0][28].ENA -wr_i => entry[0][27].ENA -wr_i => entry[0][26].ENA -wr_i => entry[0][25].ENA -wr_i => entry[0][24].ENA -wr_i => entry[0][23].ENA -wr_i => entry[0][22].ENA -wr_i => entry[0][21].ENA -wr_i => entry[0][20].ENA -wr_i => entry[0][19].ENA -wr_i => entry[0][18].ENA -wr_i => entry[0][17].ENA -wr_i => entry[0][16].ENA -wr_i => entry[0][15].ENA -wr_i => entry[0][14].ENA -wr_i => entry[0][13].ENA -wr_i => entry[0][12].ENA -wr_i => entry[0][11].ENA -wr_i => entry[0][10].ENA -wr_i => entry[0][9].ENA -wr_i => entry[0][8].ENA -wr_i => entry[0][7].ENA -wr_i => entry[0][6].ENA -wr_i => entry[0][5].ENA -wr_i => entry[0][4].ENA -wr_i => entry[0][3].ENA -wr_i => entry[0][2].ENA -wr_i => entry[0][1].ENA -wr_i => entry[0][0].ENA -wr_i => ptr_wr[1].ENA -wr_i => ptr_wr[0].ENA -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => fifo_depth_decrease.IN1 -rd_i => fifo_depth_increase.IN1 -rd_i => ptr_rd[1].ENA -rd_i => ptr_rd[0].ENA -data_i[0] => entry.DATAB -data_i[0] => entry.DATAB -data_i[0] => entry.DATAB -data_i[0] => entry.DATAB -data_i[0] => data_o.DATAB -data_i[1] => entry.DATAB -data_i[1] => entry.DATAB -data_i[1] => entry.DATAB -data_i[1] => entry.DATAB -data_i[1] => data_o.DATAB -data_i[2] => entry.DATAB -data_i[2] => entry.DATAB -data_i[2] => entry.DATAB -data_i[2] => entry.DATAB -data_i[2] => data_o.DATAB -data_i[3] => entry.DATAB -data_i[3] => entry.DATAB -data_i[3] => entry.DATAB -data_i[3] => entry.DATAB -data_i[3] => data_o.DATAB -data_i[4] => entry.DATAB -data_i[4] => entry.DATAB -data_i[4] => entry.DATAB -data_i[4] => entry.DATAB -data_i[4] => data_o.DATAB -data_i[5] => entry.DATAB -data_i[5] => entry.DATAB -data_i[5] => entry.DATAB -data_i[5] => entry.DATAB -data_i[5] => data_o.DATAB -data_i[6] => entry.DATAB -data_i[6] => entry.DATAB -data_i[6] => entry.DATAB -data_i[6] => entry.DATAB -data_i[6] => data_o.DATAB -data_i[7] => entry.DATAB -data_i[7] => entry.DATAB -data_i[7] => entry.DATAB -data_i[7] => entry.DATAB -data_i[7] => data_o.DATAB -data_i[8] => entry.DATAB -data_i[8] => entry.DATAB -data_i[8] => entry.DATAB -data_i[8] => entry.DATAB -data_i[8] => data_o.DATAB -data_i[9] => entry.DATAB -data_i[9] => entry.DATAB -data_i[9] => entry.DATAB -data_i[9] => entry.DATAB -data_i[9] => data_o.DATAB -data_i[10] => entry.DATAB -data_i[10] => entry.DATAB -data_i[10] => entry.DATAB -data_i[10] => entry.DATAB -data_i[10] => data_o.DATAB -data_i[11] => entry.DATAB -data_i[11] => entry.DATAB -data_i[11] => entry.DATAB -data_i[11] => entry.DATAB -data_i[11] => data_o.DATAB -data_i[12] => entry.DATAB -data_i[12] => entry.DATAB -data_i[12] => entry.DATAB -data_i[12] => entry.DATAB -data_i[12] => data_o.DATAB -data_i[13] => entry.DATAB -data_i[13] => entry.DATAB -data_i[13] => entry.DATAB -data_i[13] => entry.DATAB -data_i[13] => data_o.DATAB -data_i[14] => entry.DATAB -data_i[14] => entry.DATAB -data_i[14] => entry.DATAB -data_i[14] => entry.DATAB -data_i[14] => data_o.DATAB -data_i[15] => entry.DATAB -data_i[15] => entry.DATAB -data_i[15] => entry.DATAB -data_i[15] => entry.DATAB -data_i[15] => data_o.DATAB -data_i[16] => entry.DATAB -data_i[16] => entry.DATAB -data_i[16] => entry.DATAB -data_i[16] => entry.DATAB -data_i[16] => data_o.DATAB -data_i[17] => entry.DATAB -data_i[17] => entry.DATAB -data_i[17] => entry.DATAB -data_i[17] => entry.DATAB -data_i[17] => data_o.DATAB -data_i[18] => entry.DATAB -data_i[18] => entry.DATAB -data_i[18] => entry.DATAB -data_i[18] => entry.DATAB -data_i[18] => data_o.DATAB -data_i[19] => entry.DATAB -data_i[19] => entry.DATAB -data_i[19] => entry.DATAB -data_i[19] => entry.DATAB -data_i[19] => data_o.DATAB -data_i[20] => entry.DATAB -data_i[20] => entry.DATAB -data_i[20] => entry.DATAB -data_i[20] => entry.DATAB -data_i[20] => data_o.DATAB -data_i[21] => entry.DATAB -data_i[21] => entry.DATAB -data_i[21] => entry.DATAB -data_i[21] => entry.DATAB -data_i[21] => data_o.DATAB -data_i[22] => entry.DATAB -data_i[22] => entry.DATAB -data_i[22] => entry.DATAB -data_i[22] => entry.DATAB -data_i[22] => data_o.DATAB -data_i[23] => entry.DATAB -data_i[23] => entry.DATAB -data_i[23] => entry.DATAB -data_i[23] => entry.DATAB -data_i[23] => data_o.DATAB -data_i[24] => entry.DATAB -data_i[24] => entry.DATAB -data_i[24] => entry.DATAB -data_i[24] => entry.DATAB -data_i[24] => data_o.DATAB -data_i[25] => entry.DATAB -data_i[25] => entry.DATAB -data_i[25] => entry.DATAB -data_i[25] => entry.DATAB -data_i[25] => data_o.DATAB -data_i[26] => entry.DATAB -data_i[26] => entry.DATAB -data_i[26] => entry.DATAB -data_i[26] => entry.DATAB -data_i[26] => data_o.DATAB -data_i[27] => entry.DATAB -data_i[27] => entry.DATAB -data_i[27] => entry.DATAB -data_i[27] => entry.DATAB -data_i[27] => data_o.DATAB -data_i[28] => entry.DATAB -data_i[28] => entry.DATAB -data_i[28] => entry.DATAB -data_i[28] => entry.DATAB -data_i[28] => data_o.DATAB -data_i[29] => entry.DATAB -data_i[29] => entry.DATAB -data_i[29] => entry.DATAB -data_i[29] => entry.DATAB -data_i[29] => data_o.DATAB -data_i[30] => entry.DATAB -data_i[30] => entry.DATAB -data_i[30] => entry.DATAB -data_i[30] => entry.DATAB -data_i[30] => data_o.DATAB -data_i[31] => entry.DATAB -data_i[31] => entry.DATAB -data_i[31] => entry.DATAB -data_i[31] => entry.DATAB -data_i[31] => data_o.DATAB -data_i[32] => entry.DATAB -data_i[32] => entry.DATAB -data_i[32] => entry.DATAB -data_i[32] => entry.DATAB -data_i[32] => data_o.DATAB -data_i[33] => entry.DATAB -data_i[33] => entry.DATAB -data_i[33] => entry.DATAB -data_i[33] => entry.DATAB -data_i[33] => data_o.DATAB -data_i[34] => entry.DATAB -data_i[34] => entry.DATAB -data_i[34] => entry.DATAB -data_i[34] => entry.DATAB -data_i[34] => data_o.DATAB -data_i[35] => entry.DATAB -data_i[35] => entry.DATAB -data_i[35] => entry.DATAB -data_i[35] => entry.DATAB -data_i[35] => data_o.DATAB -data_i[36] => entry.DATAB -data_i[36] => entry.DATAB -data_i[36] => entry.DATAB -data_i[36] => entry.DATAB -data_i[36] => data_o.DATAB -data_i[37] => entry.DATAB -data_i[37] => entry.DATAB -data_i[37] => entry.DATAB -data_i[37] => entry.DATAB -data_i[37] => data_o.DATAB -data_i[38] => entry.DATAB -data_i[38] => entry.DATAB -data_i[38] => entry.DATAB -data_i[38] => entry.DATAB -data_i[38] => data_o.DATAB -data_i[39] => entry.DATAB -data_i[39] => entry.DATAB -data_i[39] => entry.DATAB -data_i[39] => entry.DATAB -data_i[39] => data_o.DATAB -data_i[40] => entry.DATAB -data_i[40] => entry.DATAB -data_i[40] => entry.DATAB -data_i[40] => entry.DATAB -data_i[40] => data_o.DATAB -data_o[0] <= data_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[1] <= data_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[2] <= data_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[3] <= data_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[4] <= data_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[5] <= data_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[6] <= data_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[7] <= data_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[8] <= data_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[9] <= data_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[10] <= data_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[11] <= data_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[12] <= data_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[13] <= data_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[14] <= data_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[15] <= data_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[16] <= data_o[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[17] <= data_o[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[18] <= data_o[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[19] <= data_o[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[20] <= data_o[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[21] <= data_o[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[22] <= data_o[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[23] <= data_o[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[24] <= data_o[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[25] <= data_o[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[26] <= data_o[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[27] <= data_o[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[28] <= data_o[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[29] <= data_o[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[30] <= data_o[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[31] <= data_o[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[32] <= data_o[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[33] <= data_o[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[34] <= data_o[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[35] <= data_o[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[36] <= data_o[36]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[37] <= data_o[37]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[38] <= data_o[38]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[39] <= data_o[39]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[40] <= data_o[40]~reg0.DB_MAX_OUTPUT_PORT_TYPE -status_empty_o <= status_empty.DB_MAX_OUTPUT_PORT_TYPE -status_full_o <= status_full.DB_MAX_OUTPUT_PORT_TYPE - - -|mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos -clk => clk.IN5 -rst => rst.IN5 -mbus_cmd_array_i[0] => mbus_cmd_array_i[0].IN1 -mbus_cmd_array_i[1] => mbus_cmd_array_i[1].IN1 -mbus_cmd_array_i[2] => mbus_cmd_array_i[2].IN1 -mbus_cmd_array_i[3] => mbus_cmd_array_i[3].IN1 -mbus_cmd_array_i[4] => mbus_cmd_array_i[4].IN1 -mbus_cmd_array_i[5] => mbus_cmd_array_i[5].IN1 -mbus_cmd_array_i[6] => mbus_cmd_array_i[6].IN1 -mbus_cmd_array_i[7] => mbus_cmd_array_i[7].IN1 -mbus_cmd_array_i[8] => mbus_cmd_array_i[8].IN1 -mbus_cmd_array_i[9] => mbus_cmd_array_i[9].IN1 -mbus_cmd_array_i[10] => mbus_cmd_array_i[10].IN1 -mbus_cmd_array_i[11] => mbus_cmd_array_i[11].IN1 -mbus_addr_array_i[0] => mbus_addr_array_i[0].IN1 -mbus_addr_array_i[1] => mbus_addr_array_i[1].IN1 -mbus_addr_array_i[2] => mbus_addr_array_i[2].IN1 -mbus_addr_array_i[3] => mbus_addr_array_i[3].IN1 -mbus_addr_array_i[4] => mbus_addr_array_i[4].IN1 -mbus_addr_array_i[5] => mbus_addr_array_i[5].IN1 -mbus_addr_array_i[6] => mbus_addr_array_i[6].IN1 -mbus_addr_array_i[7] => mbus_addr_array_i[7].IN1 -mbus_addr_array_i[8] => mbus_addr_array_i[8].IN1 -mbus_addr_array_i[9] => mbus_addr_array_i[9].IN1 -mbus_addr_array_i[10] => mbus_addr_array_i[10].IN1 -mbus_addr_array_i[11] => mbus_addr_array_i[11].IN1 -mbus_addr_array_i[12] => mbus_addr_array_i[12].IN1 -mbus_addr_array_i[13] => mbus_addr_array_i[13].IN1 -mbus_addr_array_i[14] => mbus_addr_array_i[14].IN1 -mbus_addr_array_i[15] => mbus_addr_array_i[15].IN1 -mbus_addr_array_i[16] => mbus_addr_array_i[16].IN1 -mbus_addr_array_i[17] => mbus_addr_array_i[17].IN1 -mbus_addr_array_i[18] => mbus_addr_array_i[18].IN1 -mbus_addr_array_i[19] => mbus_addr_array_i[19].IN1 -mbus_addr_array_i[20] => mbus_addr_array_i[20].IN1 -mbus_addr_array_i[21] => mbus_addr_array_i[21].IN1 -mbus_addr_array_i[22] => mbus_addr_array_i[22].IN1 -mbus_addr_array_i[23] => mbus_addr_array_i[23].IN1 -mbus_addr_array_i[24] => mbus_addr_array_i[24].IN1 -mbus_addr_array_i[25] => mbus_addr_array_i[25].IN1 -mbus_addr_array_i[26] => mbus_addr_array_i[26].IN1 -mbus_addr_array_i[27] => mbus_addr_array_i[27].IN1 -mbus_addr_array_i[28] => mbus_addr_array_i[28].IN1 -mbus_addr_array_i[29] => mbus_addr_array_i[29].IN1 -mbus_addr_array_i[30] => mbus_addr_array_i[30].IN1 -mbus_addr_array_i[31] => mbus_addr_array_i[31].IN1 -mbus_addr_array_i[32] => mbus_addr_array_i[32].IN1 -mbus_addr_array_i[33] => mbus_addr_array_i[33].IN1 -mbus_addr_array_i[34] => mbus_addr_array_i[34].IN1 -mbus_addr_array_i[35] => mbus_addr_array_i[35].IN1 -mbus_addr_array_i[36] => mbus_addr_array_i[36].IN1 -mbus_addr_array_i[37] => mbus_addr_array_i[37].IN1 -mbus_addr_array_i[38] => mbus_addr_array_i[38].IN1 -mbus_addr_array_i[39] => mbus_addr_array_i[39].IN1 -mbus_addr_array_i[40] => mbus_addr_array_i[40].IN1 -mbus_addr_array_i[41] => mbus_addr_array_i[41].IN1 -mbus_addr_array_i[42] => mbus_addr_array_i[42].IN1 -mbus_addr_array_i[43] => mbus_addr_array_i[43].IN1 -mbus_addr_array_i[44] => mbus_addr_array_i[44].IN1 -mbus_addr_array_i[45] => mbus_addr_array_i[45].IN1 -mbus_addr_array_i[46] => mbus_addr_array_i[46].IN1 -mbus_addr_array_i[47] => mbus_addr_array_i[47].IN1 -mbus_addr_array_i[48] => mbus_addr_array_i[48].IN1 -mbus_addr_array_i[49] => mbus_addr_array_i[49].IN1 -mbus_addr_array_i[50] => mbus_addr_array_i[50].IN1 -mbus_addr_array_i[51] => mbus_addr_array_i[51].IN1 -mbus_addr_array_i[52] => mbus_addr_array_i[52].IN1 -mbus_addr_array_i[53] => mbus_addr_array_i[53].IN1 -mbus_addr_array_i[54] => mbus_addr_array_i[54].IN1 -mbus_addr_array_i[55] => mbus_addr_array_i[55].IN1 -mbus_addr_array_i[56] => mbus_addr_array_i[56].IN1 -mbus_addr_array_i[57] => mbus_addr_array_i[57].IN1 -mbus_addr_array_i[58] => mbus_addr_array_i[58].IN1 -mbus_addr_array_i[59] => mbus_addr_array_i[59].IN1 -mbus_addr_array_i[60] => mbus_addr_array_i[60].IN1 -mbus_addr_array_i[61] => mbus_addr_array_i[61].IN1 -mbus_addr_array_i[62] => mbus_addr_array_i[62].IN1 -mbus_addr_array_i[63] => mbus_addr_array_i[63].IN1 -mbus_addr_array_i[64] => mbus_addr_array_i[64].IN1 -mbus_addr_array_i[65] => mbus_addr_array_i[65].IN1 -mbus_addr_array_i[66] => mbus_addr_array_i[66].IN1 -mbus_addr_array_i[67] => mbus_addr_array_i[67].IN1 -mbus_addr_array_i[68] => mbus_addr_array_i[68].IN1 -mbus_addr_array_i[69] => mbus_addr_array_i[69].IN1 -mbus_addr_array_i[70] => mbus_addr_array_i[70].IN1 -mbus_addr_array_i[71] => mbus_addr_array_i[71].IN1 -mbus_addr_array_i[72] => mbus_addr_array_i[72].IN1 -mbus_addr_array_i[73] => mbus_addr_array_i[73].IN1 -mbus_addr_array_i[74] => mbus_addr_array_i[74].IN1 -mbus_addr_array_i[75] => mbus_addr_array_i[75].IN1 -mbus_addr_array_i[76] => mbus_addr_array_i[76].IN1 -mbus_addr_array_i[77] => mbus_addr_array_i[77].IN1 -mbus_addr_array_i[78] => mbus_addr_array_i[78].IN1 -mbus_addr_array_i[79] => mbus_addr_array_i[79].IN1 -mbus_addr_array_i[80] => mbus_addr_array_i[80].IN1 -mbus_addr_array_i[81] => mbus_addr_array_i[81].IN1 -mbus_addr_array_i[82] => mbus_addr_array_i[82].IN1 -mbus_addr_array_i[83] => mbus_addr_array_i[83].IN1 -mbus_addr_array_i[84] => mbus_addr_array_i[84].IN1 -mbus_addr_array_i[85] => mbus_addr_array_i[85].IN1 -mbus_addr_array_i[86] => mbus_addr_array_i[86].IN1 -mbus_addr_array_i[87] => mbus_addr_array_i[87].IN1 -mbus_addr_array_i[88] => mbus_addr_array_i[88].IN1 -mbus_addr_array_i[89] => mbus_addr_array_i[89].IN1 -mbus_addr_array_i[90] => mbus_addr_array_i[90].IN1 -mbus_addr_array_i[91] => mbus_addr_array_i[91].IN1 -mbus_addr_array_i[92] => mbus_addr_array_i[92].IN1 -mbus_addr_array_i[93] => mbus_addr_array_i[93].IN1 -mbus_addr_array_i[94] => mbus_addr_array_i[94].IN1 -mbus_addr_array_i[95] => mbus_addr_array_i[95].IN1 -mbus_addr_array_i[96] => mbus_addr_array_i[96].IN1 -mbus_addr_array_i[97] => mbus_addr_array_i[97].IN1 -mbus_addr_array_i[98] => mbus_addr_array_i[98].IN1 -mbus_addr_array_i[99] => mbus_addr_array_i[99].IN1 -mbus_addr_array_i[100] => mbus_addr_array_i[100].IN1 -mbus_addr_array_i[101] => mbus_addr_array_i[101].IN1 -mbus_addr_array_i[102] => mbus_addr_array_i[102].IN1 -mbus_addr_array_i[103] => mbus_addr_array_i[103].IN1 -mbus_addr_array_i[104] => mbus_addr_array_i[104].IN1 -mbus_addr_array_i[105] => mbus_addr_array_i[105].IN1 -mbus_addr_array_i[106] => mbus_addr_array_i[106].IN1 -mbus_addr_array_i[107] => mbus_addr_array_i[107].IN1 -mbus_addr_array_i[108] => mbus_addr_array_i[108].IN1 -mbus_addr_array_i[109] => mbus_addr_array_i[109].IN1 -mbus_addr_array_i[110] => mbus_addr_array_i[110].IN1 -mbus_addr_array_i[111] => mbus_addr_array_i[111].IN1 -mbus_addr_array_i[112] => mbus_addr_array_i[112].IN1 -mbus_addr_array_i[113] => mbus_addr_array_i[113].IN1 -mbus_addr_array_i[114] => mbus_addr_array_i[114].IN1 -mbus_addr_array_i[115] => mbus_addr_array_i[115].IN1 -mbus_addr_array_i[116] => mbus_addr_array_i[116].IN1 -mbus_addr_array_i[117] => mbus_addr_array_i[117].IN1 -mbus_addr_array_i[118] => mbus_addr_array_i[118].IN1 -mbus_addr_array_i[119] => mbus_addr_array_i[119].IN1 -mbus_addr_array_i[120] => mbus_addr_array_i[120].IN1 -mbus_addr_array_i[121] => mbus_addr_array_i[121].IN1 -mbus_addr_array_i[122] => mbus_addr_array_i[122].IN1 -mbus_addr_array_i[123] => mbus_addr_array_i[123].IN1 -mbus_addr_array_i[124] => mbus_addr_array_i[124].IN1 -mbus_addr_array_i[125] => mbus_addr_array_i[125].IN1 -mbus_addr_array_i[126] => mbus_addr_array_i[126].IN1 -mbus_addr_array_i[127] => mbus_addr_array_i[127].IN1 -broad_fifo_status_full_i => broad_fifo_status_full_i.IN1 -mbus_ack_array_o[0] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.mbus_ack_array_o -mbus_ack_array_o[1] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.mbus_ack_array_o -mbus_ack_array_o[2] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.mbus_ack_array_o -mbus_ack_array_o[3] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.mbus_ack_array_o -broad_fifo_wr_o <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_fifo_wr_o -broad_addr_o[0] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[1] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[2] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[3] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[4] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[5] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[6] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[7] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[8] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[9] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[10] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[11] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[12] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[13] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[14] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[15] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[16] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[17] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[18] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[19] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[20] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[21] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[22] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[23] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[24] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[25] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[26] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[27] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[28] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[29] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[30] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_addr_o[31] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_addr_o -broad_type_o[0] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_type_o -broad_type_o[1] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_type_o -broad_cpu_id_o[0] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_cpu_id_o -broad_cpu_id_o[1] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_cpu_id_o -broad_id_o[0] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_id_o -broad_id_o[1] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_id_o -broad_id_o[2] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_id_o -broad_id_o[3] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_id_o -broad_id_o[4] <= mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl.broad_id_o - - -|mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl -clk => breq_id_base[0].CLK -clk => breq_id_base[1].CLK -clk => breq_id_base[2].CLK -clk => breq_type_array_o[0]~reg0.CLK -clk => breq_type_array_o[1]~reg0.CLK -clk => breq_type_array_o[2]~reg0.CLK -clk => breq_type_array_o[3]~reg0.CLK -clk => breq_type_array_o[4]~reg0.CLK -clk => breq_type_array_o[5]~reg0.CLK -clk => breq_type_array_o[6]~reg0.CLK -clk => breq_type_array_o[7]~reg0.CLK -clk => mbus_ack_array[0].CLK -clk => mbus_ack_array[1].CLK -clk => mbus_ack_array[2].CLK -clk => mbus_ack_array[3].CLK -clk => fifos_priority[0].CLK -clk => fifos_priority[1].CLK -clk => fifos_priority[2].CLK -clk => fifos_priority[3].CLK -rst => breq_id_base[0].ACLR -rst => breq_id_base[1].ACLR -rst => breq_id_base[2].ACLR -rst => breq_type_array_o[0]~reg0.ACLR -rst => breq_type_array_o[1]~reg0.ACLR -rst => breq_type_array_o[2]~reg0.ACLR -rst => breq_type_array_o[3]~reg0.ACLR -rst => breq_type_array_o[4]~reg0.ACLR -rst => breq_type_array_o[5]~reg0.ACLR -rst => breq_type_array_o[6]~reg0.ACLR -rst => breq_type_array_o[7]~reg0.ACLR -rst => mbus_ack_array[0].ACLR -rst => mbus_ack_array[1].ACLR -rst => mbus_ack_array[2].ACLR -rst => mbus_ack_array[3].ACLR -rst => fifos_priority[0].PRESET -rst => fifos_priority[1].ACLR -rst => fifos_priority[2].ACLR -rst => fifos_priority[3].ACLR -mbus_cmd_array_i[0] => Equal6.IN1 -mbus_cmd_array_i[0] => Equal7.IN2 -mbus_cmd_array_i[1] => Equal6.IN0 -mbus_cmd_array_i[1] => Equal7.IN1 -mbus_cmd_array_i[2] => Equal6.IN2 -mbus_cmd_array_i[2] => Equal7.IN0 -mbus_cmd_array_i[3] => Equal4.IN1 -mbus_cmd_array_i[3] => Equal5.IN2 -mbus_cmd_array_i[4] => Equal4.IN0 -mbus_cmd_array_i[4] => Equal5.IN1 -mbus_cmd_array_i[5] => Equal4.IN2 -mbus_cmd_array_i[5] => Equal5.IN0 -mbus_cmd_array_i[6] => Equal2.IN1 -mbus_cmd_array_i[6] => Equal3.IN2 -mbus_cmd_array_i[7] => Equal2.IN0 -mbus_cmd_array_i[7] => Equal3.IN1 -mbus_cmd_array_i[8] => Equal2.IN2 -mbus_cmd_array_i[8] => Equal3.IN0 -mbus_cmd_array_i[9] => Equal0.IN1 -mbus_cmd_array_i[9] => Equal1.IN2 -mbus_cmd_array_i[10] => Equal0.IN0 -mbus_cmd_array_i[10] => Equal1.IN1 -mbus_cmd_array_i[11] => Equal0.IN2 -mbus_cmd_array_i[11] => Equal1.IN0 -fifo_status_empty_array_i[0] => fifo_select_oh.IN1 -fifo_status_empty_array_i[0] => fifo_select_oh.IN1 -fifo_status_empty_array_i[0] => fifo_select_oh.IN1 -fifo_status_empty_array_i[0] => fifo_select_oh.IN1 -fifo_status_empty_array_i[1] => fifo_select_oh.IN1 -fifo_status_empty_array_i[1] => fifo_select_oh.IN1 -fifo_status_empty_array_i[1] => fifo_select_oh.IN1 -fifo_status_empty_array_i[1] => fifo_select_oh.IN1 -fifo_status_empty_array_i[2] => fifo_select_oh.IN1 -fifo_status_empty_array_i[2] => fifo_select_oh.IN1 -fifo_status_empty_array_i[2] => fifo_select_oh.IN1 -fifo_status_empty_array_i[2] => fifo_select_oh.IN1 -fifo_status_empty_array_i[3] => fifo_select_oh.IN1 -fifo_status_empty_array_i[3] => fifo_select_oh.IN1 -fifo_status_empty_array_i[3] => fifo_select_oh.IN1 -fifo_status_empty_array_i[3] => fifo_select_oh.IN1 -fifo_status_full_array_i[0] => mbus_ack_array.IN1 -fifo_status_full_array_i[1] => mbus_ack_array.IN1 -fifo_status_full_array_i[2] => mbus_ack_array.IN1 -fifo_status_full_array_i[3] => mbus_ack_array.IN1 -broad_fifo_status_full_i => fifo_rd_array_o.IN1 -broad_fifo_status_full_i => fifo_rd_array_o.IN1 -broad_fifo_status_full_i => fifo_rd_array_o.IN1 -broad_fifo_status_full_i => fifo_rd_array_o.IN1 -broad_addr_array_i[0] => broad_addr_o.IN1 -broad_addr_array_i[1] => broad_addr_o.IN1 -broad_addr_array_i[2] => broad_addr_o.IN1 -broad_addr_array_i[3] => broad_addr_o.IN1 -broad_addr_array_i[4] => broad_addr_o.IN1 -broad_addr_array_i[5] => broad_addr_o.IN1 -broad_addr_array_i[6] => broad_addr_o.IN1 -broad_addr_array_i[7] => broad_addr_o.IN1 -broad_addr_array_i[8] => broad_addr_o.IN1 -broad_addr_array_i[9] => broad_addr_o.IN1 -broad_addr_array_i[10] => broad_addr_o.IN1 -broad_addr_array_i[11] => broad_addr_o.IN1 -broad_addr_array_i[12] => broad_addr_o.IN1 -broad_addr_array_i[13] => broad_addr_o.IN1 -broad_addr_array_i[14] => broad_addr_o.IN1 -broad_addr_array_i[15] => broad_addr_o.IN1 -broad_addr_array_i[16] => broad_addr_o.IN1 -broad_addr_array_i[17] => broad_addr_o.IN1 -broad_addr_array_i[18] => broad_addr_o.IN1 -broad_addr_array_i[19] => broad_addr_o.IN1 -broad_addr_array_i[20] => broad_addr_o.IN1 -broad_addr_array_i[21] => broad_addr_o.IN1 -broad_addr_array_i[22] => broad_addr_o.IN1 -broad_addr_array_i[23] => broad_addr_o.IN1 -broad_addr_array_i[24] => broad_addr_o.IN1 -broad_addr_array_i[25] => broad_addr_o.IN1 -broad_addr_array_i[26] => broad_addr_o.IN1 -broad_addr_array_i[27] => broad_addr_o.IN1 -broad_addr_array_i[28] => broad_addr_o.IN1 -broad_addr_array_i[29] => broad_addr_o.IN1 -broad_addr_array_i[30] => broad_addr_o.IN1 -broad_addr_array_i[31] => broad_addr_o.IN1 -broad_addr_array_i[32] => broad_addr_o.IN1 -broad_addr_array_i[33] => broad_addr_o.IN1 -broad_addr_array_i[34] => broad_addr_o.IN1 -broad_addr_array_i[35] => broad_addr_o.IN1 -broad_addr_array_i[36] => broad_addr_o.IN1 -broad_addr_array_i[37] => broad_addr_o.IN1 -broad_addr_array_i[38] => broad_addr_o.IN1 -broad_addr_array_i[39] => broad_addr_o.IN1 -broad_addr_array_i[40] => broad_addr_o.IN1 -broad_addr_array_i[41] => broad_addr_o.IN1 -broad_addr_array_i[42] => broad_addr_o.IN1 -broad_addr_array_i[43] => broad_addr_o.IN1 -broad_addr_array_i[44] => broad_addr_o.IN1 -broad_addr_array_i[45] => broad_addr_o.IN1 -broad_addr_array_i[46] => broad_addr_o.IN1 -broad_addr_array_i[47] => broad_addr_o.IN1 -broad_addr_array_i[48] => broad_addr_o.IN1 -broad_addr_array_i[49] => broad_addr_o.IN1 -broad_addr_array_i[50] => broad_addr_o.IN1 -broad_addr_array_i[51] => broad_addr_o.IN1 -broad_addr_array_i[52] => broad_addr_o.IN1 -broad_addr_array_i[53] => broad_addr_o.IN1 -broad_addr_array_i[54] => broad_addr_o.IN1 -broad_addr_array_i[55] => broad_addr_o.IN1 -broad_addr_array_i[56] => broad_addr_o.IN1 -broad_addr_array_i[57] => broad_addr_o.IN1 -broad_addr_array_i[58] => broad_addr_o.IN1 -broad_addr_array_i[59] => broad_addr_o.IN1 -broad_addr_array_i[60] => broad_addr_o.IN1 -broad_addr_array_i[61] => broad_addr_o.IN1 -broad_addr_array_i[62] => broad_addr_o.IN1 -broad_addr_array_i[63] => broad_addr_o.IN1 -broad_addr_array_i[64] => broad_addr_o.IN1 -broad_addr_array_i[65] => broad_addr_o.IN1 -broad_addr_array_i[66] => broad_addr_o.IN1 -broad_addr_array_i[67] => broad_addr_o.IN1 -broad_addr_array_i[68] => broad_addr_o.IN1 -broad_addr_array_i[69] => broad_addr_o.IN1 -broad_addr_array_i[70] => broad_addr_o.IN1 -broad_addr_array_i[71] => broad_addr_o.IN1 -broad_addr_array_i[72] => broad_addr_o.IN1 -broad_addr_array_i[73] => broad_addr_o.IN1 -broad_addr_array_i[74] => broad_addr_o.IN1 -broad_addr_array_i[75] => broad_addr_o.IN1 -broad_addr_array_i[76] => broad_addr_o.IN1 -broad_addr_array_i[77] => broad_addr_o.IN1 -broad_addr_array_i[78] => broad_addr_o.IN1 -broad_addr_array_i[79] => broad_addr_o.IN1 -broad_addr_array_i[80] => broad_addr_o.IN1 -broad_addr_array_i[81] => broad_addr_o.IN1 -broad_addr_array_i[82] => broad_addr_o.IN1 -broad_addr_array_i[83] => broad_addr_o.IN1 -broad_addr_array_i[84] => broad_addr_o.IN1 -broad_addr_array_i[85] => broad_addr_o.IN1 -broad_addr_array_i[86] => broad_addr_o.IN1 -broad_addr_array_i[87] => broad_addr_o.IN1 -broad_addr_array_i[88] => broad_addr_o.IN1 -broad_addr_array_i[89] => broad_addr_o.IN1 -broad_addr_array_i[90] => broad_addr_o.IN1 -broad_addr_array_i[91] => broad_addr_o.IN1 -broad_addr_array_i[92] => broad_addr_o.IN1 -broad_addr_array_i[93] => broad_addr_o.IN1 -broad_addr_array_i[94] => broad_addr_o.IN1 -broad_addr_array_i[95] => broad_addr_o.IN1 -broad_addr_array_i[96] => broad_addr_o.IN1 -broad_addr_array_i[97] => broad_addr_o.IN1 -broad_addr_array_i[98] => broad_addr_o.IN1 -broad_addr_array_i[99] => broad_addr_o.IN1 -broad_addr_array_i[100] => broad_addr_o.IN1 -broad_addr_array_i[101] => broad_addr_o.IN1 -broad_addr_array_i[102] => broad_addr_o.IN1 -broad_addr_array_i[103] => broad_addr_o.IN1 -broad_addr_array_i[104] => broad_addr_o.IN1 -broad_addr_array_i[105] => broad_addr_o.IN1 -broad_addr_array_i[106] => broad_addr_o.IN1 -broad_addr_array_i[107] => broad_addr_o.IN1 -broad_addr_array_i[108] => broad_addr_o.IN1 -broad_addr_array_i[109] => broad_addr_o.IN1 -broad_addr_array_i[110] => broad_addr_o.IN1 -broad_addr_array_i[111] => broad_addr_o.IN1 -broad_addr_array_i[112] => broad_addr_o.IN1 -broad_addr_array_i[113] => broad_addr_o.IN1 -broad_addr_array_i[114] => broad_addr_o.IN1 -broad_addr_array_i[115] => broad_addr_o.IN1 -broad_addr_array_i[116] => broad_addr_o.IN1 -broad_addr_array_i[117] => broad_addr_o.IN1 -broad_addr_array_i[118] => broad_addr_o.IN1 -broad_addr_array_i[119] => broad_addr_o.IN1 -broad_addr_array_i[120] => broad_addr_o.IN1 -broad_addr_array_i[121] => broad_addr_o.IN1 -broad_addr_array_i[122] => broad_addr_o.IN1 -broad_addr_array_i[123] => broad_addr_o.IN1 -broad_addr_array_i[124] => broad_addr_o.IN1 -broad_addr_array_i[125] => broad_addr_o.IN1 -broad_addr_array_i[126] => broad_addr_o.IN1 -broad_addr_array_i[127] => broad_addr_o.IN1 -broad_type_array_i[0] => broad_type_o.IN1 -broad_type_array_i[1] => broad_type_o.IN1 -broad_type_array_i[2] => broad_type_o.IN1 -broad_type_array_i[3] => broad_type_o.IN1 -broad_type_array_i[4] => broad_type_o.IN1 -broad_type_array_i[5] => broad_type_o.IN1 -broad_type_array_i[6] => broad_type_o.IN1 -broad_type_array_i[7] => broad_type_o.IN1 -broad_id_array_i[0] => broad_id_o.IN1 -broad_id_array_i[1] => broad_id_o.IN1 -broad_id_array_i[2] => broad_id_o.IN1 -broad_id_array_i[3] => broad_id_o.IN1 -broad_id_array_i[4] => broad_id_o.IN1 -broad_id_array_i[5] => broad_id_o.IN1 -broad_id_array_i[6] => broad_id_o.IN1 -broad_id_array_i[7] => broad_id_o.IN1 -broad_id_array_i[8] => broad_id_o.IN1 -broad_id_array_i[9] => broad_id_o.IN1 -broad_id_array_i[10] => broad_id_o.IN1 -broad_id_array_i[11] => broad_id_o.IN1 -broad_id_array_i[12] => broad_id_o.IN1 -broad_id_array_i[13] => broad_id_o.IN1 -broad_id_array_i[14] => broad_id_o.IN1 -broad_id_array_i[15] => broad_id_o.IN1 -broad_id_array_i[16] => broad_id_o.IN1 -broad_id_array_i[17] => broad_id_o.IN1 -broad_id_array_i[18] => broad_id_o.IN1 -broad_id_array_i[19] => broad_id_o.IN1 -mbus_ack_array_o[0] <= mbus_ack_array[0].DB_MAX_OUTPUT_PORT_TYPE -mbus_ack_array_o[1] <= mbus_ack_array[1].DB_MAX_OUTPUT_PORT_TYPE -mbus_ack_array_o[2] <= mbus_ack_array[2].DB_MAX_OUTPUT_PORT_TYPE -mbus_ack_array_o[3] <= mbus_ack_array[3].DB_MAX_OUTPUT_PORT_TYPE -fifo_wr_array_o[0] <= mbus_ack_array[0].DB_MAX_OUTPUT_PORT_TYPE -fifo_wr_array_o[1] <= mbus_ack_array[1].DB_MAX_OUTPUT_PORT_TYPE -fifo_wr_array_o[2] <= mbus_ack_array[2].DB_MAX_OUTPUT_PORT_TYPE -fifo_wr_array_o[3] <= mbus_ack_array[3].DB_MAX_OUTPUT_PORT_TYPE -fifo_rd_array_o[0] <= fifo_rd_array_o.DB_MAX_OUTPUT_PORT_TYPE -fifo_rd_array_o[1] <= fifo_rd_array_o.DB_MAX_OUTPUT_PORT_TYPE -fifo_rd_array_o[2] <= fifo_rd_array_o.DB_MAX_OUTPUT_PORT_TYPE -fifo_rd_array_o[3] <= fifo_rd_array_o.DB_MAX_OUTPUT_PORT_TYPE -broad_fifo_wr_o <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[0] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[1] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[2] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[3] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[4] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[5] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[6] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[7] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[8] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[9] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[10] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[11] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[12] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[13] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[14] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[15] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[16] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[17] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[18] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[19] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[20] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[21] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[22] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[23] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[24] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[25] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[26] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[27] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[28] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[29] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[30] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_addr_o[31] <= broad_addr_o.DB_MAX_OUTPUT_PORT_TYPE -broad_type_o[0] <= broad_type_o.DB_MAX_OUTPUT_PORT_TYPE -broad_type_o[1] <= broad_type_o.DB_MAX_OUTPUT_PORT_TYPE -broad_cpu_id_o[0] <= broad_cpu_id_o.DB_MAX_OUTPUT_PORT_TYPE -broad_cpu_id_o[1] <= broad_cpu_id_o.DB_MAX_OUTPUT_PORT_TYPE -broad_id_o[0] <= broad_id_o.DB_MAX_OUTPUT_PORT_TYPE -broad_id_o[1] <= broad_id_o.DB_MAX_OUTPUT_PORT_TYPE -broad_id_o[2] <= broad_id_o.DB_MAX_OUTPUT_PORT_TYPE -broad_id_o[3] <= broad_id_o.DB_MAX_OUTPUT_PORT_TYPE -broad_id_o[4] <= broad_id_o.DB_MAX_OUTPUT_PORT_TYPE -breq_type_array_o[0] <= breq_type_array_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -breq_type_array_o[1] <= breq_type_array_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -breq_type_array_o[2] <= breq_type_array_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -breq_type_array_o[3] <= breq_type_array_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -breq_type_array_o[4] <= breq_type_array_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -breq_type_array_o[5] <= breq_type_array_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -breq_type_array_o[6] <= breq_type_array_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -breq_type_array_o[7] <= breq_type_array_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -breq_cpu_id_array_o[0] <= -breq_cpu_id_array_o[1] <= -breq_cpu_id_array_o[2] <= -breq_cpu_id_array_o[3] <= -breq_cpu_id_array_o[4] <= -breq_cpu_id_array_o[5] <= -breq_cpu_id_array_o[6] <= -breq_cpu_id_array_o[7] <= -breq_id_array_o[0] <= -breq_id_array_o[1] <= -breq_id_array_o[2] <= breq_id_base[0].DB_MAX_OUTPUT_PORT_TYPE -breq_id_array_o[3] <= breq_id_base[1].DB_MAX_OUTPUT_PORT_TYPE -breq_id_array_o[4] <= breq_id_base[2].DB_MAX_OUTPUT_PORT_TYPE -breq_id_array_o[5] <= -breq_id_array_o[6] <= -breq_id_array_o[7] <= breq_id_base[0].DB_MAX_OUTPUT_PORT_TYPE -breq_id_array_o[8] <= breq_id_base[1].DB_MAX_OUTPUT_PORT_TYPE -breq_id_array_o[9] <= breq_id_base[2].DB_MAX_OUTPUT_PORT_TYPE -breq_id_array_o[10] <= -breq_id_array_o[11] <= -breq_id_array_o[12] <= breq_id_base[0].DB_MAX_OUTPUT_PORT_TYPE -breq_id_array_o[13] <= breq_id_base[1].DB_MAX_OUTPUT_PORT_TYPE -breq_id_array_o[14] <= breq_id_base[2].DB_MAX_OUTPUT_PORT_TYPE -breq_id_array_o[15] <= -breq_id_array_o[16] <= -breq_id_array_o[17] <= breq_id_base[0].DB_MAX_OUTPUT_PORT_TYPE -breq_id_array_o[18] <= breq_id_base[1].DB_MAX_OUTPUT_PORT_TYPE -breq_id_array_o[19] <= breq_id_base[2].DB_MAX_OUTPUT_PORT_TYPE - - -|mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3 -clk => status_full.CLK -clk => status_empty.CLK -clk => ptr_rd[0].CLK -clk => data_o[0]~reg0.CLK -clk => data_o[1]~reg0.CLK -clk => data_o[2]~reg0.CLK -clk => data_o[3]~reg0.CLK -clk => data_o[4]~reg0.CLK -clk => data_o[5]~reg0.CLK -clk => data_o[6]~reg0.CLK -clk => data_o[7]~reg0.CLK -clk => data_o[8]~reg0.CLK -clk => data_o[9]~reg0.CLK -clk => data_o[10]~reg0.CLK -clk => data_o[11]~reg0.CLK -clk => data_o[12]~reg0.CLK -clk => data_o[13]~reg0.CLK -clk => data_o[14]~reg0.CLK -clk => data_o[15]~reg0.CLK -clk => data_o[16]~reg0.CLK -clk => data_o[17]~reg0.CLK -clk => data_o[18]~reg0.CLK -clk => data_o[19]~reg0.CLK -clk => data_o[20]~reg0.CLK -clk => data_o[21]~reg0.CLK -clk => data_o[22]~reg0.CLK -clk => data_o[23]~reg0.CLK -clk => data_o[24]~reg0.CLK -clk => data_o[25]~reg0.CLK -clk => data_o[26]~reg0.CLK -clk => data_o[27]~reg0.CLK -clk => data_o[28]~reg0.CLK -clk => data_o[29]~reg0.CLK -clk => data_o[30]~reg0.CLK -clk => data_o[31]~reg0.CLK -clk => data_o[32]~reg0.CLK -clk => data_o[33]~reg0.CLK -clk => data_o[34]~reg0.CLK -clk => data_o[35]~reg0.CLK -clk => data_o[36]~reg0.CLK -clk => data_o[37]~reg0.CLK -clk => data_o[38]~reg0.CLK -clk => data_o[39]~reg0.CLK -clk => data_o[40]~reg0.CLK -clk => ptr_wr[0].CLK -clk => entry[0][0].CLK -clk => entry[0][1].CLK -clk => entry[0][2].CLK -clk => entry[0][3].CLK -clk => entry[0][4].CLK -clk => entry[0][5].CLK -clk => entry[0][6].CLK -clk => entry[0][7].CLK -clk => entry[0][8].CLK -clk => entry[0][9].CLK -clk => entry[0][10].CLK -clk => entry[0][11].CLK -clk => entry[0][12].CLK -clk => entry[0][13].CLK -clk => entry[0][14].CLK -clk => entry[0][15].CLK -clk => entry[0][16].CLK -clk => entry[0][17].CLK -clk => entry[0][18].CLK -clk => entry[0][19].CLK -clk => entry[0][20].CLK -clk => entry[0][21].CLK -clk => entry[0][22].CLK -clk => entry[0][23].CLK -clk => entry[0][24].CLK -clk => entry[0][25].CLK -clk => entry[0][26].CLK -clk => entry[0][27].CLK -clk => entry[0][28].CLK -clk => entry[0][29].CLK -clk => entry[0][30].CLK -clk => entry[0][31].CLK -clk => entry[0][32].CLK -clk => entry[0][33].CLK -clk => entry[0][34].CLK -clk => entry[0][35].CLK -clk => entry[0][36].CLK -clk => entry[0][37].CLK -clk => entry[0][38].CLK -clk => entry[0][39].CLK -clk => entry[0][40].CLK -clk => entry[1][0].CLK -clk => entry[1][1].CLK -clk => entry[1][2].CLK -clk => entry[1][3].CLK -clk => entry[1][4].CLK -clk => entry[1][5].CLK -clk => entry[1][6].CLK -clk => entry[1][7].CLK -clk => entry[1][8].CLK -clk => entry[1][9].CLK -clk => entry[1][10].CLK -clk => entry[1][11].CLK -clk => entry[1][12].CLK -clk => entry[1][13].CLK -clk => entry[1][14].CLK -clk => entry[1][15].CLK -clk => entry[1][16].CLK -clk => entry[1][17].CLK -clk => entry[1][18].CLK -clk => entry[1][19].CLK -clk => entry[1][20].CLK -clk => entry[1][21].CLK -clk => entry[1][22].CLK -clk => entry[1][23].CLK -clk => entry[1][24].CLK -clk => entry[1][25].CLK -clk => entry[1][26].CLK -clk => entry[1][27].CLK -clk => entry[1][28].CLK -clk => entry[1][29].CLK -clk => entry[1][30].CLK -clk => entry[1][31].CLK -clk => entry[1][32].CLK -clk => entry[1][33].CLK -clk => entry[1][34].CLK -clk => entry[1][35].CLK -clk => entry[1][36].CLK -clk => entry[1][37].CLK -clk => entry[1][38].CLK -clk => entry[1][39].CLK -clk => entry[1][40].CLK -rst => status_full.ACLR -rst => status_empty.PRESET -rst => ptr_rd[0].ACLR -rst => data_o[0]~reg0.ACLR -rst => data_o[1]~reg0.ACLR -rst => data_o[2]~reg0.ACLR -rst => data_o[3]~reg0.ACLR -rst => data_o[4]~reg0.ACLR -rst => data_o[5]~reg0.ACLR -rst => data_o[6]~reg0.ACLR -rst => data_o[7]~reg0.ACLR -rst => data_o[8]~reg0.ACLR -rst => data_o[9]~reg0.ACLR -rst => data_o[10]~reg0.ACLR -rst => data_o[11]~reg0.ACLR -rst => data_o[12]~reg0.ACLR -rst => data_o[13]~reg0.ACLR -rst => data_o[14]~reg0.ACLR -rst => data_o[15]~reg0.ACLR -rst => data_o[16]~reg0.ACLR -rst => data_o[17]~reg0.ACLR -rst => data_o[18]~reg0.ACLR -rst => data_o[19]~reg0.ACLR -rst => data_o[20]~reg0.ACLR -rst => data_o[21]~reg0.ACLR -rst => data_o[22]~reg0.ACLR -rst => data_o[23]~reg0.ACLR -rst => data_o[24]~reg0.ACLR -rst => data_o[25]~reg0.ACLR -rst => data_o[26]~reg0.ACLR -rst => data_o[27]~reg0.ACLR -rst => data_o[28]~reg0.ACLR -rst => data_o[29]~reg0.ACLR -rst => data_o[30]~reg0.ACLR -rst => data_o[31]~reg0.ACLR -rst => data_o[32]~reg0.ACLR -rst => data_o[33]~reg0.ACLR -rst => data_o[34]~reg0.ACLR -rst => data_o[35]~reg0.ACLR -rst => data_o[36]~reg0.ACLR -rst => data_o[37]~reg0.ACLR -rst => data_o[38]~reg0.ACLR -rst => data_o[39]~reg0.ACLR -rst => data_o[40]~reg0.ACLR -rst => ptr_wr[0].ACLR -rst => entry[0][0].ACLR -rst => entry[0][1].ACLR -rst => entry[0][2].ACLR -rst => entry[0][3].ACLR -rst => entry[0][4].ACLR -rst => entry[0][5].ACLR -rst => entry[0][6].ACLR -rst => entry[0][7].ACLR -rst => entry[0][8].ACLR -rst => entry[0][9].ACLR -rst => entry[0][10].ACLR -rst => entry[0][11].ACLR -rst => entry[0][12].ACLR -rst => entry[0][13].ACLR -rst => entry[0][14].ACLR -rst => entry[0][15].ACLR -rst => entry[0][16].ACLR -rst => entry[0][17].ACLR -rst => entry[0][18].ACLR -rst => entry[0][19].ACLR -rst => entry[0][20].ACLR -rst => entry[0][21].ACLR -rst => entry[0][22].ACLR -rst => entry[0][23].ACLR -rst => entry[0][24].ACLR -rst => entry[0][25].ACLR -rst => entry[0][26].ACLR -rst => entry[0][27].ACLR -rst => entry[0][28].ACLR -rst => entry[0][29].ACLR -rst => entry[0][30].ACLR -rst => entry[0][31].ACLR -rst => entry[0][32].ACLR -rst => entry[0][33].ACLR -rst => entry[0][34].ACLR -rst => entry[0][35].ACLR -rst => entry[0][36].ACLR -rst => entry[0][37].ACLR -rst => entry[0][38].ACLR -rst => entry[0][39].ACLR -rst => entry[0][40].ACLR -rst => entry[1][0].ACLR -rst => entry[1][1].ACLR -rst => entry[1][2].ACLR -rst => entry[1][3].ACLR -rst => entry[1][4].ACLR -rst => entry[1][5].ACLR -rst => entry[1][6].ACLR -rst => entry[1][7].ACLR -rst => entry[1][8].ACLR -rst => entry[1][9].ACLR -rst => entry[1][10].ACLR -rst => entry[1][11].ACLR -rst => entry[1][12].ACLR -rst => entry[1][13].ACLR -rst => entry[1][14].ACLR -rst => entry[1][15].ACLR -rst => entry[1][16].ACLR -rst => entry[1][17].ACLR -rst => entry[1][18].ACLR -rst => entry[1][19].ACLR -rst => entry[1][20].ACLR -rst => entry[1][21].ACLR -rst => entry[1][22].ACLR -rst => entry[1][23].ACLR -rst => entry[1][24].ACLR -rst => entry[1][25].ACLR -rst => entry[1][26].ACLR -rst => entry[1][27].ACLR -rst => entry[1][28].ACLR -rst => entry[1][29].ACLR -rst => entry[1][30].ACLR -rst => entry[1][31].ACLR -rst => entry[1][32].ACLR -rst => entry[1][33].ACLR -rst => entry[1][34].ACLR -rst => entry[1][35].ACLR -rst => entry[1][36].ACLR -rst => entry[1][37].ACLR -rst => entry[1][38].ACLR -rst => entry[1][39].ACLR -rst => entry[1][40].ACLR -wr_i => fifo_depth_increase.IN0 -wr_i => fifo_depth_decrease.IN0 -wr_i => entry[1][40].ENA -wr_i => entry[1][39].ENA -wr_i => entry[1][38].ENA -wr_i => entry[1][37].ENA -wr_i => entry[1][36].ENA -wr_i => entry[1][35].ENA -wr_i => entry[1][34].ENA -wr_i => entry[1][33].ENA -wr_i => entry[1][32].ENA -wr_i => entry[1][31].ENA -wr_i => entry[1][30].ENA -wr_i => entry[1][29].ENA -wr_i => entry[1][28].ENA -wr_i => entry[1][27].ENA -wr_i => entry[1][26].ENA -wr_i => entry[1][25].ENA -wr_i => entry[1][24].ENA -wr_i => entry[1][23].ENA -wr_i => entry[1][22].ENA -wr_i => entry[1][21].ENA -wr_i => entry[1][20].ENA -wr_i => entry[1][19].ENA -wr_i => entry[1][18].ENA -wr_i => entry[1][17].ENA -wr_i => entry[1][16].ENA -wr_i => entry[1][15].ENA -wr_i => entry[1][14].ENA -wr_i => entry[1][13].ENA -wr_i => entry[1][12].ENA -wr_i => entry[1][11].ENA -wr_i => entry[1][10].ENA -wr_i => entry[1][9].ENA -wr_i => entry[1][8].ENA -wr_i => entry[1][7].ENA -wr_i => entry[1][6].ENA -wr_i => entry[1][5].ENA -wr_i => entry[1][4].ENA -wr_i => entry[1][3].ENA -wr_i => entry[1][2].ENA -wr_i => entry[1][1].ENA -wr_i => entry[1][0].ENA -wr_i => entry[0][40].ENA -wr_i => entry[0][39].ENA -wr_i => entry[0][38].ENA -wr_i => entry[0][37].ENA -wr_i => entry[0][36].ENA -wr_i => entry[0][35].ENA -wr_i => entry[0][34].ENA -wr_i => entry[0][33].ENA -wr_i => entry[0][32].ENA -wr_i => entry[0][31].ENA -wr_i => entry[0][30].ENA -wr_i => entry[0][29].ENA -wr_i => entry[0][28].ENA -wr_i => entry[0][27].ENA -wr_i => entry[0][26].ENA -wr_i => entry[0][25].ENA -wr_i => entry[0][24].ENA -wr_i => entry[0][23].ENA -wr_i => entry[0][22].ENA -wr_i => entry[0][21].ENA -wr_i => entry[0][20].ENA -wr_i => entry[0][19].ENA -wr_i => entry[0][18].ENA -wr_i => entry[0][17].ENA -wr_i => entry[0][16].ENA -wr_i => entry[0][15].ENA -wr_i => entry[0][14].ENA -wr_i => entry[0][13].ENA -wr_i => entry[0][12].ENA -wr_i => entry[0][11].ENA -wr_i => entry[0][10].ENA -wr_i => entry[0][9].ENA -wr_i => entry[0][8].ENA -wr_i => entry[0][7].ENA -wr_i => entry[0][6].ENA -wr_i => entry[0][5].ENA -wr_i => entry[0][4].ENA -wr_i => entry[0][3].ENA -wr_i => entry[0][2].ENA -wr_i => entry[0][1].ENA -wr_i => entry[0][0].ENA -wr_i => ptr_wr[0].ENA -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => fifo_depth_decrease.IN1 -rd_i => fifo_depth_increase.IN1 -rd_i => ptr_rd[0].ENA -data_i[0] => entry.DATAB -data_i[0] => entry.DATAB -data_i[0] => data_o.DATAB -data_i[1] => entry.DATAB -data_i[1] => entry.DATAB -data_i[1] => data_o.DATAB -data_i[2] => entry.DATAB -data_i[2] => entry.DATAB -data_i[2] => data_o.DATAB -data_i[3] => entry.DATAB -data_i[3] => entry.DATAB -data_i[3] => data_o.DATAB -data_i[4] => entry.DATAB -data_i[4] => entry.DATAB -data_i[4] => data_o.DATAB -data_i[5] => entry.DATAB -data_i[5] => entry.DATAB -data_i[5] => data_o.DATAB -data_i[6] => entry.DATAB -data_i[6] => entry.DATAB -data_i[6] => data_o.DATAB -data_i[7] => entry.DATAB -data_i[7] => entry.DATAB -data_i[7] => data_o.DATAB -data_i[8] => entry.DATAB -data_i[8] => entry.DATAB -data_i[8] => data_o.DATAB -data_i[9] => entry.DATAB -data_i[9] => entry.DATAB -data_i[9] => data_o.DATAB -data_i[10] => entry.DATAB -data_i[10] => entry.DATAB -data_i[10] => data_o.DATAB -data_i[11] => entry.DATAB -data_i[11] => entry.DATAB -data_i[11] => data_o.DATAB -data_i[12] => entry.DATAB -data_i[12] => entry.DATAB -data_i[12] => data_o.DATAB -data_i[13] => entry.DATAB -data_i[13] => entry.DATAB -data_i[13] => data_o.DATAB -data_i[14] => entry.DATAB -data_i[14] => entry.DATAB -data_i[14] => data_o.DATAB -data_i[15] => entry.DATAB -data_i[15] => entry.DATAB -data_i[15] => data_o.DATAB -data_i[16] => entry.DATAB -data_i[16] => entry.DATAB -data_i[16] => data_o.DATAB -data_i[17] => entry.DATAB -data_i[17] => entry.DATAB -data_i[17] => data_o.DATAB -data_i[18] => entry.DATAB -data_i[18] => entry.DATAB -data_i[18] => data_o.DATAB -data_i[19] => entry.DATAB -data_i[19] => entry.DATAB -data_i[19] => data_o.DATAB -data_i[20] => entry.DATAB -data_i[20] => entry.DATAB -data_i[20] => data_o.DATAB -data_i[21] => entry.DATAB -data_i[21] => entry.DATAB -data_i[21] => data_o.DATAB -data_i[22] => entry.DATAB -data_i[22] => entry.DATAB -data_i[22] => data_o.DATAB -data_i[23] => entry.DATAB -data_i[23] => entry.DATAB -data_i[23] => data_o.DATAB -data_i[24] => entry.DATAB -data_i[24] => entry.DATAB -data_i[24] => data_o.DATAB -data_i[25] => entry.DATAB -data_i[25] => entry.DATAB -data_i[25] => data_o.DATAB -data_i[26] => entry.DATAB -data_i[26] => entry.DATAB -data_i[26] => data_o.DATAB -data_i[27] => entry.DATAB -data_i[27] => entry.DATAB -data_i[27] => data_o.DATAB -data_i[28] => entry.DATAB -data_i[28] => entry.DATAB -data_i[28] => data_o.DATAB -data_i[29] => entry.DATAB -data_i[29] => entry.DATAB -data_i[29] => data_o.DATAB -data_i[30] => entry.DATAB -data_i[30] => entry.DATAB -data_i[30] => data_o.DATAB -data_i[31] => entry.DATAB -data_i[31] => entry.DATAB -data_i[31] => data_o.DATAB -data_i[32] => entry.DATAB -data_i[32] => entry.DATAB -data_i[32] => data_o.DATAB -data_i[33] => entry.DATAB -data_i[33] => entry.DATAB -data_i[33] => data_o.DATAB -data_i[34] => entry.DATAB -data_i[34] => entry.DATAB -data_i[34] => data_o.DATAB -data_i[35] => entry.DATAB -data_i[35] => entry.DATAB -data_i[35] => data_o.DATAB -data_i[36] => entry.DATAB -data_i[36] => entry.DATAB -data_i[36] => data_o.DATAB -data_i[37] => entry.DATAB -data_i[37] => entry.DATAB -data_i[37] => data_o.DATAB -data_i[38] => entry.DATAB -data_i[38] => entry.DATAB -data_i[38] => data_o.DATAB -data_i[39] => entry.DATAB -data_i[39] => entry.DATAB -data_i[39] => data_o.DATAB -data_i[40] => entry.DATAB -data_i[40] => entry.DATAB -data_i[40] => data_o.DATAB -data_o[0] <= data_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[1] <= data_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[2] <= data_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[3] <= data_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[4] <= data_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[5] <= data_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[6] <= data_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[7] <= data_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[8] <= data_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[9] <= data_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[10] <= data_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[11] <= data_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[12] <= data_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[13] <= data_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[14] <= data_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[15] <= data_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[16] <= data_o[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[17] <= data_o[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[18] <= data_o[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[19] <= data_o[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[20] <= data_o[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[21] <= data_o[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[22] <= data_o[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[23] <= data_o[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[24] <= data_o[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[25] <= data_o[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[26] <= data_o[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[27] <= data_o[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[28] <= data_o[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[29] <= data_o[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[30] <= data_o[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[31] <= data_o[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[32] <= data_o[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[33] <= data_o[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[34] <= data_o[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[35] <= data_o[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[36] <= data_o[36]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[37] <= data_o[37]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[38] <= data_o[38]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[39] <= data_o[39]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[40] <= data_o[40]~reg0.DB_MAX_OUTPUT_PORT_TYPE -status_empty_o <= status_empty.DB_MAX_OUTPUT_PORT_TYPE -status_full_o <= status_full.DB_MAX_OUTPUT_PORT_TYPE - - -|mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2 -clk => status_full.CLK -clk => status_empty.CLK -clk => ptr_rd[0].CLK -clk => data_o[0]~reg0.CLK -clk => data_o[1]~reg0.CLK -clk => data_o[2]~reg0.CLK -clk => data_o[3]~reg0.CLK -clk => data_o[4]~reg0.CLK -clk => data_o[5]~reg0.CLK -clk => data_o[6]~reg0.CLK -clk => data_o[7]~reg0.CLK -clk => data_o[8]~reg0.CLK -clk => data_o[9]~reg0.CLK -clk => data_o[10]~reg0.CLK -clk => data_o[11]~reg0.CLK -clk => data_o[12]~reg0.CLK -clk => data_o[13]~reg0.CLK -clk => data_o[14]~reg0.CLK -clk => data_o[15]~reg0.CLK -clk => data_o[16]~reg0.CLK -clk => data_o[17]~reg0.CLK -clk => data_o[18]~reg0.CLK -clk => data_o[19]~reg0.CLK -clk => data_o[20]~reg0.CLK -clk => data_o[21]~reg0.CLK -clk => data_o[22]~reg0.CLK -clk => data_o[23]~reg0.CLK -clk => data_o[24]~reg0.CLK -clk => data_o[25]~reg0.CLK -clk => data_o[26]~reg0.CLK -clk => data_o[27]~reg0.CLK -clk => data_o[28]~reg0.CLK -clk => data_o[29]~reg0.CLK -clk => data_o[30]~reg0.CLK -clk => data_o[31]~reg0.CLK -clk => data_o[32]~reg0.CLK -clk => data_o[33]~reg0.CLK -clk => data_o[34]~reg0.CLK -clk => data_o[35]~reg0.CLK -clk => data_o[36]~reg0.CLK -clk => data_o[37]~reg0.CLK -clk => data_o[38]~reg0.CLK -clk => data_o[39]~reg0.CLK -clk => data_o[40]~reg0.CLK -clk => ptr_wr[0].CLK -clk => entry[0][0].CLK -clk => entry[0][1].CLK -clk => entry[0][2].CLK -clk => entry[0][3].CLK -clk => entry[0][4].CLK -clk => entry[0][5].CLK -clk => entry[0][6].CLK -clk => entry[0][7].CLK -clk => entry[0][8].CLK -clk => entry[0][9].CLK -clk => entry[0][10].CLK -clk => entry[0][11].CLK -clk => entry[0][12].CLK -clk => entry[0][13].CLK -clk => entry[0][14].CLK -clk => entry[0][15].CLK -clk => entry[0][16].CLK -clk => entry[0][17].CLK -clk => entry[0][18].CLK -clk => entry[0][19].CLK -clk => entry[0][20].CLK -clk => entry[0][21].CLK -clk => entry[0][22].CLK -clk => entry[0][23].CLK -clk => entry[0][24].CLK -clk => entry[0][25].CLK -clk => entry[0][26].CLK -clk => entry[0][27].CLK -clk => entry[0][28].CLK -clk => entry[0][29].CLK -clk => entry[0][30].CLK -clk => entry[0][31].CLK -clk => entry[0][32].CLK -clk => entry[0][33].CLK -clk => entry[0][34].CLK -clk => entry[0][35].CLK -clk => entry[0][36].CLK -clk => entry[0][37].CLK -clk => entry[0][38].CLK -clk => entry[0][39].CLK -clk => entry[0][40].CLK -clk => entry[1][0].CLK -clk => entry[1][1].CLK -clk => entry[1][2].CLK -clk => entry[1][3].CLK -clk => entry[1][4].CLK -clk => entry[1][5].CLK -clk => entry[1][6].CLK -clk => entry[1][7].CLK -clk => entry[1][8].CLK -clk => entry[1][9].CLK -clk => entry[1][10].CLK -clk => entry[1][11].CLK -clk => entry[1][12].CLK -clk => entry[1][13].CLK -clk => entry[1][14].CLK -clk => entry[1][15].CLK -clk => entry[1][16].CLK -clk => entry[1][17].CLK -clk => entry[1][18].CLK -clk => entry[1][19].CLK -clk => entry[1][20].CLK -clk => entry[1][21].CLK -clk => entry[1][22].CLK -clk => entry[1][23].CLK -clk => entry[1][24].CLK -clk => entry[1][25].CLK -clk => entry[1][26].CLK -clk => entry[1][27].CLK -clk => entry[1][28].CLK -clk => entry[1][29].CLK -clk => entry[1][30].CLK -clk => entry[1][31].CLK -clk => entry[1][32].CLK -clk => entry[1][33].CLK -clk => entry[1][34].CLK -clk => entry[1][35].CLK -clk => entry[1][36].CLK -clk => entry[1][37].CLK -clk => entry[1][38].CLK -clk => entry[1][39].CLK -clk => entry[1][40].CLK -rst => status_full.ACLR -rst => status_empty.PRESET -rst => ptr_rd[0].ACLR -rst => data_o[0]~reg0.ACLR -rst => data_o[1]~reg0.ACLR -rst => data_o[2]~reg0.ACLR -rst => data_o[3]~reg0.ACLR -rst => data_o[4]~reg0.ACLR -rst => data_o[5]~reg0.ACLR -rst => data_o[6]~reg0.ACLR -rst => data_o[7]~reg0.ACLR -rst => data_o[8]~reg0.ACLR -rst => data_o[9]~reg0.ACLR -rst => data_o[10]~reg0.ACLR -rst => data_o[11]~reg0.ACLR -rst => data_o[12]~reg0.ACLR -rst => data_o[13]~reg0.ACLR -rst => data_o[14]~reg0.ACLR -rst => data_o[15]~reg0.ACLR -rst => data_o[16]~reg0.ACLR -rst => data_o[17]~reg0.ACLR -rst => data_o[18]~reg0.ACLR -rst => data_o[19]~reg0.ACLR -rst => data_o[20]~reg0.ACLR -rst => data_o[21]~reg0.ACLR -rst => data_o[22]~reg0.ACLR -rst => data_o[23]~reg0.ACLR -rst => data_o[24]~reg0.ACLR -rst => data_o[25]~reg0.ACLR -rst => data_o[26]~reg0.ACLR -rst => data_o[27]~reg0.ACLR -rst => data_o[28]~reg0.ACLR -rst => data_o[29]~reg0.ACLR -rst => data_o[30]~reg0.ACLR -rst => data_o[31]~reg0.ACLR -rst => data_o[32]~reg0.ACLR -rst => data_o[33]~reg0.ACLR -rst => data_o[34]~reg0.ACLR -rst => data_o[35]~reg0.ACLR -rst => data_o[36]~reg0.ACLR -rst => data_o[37]~reg0.ACLR -rst => data_o[38]~reg0.ACLR -rst => data_o[39]~reg0.ACLR -rst => data_o[40]~reg0.ACLR -rst => ptr_wr[0].ACLR -rst => entry[0][0].ACLR -rst => entry[0][1].ACLR -rst => entry[0][2].ACLR -rst => entry[0][3].ACLR -rst => entry[0][4].ACLR -rst => entry[0][5].ACLR -rst => entry[0][6].ACLR -rst => entry[0][7].ACLR -rst => entry[0][8].ACLR -rst => entry[0][9].ACLR -rst => entry[0][10].ACLR -rst => entry[0][11].ACLR -rst => entry[0][12].ACLR -rst => entry[0][13].ACLR -rst => entry[0][14].ACLR -rst => entry[0][15].ACLR -rst => entry[0][16].ACLR -rst => entry[0][17].ACLR -rst => entry[0][18].ACLR -rst => entry[0][19].ACLR -rst => entry[0][20].ACLR -rst => entry[0][21].ACLR -rst => entry[0][22].ACLR -rst => entry[0][23].ACLR -rst => entry[0][24].ACLR -rst => entry[0][25].ACLR -rst => entry[0][26].ACLR -rst => entry[0][27].ACLR -rst => entry[0][28].ACLR -rst => entry[0][29].ACLR -rst => entry[0][30].ACLR -rst => entry[0][31].ACLR -rst => entry[0][32].ACLR -rst => entry[0][33].ACLR -rst => entry[0][34].ACLR -rst => entry[0][35].ACLR -rst => entry[0][36].ACLR -rst => entry[0][37].ACLR -rst => entry[0][38].ACLR -rst => entry[0][39].ACLR -rst => entry[0][40].ACLR -rst => entry[1][0].ACLR -rst => entry[1][1].ACLR -rst => entry[1][2].ACLR -rst => entry[1][3].ACLR -rst => entry[1][4].ACLR -rst => entry[1][5].ACLR -rst => entry[1][6].ACLR -rst => entry[1][7].ACLR -rst => entry[1][8].ACLR -rst => entry[1][9].ACLR -rst => entry[1][10].ACLR -rst => entry[1][11].ACLR -rst => entry[1][12].ACLR -rst => entry[1][13].ACLR -rst => entry[1][14].ACLR -rst => entry[1][15].ACLR -rst => entry[1][16].ACLR -rst => entry[1][17].ACLR -rst => entry[1][18].ACLR -rst => entry[1][19].ACLR -rst => entry[1][20].ACLR -rst => entry[1][21].ACLR -rst => entry[1][22].ACLR -rst => entry[1][23].ACLR -rst => entry[1][24].ACLR -rst => entry[1][25].ACLR -rst => entry[1][26].ACLR -rst => entry[1][27].ACLR -rst => entry[1][28].ACLR -rst => entry[1][29].ACLR -rst => entry[1][30].ACLR -rst => entry[1][31].ACLR -rst => entry[1][32].ACLR -rst => entry[1][33].ACLR -rst => entry[1][34].ACLR -rst => entry[1][35].ACLR -rst => entry[1][36].ACLR -rst => entry[1][37].ACLR -rst => entry[1][38].ACLR -rst => entry[1][39].ACLR -rst => entry[1][40].ACLR -wr_i => fifo_depth_increase.IN0 -wr_i => fifo_depth_decrease.IN0 -wr_i => entry[1][40].ENA -wr_i => entry[1][39].ENA -wr_i => entry[1][38].ENA -wr_i => entry[1][37].ENA -wr_i => entry[1][36].ENA -wr_i => entry[1][35].ENA -wr_i => entry[1][34].ENA -wr_i => entry[1][33].ENA -wr_i => entry[1][32].ENA -wr_i => entry[1][31].ENA -wr_i => entry[1][30].ENA -wr_i => entry[1][29].ENA -wr_i => entry[1][28].ENA -wr_i => entry[1][27].ENA -wr_i => entry[1][26].ENA -wr_i => entry[1][25].ENA -wr_i => entry[1][24].ENA -wr_i => entry[1][23].ENA -wr_i => entry[1][22].ENA -wr_i => entry[1][21].ENA -wr_i => entry[1][20].ENA -wr_i => entry[1][19].ENA -wr_i => entry[1][18].ENA -wr_i => entry[1][17].ENA -wr_i => entry[1][16].ENA -wr_i => entry[1][15].ENA -wr_i => entry[1][14].ENA -wr_i => entry[1][13].ENA -wr_i => entry[1][12].ENA -wr_i => entry[1][11].ENA -wr_i => entry[1][10].ENA -wr_i => entry[1][9].ENA -wr_i => entry[1][8].ENA -wr_i => entry[1][7].ENA -wr_i => entry[1][6].ENA -wr_i => entry[1][5].ENA -wr_i => entry[1][4].ENA -wr_i => entry[1][3].ENA -wr_i => entry[1][2].ENA -wr_i => entry[1][1].ENA -wr_i => entry[1][0].ENA -wr_i => entry[0][40].ENA -wr_i => entry[0][39].ENA -wr_i => entry[0][38].ENA -wr_i => entry[0][37].ENA -wr_i => entry[0][36].ENA -wr_i => entry[0][35].ENA -wr_i => entry[0][34].ENA -wr_i => entry[0][33].ENA -wr_i => entry[0][32].ENA -wr_i => entry[0][31].ENA -wr_i => entry[0][30].ENA -wr_i => entry[0][29].ENA -wr_i => entry[0][28].ENA -wr_i => entry[0][27].ENA -wr_i => entry[0][26].ENA -wr_i => entry[0][25].ENA -wr_i => entry[0][24].ENA -wr_i => entry[0][23].ENA -wr_i => entry[0][22].ENA -wr_i => entry[0][21].ENA -wr_i => entry[0][20].ENA -wr_i => entry[0][19].ENA -wr_i => entry[0][18].ENA -wr_i => entry[0][17].ENA -wr_i => entry[0][16].ENA -wr_i => entry[0][15].ENA -wr_i => entry[0][14].ENA -wr_i => entry[0][13].ENA -wr_i => entry[0][12].ENA -wr_i => entry[0][11].ENA -wr_i => entry[0][10].ENA -wr_i => entry[0][9].ENA -wr_i => entry[0][8].ENA -wr_i => entry[0][7].ENA -wr_i => entry[0][6].ENA -wr_i => entry[0][5].ENA -wr_i => entry[0][4].ENA -wr_i => entry[0][3].ENA -wr_i => entry[0][2].ENA -wr_i => entry[0][1].ENA -wr_i => entry[0][0].ENA -wr_i => ptr_wr[0].ENA -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => fifo_depth_decrease.IN1 -rd_i => fifo_depth_increase.IN1 -rd_i => ptr_rd[0].ENA -data_i[0] => entry.DATAB -data_i[0] => entry.DATAB -data_i[0] => data_o.DATAB -data_i[1] => entry.DATAB -data_i[1] => entry.DATAB -data_i[1] => data_o.DATAB -data_i[2] => entry.DATAB -data_i[2] => entry.DATAB -data_i[2] => data_o.DATAB -data_i[3] => entry.DATAB -data_i[3] => entry.DATAB -data_i[3] => data_o.DATAB -data_i[4] => entry.DATAB -data_i[4] => entry.DATAB -data_i[4] => data_o.DATAB -data_i[5] => entry.DATAB -data_i[5] => entry.DATAB -data_i[5] => data_o.DATAB -data_i[6] => entry.DATAB -data_i[6] => entry.DATAB -data_i[6] => data_o.DATAB -data_i[7] => entry.DATAB -data_i[7] => entry.DATAB -data_i[7] => data_o.DATAB -data_i[8] => entry.DATAB -data_i[8] => entry.DATAB -data_i[8] => data_o.DATAB -data_i[9] => entry.DATAB -data_i[9] => entry.DATAB -data_i[9] => data_o.DATAB -data_i[10] => entry.DATAB -data_i[10] => entry.DATAB -data_i[10] => data_o.DATAB -data_i[11] => entry.DATAB -data_i[11] => entry.DATAB -data_i[11] => data_o.DATAB -data_i[12] => entry.DATAB -data_i[12] => entry.DATAB -data_i[12] => data_o.DATAB -data_i[13] => entry.DATAB -data_i[13] => entry.DATAB -data_i[13] => data_o.DATAB -data_i[14] => entry.DATAB -data_i[14] => entry.DATAB -data_i[14] => data_o.DATAB -data_i[15] => entry.DATAB -data_i[15] => entry.DATAB -data_i[15] => data_o.DATAB -data_i[16] => entry.DATAB -data_i[16] => entry.DATAB -data_i[16] => data_o.DATAB -data_i[17] => entry.DATAB -data_i[17] => entry.DATAB -data_i[17] => data_o.DATAB -data_i[18] => entry.DATAB -data_i[18] => entry.DATAB -data_i[18] => data_o.DATAB -data_i[19] => entry.DATAB -data_i[19] => entry.DATAB -data_i[19] => data_o.DATAB -data_i[20] => entry.DATAB -data_i[20] => entry.DATAB -data_i[20] => data_o.DATAB -data_i[21] => entry.DATAB -data_i[21] => entry.DATAB -data_i[21] => data_o.DATAB -data_i[22] => entry.DATAB -data_i[22] => entry.DATAB -data_i[22] => data_o.DATAB -data_i[23] => entry.DATAB -data_i[23] => entry.DATAB -data_i[23] => data_o.DATAB -data_i[24] => entry.DATAB -data_i[24] => entry.DATAB -data_i[24] => data_o.DATAB -data_i[25] => entry.DATAB -data_i[25] => entry.DATAB -data_i[25] => data_o.DATAB -data_i[26] => entry.DATAB -data_i[26] => entry.DATAB -data_i[26] => data_o.DATAB -data_i[27] => entry.DATAB -data_i[27] => entry.DATAB -data_i[27] => data_o.DATAB -data_i[28] => entry.DATAB -data_i[28] => entry.DATAB -data_i[28] => data_o.DATAB -data_i[29] => entry.DATAB -data_i[29] => entry.DATAB -data_i[29] => data_o.DATAB -data_i[30] => entry.DATAB -data_i[30] => entry.DATAB -data_i[30] => data_o.DATAB -data_i[31] => entry.DATAB -data_i[31] => entry.DATAB -data_i[31] => data_o.DATAB -data_i[32] => entry.DATAB -data_i[32] => entry.DATAB -data_i[32] => data_o.DATAB -data_i[33] => entry.DATAB -data_i[33] => entry.DATAB -data_i[33] => data_o.DATAB -data_i[34] => entry.DATAB -data_i[34] => entry.DATAB -data_i[34] => data_o.DATAB -data_i[35] => entry.DATAB -data_i[35] => entry.DATAB -data_i[35] => data_o.DATAB -data_i[36] => entry.DATAB -data_i[36] => entry.DATAB -data_i[36] => data_o.DATAB -data_i[37] => entry.DATAB -data_i[37] => entry.DATAB -data_i[37] => data_o.DATAB -data_i[38] => entry.DATAB -data_i[38] => entry.DATAB -data_i[38] => data_o.DATAB -data_i[39] => entry.DATAB -data_i[39] => entry.DATAB -data_i[39] => data_o.DATAB -data_i[40] => entry.DATAB -data_i[40] => entry.DATAB -data_i[40] => data_o.DATAB -data_o[0] <= data_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[1] <= data_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[2] <= data_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[3] <= data_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[4] <= data_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[5] <= data_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[6] <= data_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[7] <= data_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[8] <= data_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[9] <= data_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[10] <= data_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[11] <= data_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[12] <= data_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[13] <= data_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[14] <= data_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[15] <= data_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[16] <= data_o[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[17] <= data_o[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[18] <= data_o[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[19] <= data_o[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[20] <= data_o[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[21] <= data_o[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[22] <= data_o[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[23] <= data_o[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[24] <= data_o[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[25] <= data_o[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[26] <= data_o[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[27] <= data_o[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[28] <= data_o[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[29] <= data_o[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[30] <= data_o[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[31] <= data_o[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[32] <= data_o[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[33] <= data_o[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[34] <= data_o[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[35] <= data_o[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[36] <= data_o[36]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[37] <= data_o[37]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[38] <= data_o[38]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[39] <= data_o[39]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[40] <= data_o[40]~reg0.DB_MAX_OUTPUT_PORT_TYPE -status_empty_o <= status_empty.DB_MAX_OUTPUT_PORT_TYPE -status_full_o <= status_full.DB_MAX_OUTPUT_PORT_TYPE - - -|mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1 -clk => status_full.CLK -clk => status_empty.CLK -clk => ptr_rd[0].CLK -clk => data_o[0]~reg0.CLK -clk => data_o[1]~reg0.CLK -clk => data_o[2]~reg0.CLK -clk => data_o[3]~reg0.CLK -clk => data_o[4]~reg0.CLK -clk => data_o[5]~reg0.CLK -clk => data_o[6]~reg0.CLK -clk => data_o[7]~reg0.CLK -clk => data_o[8]~reg0.CLK -clk => data_o[9]~reg0.CLK -clk => data_o[10]~reg0.CLK -clk => data_o[11]~reg0.CLK -clk => data_o[12]~reg0.CLK -clk => data_o[13]~reg0.CLK -clk => data_o[14]~reg0.CLK -clk => data_o[15]~reg0.CLK -clk => data_o[16]~reg0.CLK -clk => data_o[17]~reg0.CLK -clk => data_o[18]~reg0.CLK -clk => data_o[19]~reg0.CLK -clk => data_o[20]~reg0.CLK -clk => data_o[21]~reg0.CLK -clk => data_o[22]~reg0.CLK -clk => data_o[23]~reg0.CLK -clk => data_o[24]~reg0.CLK -clk => data_o[25]~reg0.CLK -clk => data_o[26]~reg0.CLK -clk => data_o[27]~reg0.CLK -clk => data_o[28]~reg0.CLK -clk => data_o[29]~reg0.CLK -clk => data_o[30]~reg0.CLK -clk => data_o[31]~reg0.CLK -clk => data_o[32]~reg0.CLK -clk => data_o[33]~reg0.CLK -clk => data_o[34]~reg0.CLK -clk => data_o[35]~reg0.CLK -clk => data_o[36]~reg0.CLK -clk => data_o[37]~reg0.CLK -clk => data_o[38]~reg0.CLK -clk => data_o[39]~reg0.CLK -clk => data_o[40]~reg0.CLK -clk => ptr_wr[0].CLK -clk => entry[0][0].CLK -clk => entry[0][1].CLK -clk => entry[0][2].CLK -clk => entry[0][3].CLK -clk => entry[0][4].CLK -clk => entry[0][5].CLK -clk => entry[0][6].CLK -clk => entry[0][7].CLK -clk => entry[0][8].CLK -clk => entry[0][9].CLK -clk => entry[0][10].CLK -clk => entry[0][11].CLK -clk => entry[0][12].CLK -clk => entry[0][13].CLK -clk => entry[0][14].CLK -clk => entry[0][15].CLK -clk => entry[0][16].CLK -clk => entry[0][17].CLK -clk => entry[0][18].CLK -clk => entry[0][19].CLK -clk => entry[0][20].CLK -clk => entry[0][21].CLK -clk => entry[0][22].CLK -clk => entry[0][23].CLK -clk => entry[0][24].CLK -clk => entry[0][25].CLK -clk => entry[0][26].CLK -clk => entry[0][27].CLK -clk => entry[0][28].CLK -clk => entry[0][29].CLK -clk => entry[0][30].CLK -clk => entry[0][31].CLK -clk => entry[0][32].CLK -clk => entry[0][33].CLK -clk => entry[0][34].CLK -clk => entry[0][35].CLK -clk => entry[0][36].CLK -clk => entry[0][37].CLK -clk => entry[0][38].CLK -clk => entry[0][39].CLK -clk => entry[0][40].CLK -clk => entry[1][0].CLK -clk => entry[1][1].CLK -clk => entry[1][2].CLK -clk => entry[1][3].CLK -clk => entry[1][4].CLK -clk => entry[1][5].CLK -clk => entry[1][6].CLK -clk => entry[1][7].CLK -clk => entry[1][8].CLK -clk => entry[1][9].CLK -clk => entry[1][10].CLK -clk => entry[1][11].CLK -clk => entry[1][12].CLK -clk => entry[1][13].CLK -clk => entry[1][14].CLK -clk => entry[1][15].CLK -clk => entry[1][16].CLK -clk => entry[1][17].CLK -clk => entry[1][18].CLK -clk => entry[1][19].CLK -clk => entry[1][20].CLK -clk => entry[1][21].CLK -clk => entry[1][22].CLK -clk => entry[1][23].CLK -clk => entry[1][24].CLK -clk => entry[1][25].CLK -clk => entry[1][26].CLK -clk => entry[1][27].CLK -clk => entry[1][28].CLK -clk => entry[1][29].CLK -clk => entry[1][30].CLK -clk => entry[1][31].CLK -clk => entry[1][32].CLK -clk => entry[1][33].CLK -clk => entry[1][34].CLK -clk => entry[1][35].CLK -clk => entry[1][36].CLK -clk => entry[1][37].CLK -clk => entry[1][38].CLK -clk => entry[1][39].CLK -clk => entry[1][40].CLK -rst => status_full.ACLR -rst => status_empty.PRESET -rst => ptr_rd[0].ACLR -rst => data_o[0]~reg0.ACLR -rst => data_o[1]~reg0.ACLR -rst => data_o[2]~reg0.ACLR -rst => data_o[3]~reg0.ACLR -rst => data_o[4]~reg0.ACLR -rst => data_o[5]~reg0.ACLR -rst => data_o[6]~reg0.ACLR -rst => data_o[7]~reg0.ACLR -rst => data_o[8]~reg0.ACLR -rst => data_o[9]~reg0.ACLR -rst => data_o[10]~reg0.ACLR -rst => data_o[11]~reg0.ACLR -rst => data_o[12]~reg0.ACLR -rst => data_o[13]~reg0.ACLR -rst => data_o[14]~reg0.ACLR -rst => data_o[15]~reg0.ACLR -rst => data_o[16]~reg0.ACLR -rst => data_o[17]~reg0.ACLR -rst => data_o[18]~reg0.ACLR -rst => data_o[19]~reg0.ACLR -rst => data_o[20]~reg0.ACLR -rst => data_o[21]~reg0.ACLR -rst => data_o[22]~reg0.ACLR -rst => data_o[23]~reg0.ACLR -rst => data_o[24]~reg0.ACLR -rst => data_o[25]~reg0.ACLR -rst => data_o[26]~reg0.ACLR -rst => data_o[27]~reg0.ACLR -rst => data_o[28]~reg0.ACLR -rst => data_o[29]~reg0.ACLR -rst => data_o[30]~reg0.ACLR -rst => data_o[31]~reg0.ACLR -rst => data_o[32]~reg0.ACLR -rst => data_o[33]~reg0.ACLR -rst => data_o[34]~reg0.ACLR -rst => data_o[35]~reg0.ACLR -rst => data_o[36]~reg0.ACLR -rst => data_o[37]~reg0.ACLR -rst => data_o[38]~reg0.ACLR -rst => data_o[39]~reg0.ACLR -rst => data_o[40]~reg0.ACLR -rst => ptr_wr[0].ACLR -rst => entry[0][0].ACLR -rst => entry[0][1].ACLR -rst => entry[0][2].ACLR -rst => entry[0][3].ACLR -rst => entry[0][4].ACLR -rst => entry[0][5].ACLR -rst => entry[0][6].ACLR -rst => entry[0][7].ACLR -rst => entry[0][8].ACLR -rst => entry[0][9].ACLR -rst => entry[0][10].ACLR -rst => entry[0][11].ACLR -rst => entry[0][12].ACLR -rst => entry[0][13].ACLR -rst => entry[0][14].ACLR -rst => entry[0][15].ACLR -rst => entry[0][16].ACLR -rst => entry[0][17].ACLR -rst => entry[0][18].ACLR -rst => entry[0][19].ACLR -rst => entry[0][20].ACLR -rst => entry[0][21].ACLR -rst => entry[0][22].ACLR -rst => entry[0][23].ACLR -rst => entry[0][24].ACLR -rst => entry[0][25].ACLR -rst => entry[0][26].ACLR -rst => entry[0][27].ACLR -rst => entry[0][28].ACLR -rst => entry[0][29].ACLR -rst => entry[0][30].ACLR -rst => entry[0][31].ACLR -rst => entry[0][32].ACLR -rst => entry[0][33].ACLR -rst => entry[0][34].ACLR -rst => entry[0][35].ACLR -rst => entry[0][36].ACLR -rst => entry[0][37].ACLR -rst => entry[0][38].ACLR -rst => entry[0][39].ACLR -rst => entry[0][40].ACLR -rst => entry[1][0].ACLR -rst => entry[1][1].ACLR -rst => entry[1][2].ACLR -rst => entry[1][3].ACLR -rst => entry[1][4].ACLR -rst => entry[1][5].ACLR -rst => entry[1][6].ACLR -rst => entry[1][7].ACLR -rst => entry[1][8].ACLR -rst => entry[1][9].ACLR -rst => entry[1][10].ACLR -rst => entry[1][11].ACLR -rst => entry[1][12].ACLR -rst => entry[1][13].ACLR -rst => entry[1][14].ACLR -rst => entry[1][15].ACLR -rst => entry[1][16].ACLR -rst => entry[1][17].ACLR -rst => entry[1][18].ACLR -rst => entry[1][19].ACLR -rst => entry[1][20].ACLR -rst => entry[1][21].ACLR -rst => entry[1][22].ACLR -rst => entry[1][23].ACLR -rst => entry[1][24].ACLR -rst => entry[1][25].ACLR -rst => entry[1][26].ACLR -rst => entry[1][27].ACLR -rst => entry[1][28].ACLR -rst => entry[1][29].ACLR -rst => entry[1][30].ACLR -rst => entry[1][31].ACLR -rst => entry[1][32].ACLR -rst => entry[1][33].ACLR -rst => entry[1][34].ACLR -rst => entry[1][35].ACLR -rst => entry[1][36].ACLR -rst => entry[1][37].ACLR -rst => entry[1][38].ACLR -rst => entry[1][39].ACLR -rst => entry[1][40].ACLR -wr_i => fifo_depth_increase.IN0 -wr_i => fifo_depth_decrease.IN0 -wr_i => entry[1][40].ENA -wr_i => entry[1][39].ENA -wr_i => entry[1][38].ENA -wr_i => entry[1][37].ENA -wr_i => entry[1][36].ENA -wr_i => entry[1][35].ENA -wr_i => entry[1][34].ENA -wr_i => entry[1][33].ENA -wr_i => entry[1][32].ENA -wr_i => entry[1][31].ENA -wr_i => entry[1][30].ENA -wr_i => entry[1][29].ENA -wr_i => entry[1][28].ENA -wr_i => entry[1][27].ENA -wr_i => entry[1][26].ENA -wr_i => entry[1][25].ENA -wr_i => entry[1][24].ENA -wr_i => entry[1][23].ENA -wr_i => entry[1][22].ENA -wr_i => entry[1][21].ENA -wr_i => entry[1][20].ENA -wr_i => entry[1][19].ENA -wr_i => entry[1][18].ENA -wr_i => entry[1][17].ENA -wr_i => entry[1][16].ENA -wr_i => entry[1][15].ENA -wr_i => entry[1][14].ENA -wr_i => entry[1][13].ENA -wr_i => entry[1][12].ENA -wr_i => entry[1][11].ENA -wr_i => entry[1][10].ENA -wr_i => entry[1][9].ENA -wr_i => entry[1][8].ENA -wr_i => entry[1][7].ENA -wr_i => entry[1][6].ENA -wr_i => entry[1][5].ENA -wr_i => entry[1][4].ENA -wr_i => entry[1][3].ENA -wr_i => entry[1][2].ENA -wr_i => entry[1][1].ENA -wr_i => entry[1][0].ENA -wr_i => entry[0][40].ENA -wr_i => entry[0][39].ENA -wr_i => entry[0][38].ENA -wr_i => entry[0][37].ENA -wr_i => entry[0][36].ENA -wr_i => entry[0][35].ENA -wr_i => entry[0][34].ENA -wr_i => entry[0][33].ENA -wr_i => entry[0][32].ENA -wr_i => entry[0][31].ENA -wr_i => entry[0][30].ENA -wr_i => entry[0][29].ENA -wr_i => entry[0][28].ENA -wr_i => entry[0][27].ENA -wr_i => entry[0][26].ENA -wr_i => entry[0][25].ENA -wr_i => entry[0][24].ENA -wr_i => entry[0][23].ENA -wr_i => entry[0][22].ENA -wr_i => entry[0][21].ENA -wr_i => entry[0][20].ENA -wr_i => entry[0][19].ENA -wr_i => entry[0][18].ENA -wr_i => entry[0][17].ENA -wr_i => entry[0][16].ENA -wr_i => entry[0][15].ENA -wr_i => entry[0][14].ENA -wr_i => entry[0][13].ENA -wr_i => entry[0][12].ENA -wr_i => entry[0][11].ENA -wr_i => entry[0][10].ENA -wr_i => entry[0][9].ENA -wr_i => entry[0][8].ENA -wr_i => entry[0][7].ENA -wr_i => entry[0][6].ENA -wr_i => entry[0][5].ENA -wr_i => entry[0][4].ENA -wr_i => entry[0][3].ENA -wr_i => entry[0][2].ENA -wr_i => entry[0][1].ENA -wr_i => entry[0][0].ENA -wr_i => ptr_wr[0].ENA -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => fifo_depth_decrease.IN1 -rd_i => fifo_depth_increase.IN1 -rd_i => ptr_rd[0].ENA -data_i[0] => entry.DATAB -data_i[0] => entry.DATAB -data_i[0] => data_o.DATAB -data_i[1] => entry.DATAB -data_i[1] => entry.DATAB -data_i[1] => data_o.DATAB -data_i[2] => entry.DATAB -data_i[2] => entry.DATAB -data_i[2] => data_o.DATAB -data_i[3] => entry.DATAB -data_i[3] => entry.DATAB -data_i[3] => data_o.DATAB -data_i[4] => entry.DATAB -data_i[4] => entry.DATAB -data_i[4] => data_o.DATAB -data_i[5] => entry.DATAB -data_i[5] => entry.DATAB -data_i[5] => data_o.DATAB -data_i[6] => entry.DATAB -data_i[6] => entry.DATAB -data_i[6] => data_o.DATAB -data_i[7] => entry.DATAB -data_i[7] => entry.DATAB -data_i[7] => data_o.DATAB -data_i[8] => entry.DATAB -data_i[8] => entry.DATAB -data_i[8] => data_o.DATAB -data_i[9] => entry.DATAB -data_i[9] => entry.DATAB -data_i[9] => data_o.DATAB -data_i[10] => entry.DATAB -data_i[10] => entry.DATAB -data_i[10] => data_o.DATAB -data_i[11] => entry.DATAB -data_i[11] => entry.DATAB -data_i[11] => data_o.DATAB -data_i[12] => entry.DATAB -data_i[12] => entry.DATAB -data_i[12] => data_o.DATAB -data_i[13] => entry.DATAB -data_i[13] => entry.DATAB -data_i[13] => data_o.DATAB -data_i[14] => entry.DATAB -data_i[14] => entry.DATAB -data_i[14] => data_o.DATAB -data_i[15] => entry.DATAB -data_i[15] => entry.DATAB -data_i[15] => data_o.DATAB -data_i[16] => entry.DATAB -data_i[16] => entry.DATAB -data_i[16] => data_o.DATAB -data_i[17] => entry.DATAB -data_i[17] => entry.DATAB -data_i[17] => data_o.DATAB -data_i[18] => entry.DATAB -data_i[18] => entry.DATAB -data_i[18] => data_o.DATAB -data_i[19] => entry.DATAB -data_i[19] => entry.DATAB -data_i[19] => data_o.DATAB -data_i[20] => entry.DATAB -data_i[20] => entry.DATAB -data_i[20] => data_o.DATAB -data_i[21] => entry.DATAB -data_i[21] => entry.DATAB -data_i[21] => data_o.DATAB -data_i[22] => entry.DATAB -data_i[22] => entry.DATAB -data_i[22] => data_o.DATAB -data_i[23] => entry.DATAB -data_i[23] => entry.DATAB -data_i[23] => data_o.DATAB -data_i[24] => entry.DATAB -data_i[24] => entry.DATAB -data_i[24] => data_o.DATAB -data_i[25] => entry.DATAB -data_i[25] => entry.DATAB -data_i[25] => data_o.DATAB -data_i[26] => entry.DATAB -data_i[26] => entry.DATAB -data_i[26] => data_o.DATAB -data_i[27] => entry.DATAB -data_i[27] => entry.DATAB -data_i[27] => data_o.DATAB -data_i[28] => entry.DATAB -data_i[28] => entry.DATAB -data_i[28] => data_o.DATAB -data_i[29] => entry.DATAB -data_i[29] => entry.DATAB -data_i[29] => data_o.DATAB -data_i[30] => entry.DATAB -data_i[30] => entry.DATAB -data_i[30] => data_o.DATAB -data_i[31] => entry.DATAB -data_i[31] => entry.DATAB -data_i[31] => data_o.DATAB -data_i[32] => entry.DATAB -data_i[32] => entry.DATAB -data_i[32] => data_o.DATAB -data_i[33] => entry.DATAB -data_i[33] => entry.DATAB -data_i[33] => data_o.DATAB -data_i[34] => entry.DATAB -data_i[34] => entry.DATAB -data_i[34] => data_o.DATAB -data_i[35] => entry.DATAB -data_i[35] => entry.DATAB -data_i[35] => data_o.DATAB -data_i[36] => entry.DATAB -data_i[36] => entry.DATAB -data_i[36] => data_o.DATAB -data_i[37] => entry.DATAB -data_i[37] => entry.DATAB -data_i[37] => data_o.DATAB -data_i[38] => entry.DATAB -data_i[38] => entry.DATAB -data_i[38] => data_o.DATAB -data_i[39] => entry.DATAB -data_i[39] => entry.DATAB -data_i[39] => data_o.DATAB -data_i[40] => entry.DATAB -data_i[40] => entry.DATAB -data_i[40] => data_o.DATAB -data_o[0] <= data_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[1] <= data_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[2] <= data_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[3] <= data_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[4] <= data_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[5] <= data_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[6] <= data_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[7] <= data_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[8] <= data_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[9] <= data_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[10] <= data_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[11] <= data_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[12] <= data_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[13] <= data_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[14] <= data_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[15] <= data_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[16] <= data_o[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[17] <= data_o[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[18] <= data_o[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[19] <= data_o[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[20] <= data_o[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[21] <= data_o[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[22] <= data_o[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[23] <= data_o[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[24] <= data_o[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[25] <= data_o[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[26] <= data_o[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[27] <= data_o[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[28] <= data_o[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[29] <= data_o[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[30] <= data_o[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[31] <= data_o[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[32] <= data_o[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[33] <= data_o[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[34] <= data_o[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[35] <= data_o[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[36] <= data_o[36]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[37] <= data_o[37]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[38] <= data_o[38]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[39] <= data_o[39]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[40] <= data_o[40]~reg0.DB_MAX_OUTPUT_PORT_TYPE -status_empty_o <= status_empty.DB_MAX_OUTPUT_PORT_TYPE -status_full_o <= status_full.DB_MAX_OUTPUT_PORT_TYPE - - -|mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0 -clk => status_full.CLK -clk => status_empty.CLK -clk => ptr_rd[0].CLK -clk => data_o[0]~reg0.CLK -clk => data_o[1]~reg0.CLK -clk => data_o[2]~reg0.CLK -clk => data_o[3]~reg0.CLK -clk => data_o[4]~reg0.CLK -clk => data_o[5]~reg0.CLK -clk => data_o[6]~reg0.CLK -clk => data_o[7]~reg0.CLK -clk => data_o[8]~reg0.CLK -clk => data_o[9]~reg0.CLK -clk => data_o[10]~reg0.CLK -clk => data_o[11]~reg0.CLK -clk => data_o[12]~reg0.CLK -clk => data_o[13]~reg0.CLK -clk => data_o[14]~reg0.CLK -clk => data_o[15]~reg0.CLK -clk => data_o[16]~reg0.CLK -clk => data_o[17]~reg0.CLK -clk => data_o[18]~reg0.CLK -clk => data_o[19]~reg0.CLK -clk => data_o[20]~reg0.CLK -clk => data_o[21]~reg0.CLK -clk => data_o[22]~reg0.CLK -clk => data_o[23]~reg0.CLK -clk => data_o[24]~reg0.CLK -clk => data_o[25]~reg0.CLK -clk => data_o[26]~reg0.CLK -clk => data_o[27]~reg0.CLK -clk => data_o[28]~reg0.CLK -clk => data_o[29]~reg0.CLK -clk => data_o[30]~reg0.CLK -clk => data_o[31]~reg0.CLK -clk => data_o[32]~reg0.CLK -clk => data_o[33]~reg0.CLK -clk => data_o[34]~reg0.CLK -clk => data_o[35]~reg0.CLK -clk => data_o[36]~reg0.CLK -clk => data_o[37]~reg0.CLK -clk => data_o[38]~reg0.CLK -clk => data_o[39]~reg0.CLK -clk => data_o[40]~reg0.CLK -clk => ptr_wr[0].CLK -clk => entry[0][0].CLK -clk => entry[0][1].CLK -clk => entry[0][2].CLK -clk => entry[0][3].CLK -clk => entry[0][4].CLK -clk => entry[0][5].CLK -clk => entry[0][6].CLK -clk => entry[0][7].CLK -clk => entry[0][8].CLK -clk => entry[0][9].CLK -clk => entry[0][10].CLK -clk => entry[0][11].CLK -clk => entry[0][12].CLK -clk => entry[0][13].CLK -clk => entry[0][14].CLK -clk => entry[0][15].CLK -clk => entry[0][16].CLK -clk => entry[0][17].CLK -clk => entry[0][18].CLK -clk => entry[0][19].CLK -clk => entry[0][20].CLK -clk => entry[0][21].CLK -clk => entry[0][22].CLK -clk => entry[0][23].CLK -clk => entry[0][24].CLK -clk => entry[0][25].CLK -clk => entry[0][26].CLK -clk => entry[0][27].CLK -clk => entry[0][28].CLK -clk => entry[0][29].CLK -clk => entry[0][30].CLK -clk => entry[0][31].CLK -clk => entry[0][32].CLK -clk => entry[0][33].CLK -clk => entry[0][34].CLK -clk => entry[0][35].CLK -clk => entry[0][36].CLK -clk => entry[0][37].CLK -clk => entry[0][38].CLK -clk => entry[0][39].CLK -clk => entry[0][40].CLK -clk => entry[1][0].CLK -clk => entry[1][1].CLK -clk => entry[1][2].CLK -clk => entry[1][3].CLK -clk => entry[1][4].CLK -clk => entry[1][5].CLK -clk => entry[1][6].CLK -clk => entry[1][7].CLK -clk => entry[1][8].CLK -clk => entry[1][9].CLK -clk => entry[1][10].CLK -clk => entry[1][11].CLK -clk => entry[1][12].CLK -clk => entry[1][13].CLK -clk => entry[1][14].CLK -clk => entry[1][15].CLK -clk => entry[1][16].CLK -clk => entry[1][17].CLK -clk => entry[1][18].CLK -clk => entry[1][19].CLK -clk => entry[1][20].CLK -clk => entry[1][21].CLK -clk => entry[1][22].CLK -clk => entry[1][23].CLK -clk => entry[1][24].CLK -clk => entry[1][25].CLK -clk => entry[1][26].CLK -clk => entry[1][27].CLK -clk => entry[1][28].CLK -clk => entry[1][29].CLK -clk => entry[1][30].CLK -clk => entry[1][31].CLK -clk => entry[1][32].CLK -clk => entry[1][33].CLK -clk => entry[1][34].CLK -clk => entry[1][35].CLK -clk => entry[1][36].CLK -clk => entry[1][37].CLK -clk => entry[1][38].CLK -clk => entry[1][39].CLK -clk => entry[1][40].CLK -rst => status_full.ACLR -rst => status_empty.PRESET -rst => ptr_rd[0].ACLR -rst => data_o[0]~reg0.ACLR -rst => data_o[1]~reg0.ACLR -rst => data_o[2]~reg0.ACLR -rst => data_o[3]~reg0.ACLR -rst => data_o[4]~reg0.ACLR -rst => data_o[5]~reg0.ACLR -rst => data_o[6]~reg0.ACLR -rst => data_o[7]~reg0.ACLR -rst => data_o[8]~reg0.ACLR -rst => data_o[9]~reg0.ACLR -rst => data_o[10]~reg0.ACLR -rst => data_o[11]~reg0.ACLR -rst => data_o[12]~reg0.ACLR -rst => data_o[13]~reg0.ACLR -rst => data_o[14]~reg0.ACLR -rst => data_o[15]~reg0.ACLR -rst => data_o[16]~reg0.ACLR -rst => data_o[17]~reg0.ACLR -rst => data_o[18]~reg0.ACLR -rst => data_o[19]~reg0.ACLR -rst => data_o[20]~reg0.ACLR -rst => data_o[21]~reg0.ACLR -rst => data_o[22]~reg0.ACLR -rst => data_o[23]~reg0.ACLR -rst => data_o[24]~reg0.ACLR -rst => data_o[25]~reg0.ACLR -rst => data_o[26]~reg0.ACLR -rst => data_o[27]~reg0.ACLR -rst => data_o[28]~reg0.ACLR -rst => data_o[29]~reg0.ACLR -rst => data_o[30]~reg0.ACLR -rst => data_o[31]~reg0.ACLR -rst => data_o[32]~reg0.ACLR -rst => data_o[33]~reg0.ACLR -rst => data_o[34]~reg0.ACLR -rst => data_o[35]~reg0.ACLR -rst => data_o[36]~reg0.ACLR -rst => data_o[37]~reg0.ACLR -rst => data_o[38]~reg0.ACLR -rst => data_o[39]~reg0.ACLR -rst => data_o[40]~reg0.ACLR -rst => ptr_wr[0].ACLR -rst => entry[0][0].ACLR -rst => entry[0][1].ACLR -rst => entry[0][2].ACLR -rst => entry[0][3].ACLR -rst => entry[0][4].ACLR -rst => entry[0][5].ACLR -rst => entry[0][6].ACLR -rst => entry[0][7].ACLR -rst => entry[0][8].ACLR -rst => entry[0][9].ACLR -rst => entry[0][10].ACLR -rst => entry[0][11].ACLR -rst => entry[0][12].ACLR -rst => entry[0][13].ACLR -rst => entry[0][14].ACLR -rst => entry[0][15].ACLR -rst => entry[0][16].ACLR -rst => entry[0][17].ACLR -rst => entry[0][18].ACLR -rst => entry[0][19].ACLR -rst => entry[0][20].ACLR -rst => entry[0][21].ACLR -rst => entry[0][22].ACLR -rst => entry[0][23].ACLR -rst => entry[0][24].ACLR -rst => entry[0][25].ACLR -rst => entry[0][26].ACLR -rst => entry[0][27].ACLR -rst => entry[0][28].ACLR -rst => entry[0][29].ACLR -rst => entry[0][30].ACLR -rst => entry[0][31].ACLR -rst => entry[0][32].ACLR -rst => entry[0][33].ACLR -rst => entry[0][34].ACLR -rst => entry[0][35].ACLR -rst => entry[0][36].ACLR -rst => entry[0][37].ACLR -rst => entry[0][38].ACLR -rst => entry[0][39].ACLR -rst => entry[0][40].ACLR -rst => entry[1][0].ACLR -rst => entry[1][1].ACLR -rst => entry[1][2].ACLR -rst => entry[1][3].ACLR -rst => entry[1][4].ACLR -rst => entry[1][5].ACLR -rst => entry[1][6].ACLR -rst => entry[1][7].ACLR -rst => entry[1][8].ACLR -rst => entry[1][9].ACLR -rst => entry[1][10].ACLR -rst => entry[1][11].ACLR -rst => entry[1][12].ACLR -rst => entry[1][13].ACLR -rst => entry[1][14].ACLR -rst => entry[1][15].ACLR -rst => entry[1][16].ACLR -rst => entry[1][17].ACLR -rst => entry[1][18].ACLR -rst => entry[1][19].ACLR -rst => entry[1][20].ACLR -rst => entry[1][21].ACLR -rst => entry[1][22].ACLR -rst => entry[1][23].ACLR -rst => entry[1][24].ACLR -rst => entry[1][25].ACLR -rst => entry[1][26].ACLR -rst => entry[1][27].ACLR -rst => entry[1][28].ACLR -rst => entry[1][29].ACLR -rst => entry[1][30].ACLR -rst => entry[1][31].ACLR -rst => entry[1][32].ACLR -rst => entry[1][33].ACLR -rst => entry[1][34].ACLR -rst => entry[1][35].ACLR -rst => entry[1][36].ACLR -rst => entry[1][37].ACLR -rst => entry[1][38].ACLR -rst => entry[1][39].ACLR -rst => entry[1][40].ACLR -wr_i => fifo_depth_increase.IN0 -wr_i => fifo_depth_decrease.IN0 -wr_i => entry[1][40].ENA -wr_i => entry[1][39].ENA -wr_i => entry[1][38].ENA -wr_i => entry[1][37].ENA -wr_i => entry[1][36].ENA -wr_i => entry[1][35].ENA -wr_i => entry[1][34].ENA -wr_i => entry[1][33].ENA -wr_i => entry[1][32].ENA -wr_i => entry[1][31].ENA -wr_i => entry[1][30].ENA -wr_i => entry[1][29].ENA -wr_i => entry[1][28].ENA -wr_i => entry[1][27].ENA -wr_i => entry[1][26].ENA -wr_i => entry[1][25].ENA -wr_i => entry[1][24].ENA -wr_i => entry[1][23].ENA -wr_i => entry[1][22].ENA -wr_i => entry[1][21].ENA -wr_i => entry[1][20].ENA -wr_i => entry[1][19].ENA -wr_i => entry[1][18].ENA -wr_i => entry[1][17].ENA -wr_i => entry[1][16].ENA -wr_i => entry[1][15].ENA -wr_i => entry[1][14].ENA -wr_i => entry[1][13].ENA -wr_i => entry[1][12].ENA -wr_i => entry[1][11].ENA -wr_i => entry[1][10].ENA -wr_i => entry[1][9].ENA -wr_i => entry[1][8].ENA -wr_i => entry[1][7].ENA -wr_i => entry[1][6].ENA -wr_i => entry[1][5].ENA -wr_i => entry[1][4].ENA -wr_i => entry[1][3].ENA -wr_i => entry[1][2].ENA -wr_i => entry[1][1].ENA -wr_i => entry[1][0].ENA -wr_i => entry[0][40].ENA -wr_i => entry[0][39].ENA -wr_i => entry[0][38].ENA -wr_i => entry[0][37].ENA -wr_i => entry[0][36].ENA -wr_i => entry[0][35].ENA -wr_i => entry[0][34].ENA -wr_i => entry[0][33].ENA -wr_i => entry[0][32].ENA -wr_i => entry[0][31].ENA -wr_i => entry[0][30].ENA -wr_i => entry[0][29].ENA -wr_i => entry[0][28].ENA -wr_i => entry[0][27].ENA -wr_i => entry[0][26].ENA -wr_i => entry[0][25].ENA -wr_i => entry[0][24].ENA -wr_i => entry[0][23].ENA -wr_i => entry[0][22].ENA -wr_i => entry[0][21].ENA -wr_i => entry[0][20].ENA -wr_i => entry[0][19].ENA -wr_i => entry[0][18].ENA -wr_i => entry[0][17].ENA -wr_i => entry[0][16].ENA -wr_i => entry[0][15].ENA -wr_i => entry[0][14].ENA -wr_i => entry[0][13].ENA -wr_i => entry[0][12].ENA -wr_i => entry[0][11].ENA -wr_i => entry[0][10].ENA -wr_i => entry[0][9].ENA -wr_i => entry[0][8].ENA -wr_i => entry[0][7].ENA -wr_i => entry[0][6].ENA -wr_i => entry[0][5].ENA -wr_i => entry[0][4].ENA -wr_i => entry[0][3].ENA -wr_i => entry[0][2].ENA -wr_i => entry[0][1].ENA -wr_i => entry[0][0].ENA -wr_i => ptr_wr[0].ENA -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => data_o.OUTPUTSELECT -rd_i => fifo_depth_decrease.IN1 -rd_i => fifo_depth_increase.IN1 -rd_i => ptr_rd[0].ENA -data_i[0] => entry.DATAB -data_i[0] => entry.DATAB -data_i[0] => data_o.DATAB -data_i[1] => entry.DATAB -data_i[1] => entry.DATAB -data_i[1] => data_o.DATAB -data_i[2] => entry.DATAB -data_i[2] => entry.DATAB -data_i[2] => data_o.DATAB -data_i[3] => entry.DATAB -data_i[3] => entry.DATAB -data_i[3] => data_o.DATAB -data_i[4] => entry.DATAB -data_i[4] => entry.DATAB -data_i[4] => data_o.DATAB -data_i[5] => entry.DATAB -data_i[5] => entry.DATAB -data_i[5] => data_o.DATAB -data_i[6] => entry.DATAB -data_i[6] => entry.DATAB -data_i[6] => data_o.DATAB -data_i[7] => entry.DATAB -data_i[7] => entry.DATAB -data_i[7] => data_o.DATAB -data_i[8] => entry.DATAB -data_i[8] => entry.DATAB -data_i[8] => data_o.DATAB -data_i[9] => entry.DATAB -data_i[9] => entry.DATAB -data_i[9] => data_o.DATAB -data_i[10] => entry.DATAB -data_i[10] => entry.DATAB -data_i[10] => data_o.DATAB -data_i[11] => entry.DATAB -data_i[11] => entry.DATAB -data_i[11] => data_o.DATAB -data_i[12] => entry.DATAB -data_i[12] => entry.DATAB -data_i[12] => data_o.DATAB -data_i[13] => entry.DATAB -data_i[13] => entry.DATAB -data_i[13] => data_o.DATAB -data_i[14] => entry.DATAB -data_i[14] => entry.DATAB -data_i[14] => data_o.DATAB -data_i[15] => entry.DATAB -data_i[15] => entry.DATAB -data_i[15] => data_o.DATAB -data_i[16] => entry.DATAB -data_i[16] => entry.DATAB -data_i[16] => data_o.DATAB -data_i[17] => entry.DATAB -data_i[17] => entry.DATAB -data_i[17] => data_o.DATAB -data_i[18] => entry.DATAB -data_i[18] => entry.DATAB -data_i[18] => data_o.DATAB -data_i[19] => entry.DATAB -data_i[19] => entry.DATAB -data_i[19] => data_o.DATAB -data_i[20] => entry.DATAB -data_i[20] => entry.DATAB -data_i[20] => data_o.DATAB -data_i[21] => entry.DATAB -data_i[21] => entry.DATAB -data_i[21] => data_o.DATAB -data_i[22] => entry.DATAB -data_i[22] => entry.DATAB -data_i[22] => data_o.DATAB -data_i[23] => entry.DATAB -data_i[23] => entry.DATAB -data_i[23] => data_o.DATAB -data_i[24] => entry.DATAB -data_i[24] => entry.DATAB -data_i[24] => data_o.DATAB -data_i[25] => entry.DATAB -data_i[25] => entry.DATAB -data_i[25] => data_o.DATAB -data_i[26] => entry.DATAB -data_i[26] => entry.DATAB -data_i[26] => data_o.DATAB -data_i[27] => entry.DATAB -data_i[27] => entry.DATAB -data_i[27] => data_o.DATAB -data_i[28] => entry.DATAB -data_i[28] => entry.DATAB -data_i[28] => data_o.DATAB -data_i[29] => entry.DATAB -data_i[29] => entry.DATAB -data_i[29] => data_o.DATAB -data_i[30] => entry.DATAB -data_i[30] => entry.DATAB -data_i[30] => data_o.DATAB -data_i[31] => entry.DATAB -data_i[31] => entry.DATAB -data_i[31] => data_o.DATAB -data_i[32] => entry.DATAB -data_i[32] => entry.DATAB -data_i[32] => data_o.DATAB -data_i[33] => entry.DATAB -data_i[33] => entry.DATAB -data_i[33] => data_o.DATAB -data_i[34] => entry.DATAB -data_i[34] => entry.DATAB -data_i[34] => data_o.DATAB -data_i[35] => entry.DATAB -data_i[35] => entry.DATAB -data_i[35] => data_o.DATAB -data_i[36] => entry.DATAB -data_i[36] => entry.DATAB -data_i[36] => data_o.DATAB -data_i[37] => entry.DATAB -data_i[37] => entry.DATAB -data_i[37] => data_o.DATAB -data_i[38] => entry.DATAB -data_i[38] => entry.DATAB -data_i[38] => data_o.DATAB -data_i[39] => entry.DATAB -data_i[39] => entry.DATAB -data_i[39] => data_o.DATAB -data_i[40] => entry.DATAB -data_i[40] => entry.DATAB -data_i[40] => data_o.DATAB -data_o[0] <= data_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[1] <= data_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[2] <= data_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[3] <= data_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[4] <= data_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[5] <= data_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[6] <= data_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[7] <= data_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[8] <= data_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[9] <= data_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[10] <= data_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[11] <= data_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[12] <= data_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[13] <= data_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[14] <= data_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[15] <= data_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[16] <= data_o[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[17] <= data_o[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[18] <= data_o[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[19] <= data_o[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[20] <= data_o[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[21] <= data_o[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[22] <= data_o[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[23] <= data_o[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[24] <= data_o[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[25] <= data_o[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[26] <= data_o[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[27] <= data_o[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[28] <= data_o[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[29] <= data_o[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[30] <= data_o[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[31] <= data_o[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[32] <= data_o[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[33] <= data_o[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[34] <= data_o[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[35] <= data_o[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[36] <= data_o[36]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[37] <= data_o[37]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[38] <= data_o[38]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[39] <= data_o[39]~reg0.DB_MAX_OUTPUT_PORT_TYPE -data_o[40] <= data_o[40]~reg0.DB_MAX_OUTPUT_PORT_TYPE -status_empty_o <= status_empty.DB_MAX_OUTPUT_PORT_TYPE -status_full_o <= status_full.DB_MAX_OUTPUT_PORT_TYPE - - Index: syn/db/mesi_isc.rtlv_sg.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.rtlv_sg.cdb =================================================================== --- syn/db/mesi_isc.rtlv_sg.cdb (revision 4) +++ syn/db/mesi_isc.rtlv_sg.cdb (nonexistent)
syn/db/mesi_isc.rtlv_sg.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.analyze_file.qmsg =================================================================== --- syn/db/mesi_isc.analyze_file.qmsg (revision 4) +++ syn/db/mesi_isc.analyze_file.qmsg (nonexistent) @@ -1,5 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1356256079791 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus II 32-bit " "Running Quartus II 32-bit Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition " "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1356256079792 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 23 11:47:59 2012 " "Processing started: Sun Dec 23 11:47:59 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1356256079792 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1356256079792 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off mesi_isc -c mesi_isc --analyze_file=/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v " "Command: quartus_map --read_settings_files=on --write_settings_files=off mesi_isc -c mesi_isc --analyze_file=/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1356256079792 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "" 0 -1 1356256079971 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "362 " "Peak virtual memory: 362 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1356256080080 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 23 11:48:00 2012 " "Processing ended: Sun Dec 23 11:48:00 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1356256080080 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1356256080080 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1356256080080 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1356256080080 ""} Index: syn/db/mesi_isc.sld_design_entry.sci =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.sld_design_entry.sci =================================================================== --- syn/db/mesi_isc.sld_design_entry.sci (revision 4) +++ syn/db/mesi_isc.sld_design_entry.sci (nonexistent)
syn/db/mesi_isc.sld_design_entry.sci Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.map.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.map.hdb =================================================================== --- syn/db/mesi_isc.map.hdb (revision 4) +++ syn/db/mesi_isc.map.hdb (nonexistent)
syn/db/mesi_isc.map.hdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.cmp.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.cmp.hdb =================================================================== --- syn/db/mesi_isc.cmp.hdb (revision 4) +++ syn/db/mesi_isc.cmp.hdb (nonexistent)
syn/db/mesi_isc.cmp.hdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.(2).cnf.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.(2).cnf.cdb =================================================================== --- syn/db/mesi_isc.(2).cnf.cdb (revision 4) +++ syn/db/mesi_isc.(2).cnf.cdb (nonexistent)
syn/db/mesi_isc.(2).cnf.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.ace_cmp.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.ace_cmp.cdb =================================================================== --- syn/db/mesi_isc.ace_cmp.cdb (revision 4) +++ syn/db/mesi_isc.ace_cmp.cdb (nonexistent)
syn/db/mesi_isc.ace_cmp.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.pre_map.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.pre_map.hdb =================================================================== --- syn/db/mesi_isc.pre_map.hdb (revision 4) +++ syn/db/mesi_isc.pre_map.hdb (nonexistent)
syn/db/mesi_isc.pre_map.hdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.(0).cnf.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.(0).cnf.hdb =================================================================== --- syn/db/mesi_isc.(0).cnf.hdb (revision 4) +++ syn/db/mesi_isc.(0).cnf.hdb (nonexistent)
syn/db/mesi_isc.(0).cnf.hdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.(6).cnf.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.(6).cnf.cdb =================================================================== --- syn/db/mesi_isc.(6).cnf.cdb (revision 4) +++ syn/db/mesi_isc.(6).cnf.cdb (nonexistent)
syn/db/mesi_isc.(6).cnf.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.map.qmsg =================================================================== --- syn/db/mesi_isc.map.qmsg (revision 4) +++ syn/db/mesi_isc.map.qmsg (nonexistent) @@ -1,36 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1356436450049 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition " "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1356436450050 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 25 13:54:09 2012 " "Processing started: Tue Dec 25 13:54:09 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1356436450050 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1356436450050 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off mesi_isc -c mesi_isc " "Command: quartus_map --read_settings_files=on --write_settings_files=off mesi_isc -c mesi_isc" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1356436450050 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "" 0 -1 1356436450262 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_define.v 0 0 " "Found 0 design units, including 0 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_define.v" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1356436450369 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 mesi_isc_broad_cntl " "Found entity 1: mesi_isc_broad_cntl" { } { { "../src/rtl/mesi_isc_broad_cntl.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad_cntl.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1356436450374 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1356436450374 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad.v" { { "Info" "ISGN_ENTITY_NAME" "1 mesi_isc_broad " "Found entity 1: mesi_isc_broad" { } { { "../src/rtl/mesi_isc_broad.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1356436450376 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1356436450376 ""} -{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "mesi_isc_breq_fifos_cntl.v(294) " "Verilog HDL information at mesi_isc_breq_fifos_cntl.v(294): always construct contains both blocking and non-blocking assignments" { } { { "../src/rtl/mesi_isc_breq_fifos_cntl.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos_cntl.v" 294 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 -1 1356436450378 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 mesi_isc_breq_fifos_cntl " "Found entity 1: mesi_isc_breq_fifos_cntl" { } { { "../src/rtl/mesi_isc_breq_fifos_cntl.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos_cntl.v" 49 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1356436450379 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1356436450379 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos.v" { { "Info" "ISGN_ENTITY_NAME" "1 mesi_isc_breq_fifos " "Found entity 1: mesi_isc_breq_fifos" { } { { "../src/rtl/mesi_isc_breq_fifos.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos.v" 67 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1356436450381 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1356436450381 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 mesi_isc_basic_fifo " "Found entity 1: mesi_isc_basic_fifo" { } { { "../src/rtl/mesi_isc_basic_fifo.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" 48 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1356436450383 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1356436450383 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" { { "Info" "ISGN_ENTITY_NAME" "1 mesi_isc " "Found entity 1: mesi_isc" { } { { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1356436450385 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1356436450385 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "mesi_isc " "Elaborating entity \"mesi_isc\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1 1356436450490 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mesi_isc_broad mesi_isc_broad:mesi_isc_broad " "Elaborating entity \"mesi_isc_broad\" for hierarchy \"mesi_isc_broad:mesi_isc_broad\"" { } { { "../src/rtl/mesi_isc.v" "mesi_isc_broad" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 163 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1356436450495 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mesi_isc_broad_cntl mesi_isc_broad:mesi_isc_broad\|mesi_isc_broad_cntl:mesi_isc_broad_cntl " "Elaborating entity \"mesi_isc_broad_cntl\" for hierarchy \"mesi_isc_broad:mesi_isc_broad\|mesi_isc_broad_cntl:mesi_isc_broad_cntl\"" { } { { "../src/rtl/mesi_isc_broad.v" "mesi_isc_broad_cntl" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad.v" 138 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1356436450497 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mesi_isc_basic_fifo mesi_isc_broad:mesi_isc_broad\|mesi_isc_basic_fifo:broad_fifo " "Elaborating entity \"mesi_isc_basic_fifo\" for hierarchy \"mesi_isc_broad:mesi_isc_broad\|mesi_isc_basic_fifo:broad_fifo\"" { } { { "../src/rtl/mesi_isc_broad.v" "broad_fifo" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad.v" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1356436450500 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 mesi_isc_basic_fifo.v(122) " "Verilog HDL assignment warning at mesi_isc_basic_fifo.v(122): truncated value with size 32 to match size of target (2)" { } { { "../src/rtl/mesi_isc_basic_fifo.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" 122 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1 1356436450504 "|mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo"} -{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "i mesi_isc_basic_fifo.v(112) " "Verilog HDL Always Construct warning at mesi_isc_basic_fifo.v(112): inferring latch(es) for variable \"i\", which holds its previous value in one or more paths through the always construct" { } { { "../src/rtl/mesi_isc_basic_fifo.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" 112 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 -1 1356436450504 "|mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 mesi_isc_basic_fifo.v(154) " "Verilog HDL assignment warning at mesi_isc_basic_fifo.v(154): truncated value with size 32 to match size of target (2)" { } { { "../src/rtl/mesi_isc_basic_fifo.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1 1356436450504 "|mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 mesi_isc_basic_fifo.v(157) " "Verilog HDL assignment warning at mesi_isc_basic_fifo.v(157): truncated value with size 32 to match size of target (2)" { } { { "../src/rtl/mesi_isc_basic_fifo.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" 157 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1 1356436450504 "|mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mesi_isc_breq_fifos mesi_isc_breq_fifos:mesi_isc_breq_fifos " "Elaborating entity \"mesi_isc_breq_fifos\" for hierarchy \"mesi_isc_breq_fifos:mesi_isc_breq_fifos\"" { } { { "../src/rtl/mesi_isc.v" "mesi_isc_breq_fifos" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 200 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1356436450505 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mesi_isc_breq_fifos_cntl mesi_isc_breq_fifos:mesi_isc_breq_fifos\|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl " "Elaborating entity \"mesi_isc_breq_fifos_cntl\" for hierarchy \"mesi_isc_breq_fifos:mesi_isc_breq_fifos\|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl\"" { } { { "../src/rtl/mesi_isc_breq_fifos.v" "mesi_isc_breq_fifos_cntl" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos.v" 174 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1356436450509 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 mesi_isc_breq_fifos_cntl.v(371) " "Verilog HDL assignment warning at mesi_isc_breq_fifos_cntl.v(371): truncated value with size 32 to match size of target (3)" { } { { "../src/rtl/mesi_isc_breq_fifos_cntl.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos_cntl.v" 371 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1 1356436450512 "|mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mesi_isc_basic_fifo mesi_isc_breq_fifos:mesi_isc_breq_fifos\|mesi_isc_basic_fifo:fifo_3 " "Elaborating entity \"mesi_isc_basic_fifo\" for hierarchy \"mesi_isc_breq_fifos:mesi_isc_breq_fifos\|mesi_isc_basic_fifo:fifo_3\"" { } { { "../src/rtl/mesi_isc_breq_fifos.v" "fifo_3" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos.v" 234 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1356436450513 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 mesi_isc_basic_fifo.v(122) " "Verilog HDL assignment warning at mesi_isc_basic_fifo.v(122): truncated value with size 32 to match size of target (1)" { } { { "../src/rtl/mesi_isc_basic_fifo.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" 122 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1 1356436450515 "|mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3"} -{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "i mesi_isc_basic_fifo.v(112) " "Verilog HDL Always Construct warning at mesi_isc_basic_fifo.v(112): inferring latch(es) for variable \"i\", which holds its previous value in one or more paths through the always construct" { } { { "../src/rtl/mesi_isc_basic_fifo.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" 112 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 -1 1356436450515 "|mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 mesi_isc_basic_fifo.v(154) " "Verilog HDL assignment warning at mesi_isc_basic_fifo.v(154): truncated value with size 32 to match size of target (1)" { } { { "../src/rtl/mesi_isc_basic_fifo.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1 1356436450515 "|mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 mesi_isc_basic_fifo.v(157) " "Verilog HDL assignment warning at mesi_isc_basic_fifo.v(157): truncated value with size 32 to match size of target (1)" { } { { "../src/rtl/mesi_isc_basic_fifo.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" 157 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1 1356436450516 "|mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3"} -{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "" 0 -1 1356436451844 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "../src/rtl/mesi_isc_breq_fifos_cntl.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos_cntl.v" 177 -1 0 } } { "../src/rtl/mesi_isc_basic_fifo.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" 171 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "" 0 -1 1356436451905 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 -1 1356436451906 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "" 0 -1 1356436452498 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/yair/Work/Projects/mesi_isc/syn/mesi_isc.map.smsg " "Generated suppressed messages file /home/yair/Work/Projects/mesi_isc/syn/mesi_isc.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1 1356436453653 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "" 0 -1 1356436453827 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "" 0 -1 1356436453827 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "1101 " "Implemented 1101 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "146 " "Implemented 146 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "" 0 -1 1356436453981 ""} { "Info" "ICUT_CUT_TM_OPINS" "48 " "Implemented 48 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "" 0 -1 1356436453981 ""} { "Info" "ICUT_CUT_TM_LCELLS" "907 " "Implemented 907 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "" 0 -1 1356436453981 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1 1356436453981 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "370 " "Peak virtual memory: 370 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1356436453997 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 25 13:54:13 2012 " "Processing ended: Tue Dec 25 13:54:13 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1356436453997 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1356436453997 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1356436453997 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1356436453997 ""} Index: syn/db/mesi_isc.map.rdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.map.rdb =================================================================== --- syn/db/mesi_isc.map.rdb (revision 4) +++ syn/db/mesi_isc.map.rdb (nonexistent)
syn/db/mesi_isc.map.rdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.(4).cnf.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.(4).cnf.hdb =================================================================== --- syn/db/mesi_isc.(4).cnf.hdb (revision 4) +++ syn/db/mesi_isc.(4).cnf.hdb (nonexistent)
syn/db/mesi_isc.(4).cnf.hdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.cmp.rdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.cmp.rdb =================================================================== --- syn/db/mesi_isc.cmp.rdb (revision 4) +++ syn/db/mesi_isc.cmp.rdb (nonexistent)
syn/db/mesi_isc.cmp.rdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.idb.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.idb.cdb =================================================================== --- syn/db/mesi_isc.idb.cdb (revision 4) +++ syn/db/mesi_isc.idb.cdb (nonexistent)
syn/db/mesi_isc.idb.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.tis_db_list.ddb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.tis_db_list.ddb =================================================================== --- syn/db/mesi_isc.tis_db_list.ddb (revision 4) +++ syn/db/mesi_isc.tis_db_list.ddb (nonexistent)
syn/db/mesi_isc.tis_db_list.ddb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.stingray_io_sim_cache.45um_tt_1200mv_85c_slow.hsd =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.stingray_io_sim_cache.45um_tt_1200mv_85c_slow.hsd =================================================================== --- syn/db/mesi_isc.stingray_io_sim_cache.45um_tt_1200mv_85c_slow.hsd (revision 4) +++ syn/db/mesi_isc.stingray_io_sim_cache.45um_tt_1200mv_85c_slow.hsd (nonexistent)
syn/db/mesi_isc.stingray_io_sim_cache.45um_tt_1200mv_85c_slow.hsd Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.sta_cmp.6_slow_1200mv_85c.tdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.sta_cmp.6_slow_1200mv_85c.tdb =================================================================== --- syn/db/mesi_isc.sta_cmp.6_slow_1200mv_85c.tdb (revision 4) +++ syn/db/mesi_isc.sta_cmp.6_slow_1200mv_85c.tdb (nonexistent)
syn/db/mesi_isc.sta_cmp.6_slow_1200mv_85c.tdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.map.bpm =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.map.bpm =================================================================== --- syn/db/mesi_isc.map.bpm (revision 4) +++ syn/db/mesi_isc.map.bpm (nonexistent)
syn/db/mesi_isc.map.bpm Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.cmp.bpm =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.cmp.bpm =================================================================== --- syn/db/mesi_isc.cmp.bpm (revision 4) +++ syn/db/mesi_isc.cmp.bpm (nonexistent)
syn/db/mesi_isc.cmp.bpm Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.smart_action.txt =================================================================== --- syn/db/mesi_isc.smart_action.txt (revision 4) +++ syn/db/mesi_isc.smart_action.txt (nonexistent) @@ -1 +0,0 @@ -SOURCE Index: syn/db/mesi_isc.sld_design_entry_dsc.sci =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.sld_design_entry_dsc.sci =================================================================== --- syn/db/mesi_isc.sld_design_entry_dsc.sci (revision 4) +++ syn/db/mesi_isc.sld_design_entry_dsc.sci (nonexistent)
syn/db/mesi_isc.sld_design_entry_dsc.sci Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.hif =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.hif =================================================================== --- syn/db/mesi_isc.hif (revision 4) +++ syn/db/mesi_isc.hif (nonexistent)
syn/db/mesi_isc.hif Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.stingray_io_sim_cache.45um_ff_1200mv_0c_fast.hsd =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.stingray_io_sim_cache.45um_ff_1200mv_0c_fast.hsd =================================================================== --- syn/db/mesi_isc.stingray_io_sim_cache.45um_ff_1200mv_0c_fast.hsd (revision 4) +++ syn/db/mesi_isc.stingray_io_sim_cache.45um_ff_1200mv_0c_fast.hsd (nonexistent)
syn/db/mesi_isc.stingray_io_sim_cache.45um_ff_1200mv_0c_fast.hsd Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.map_bb.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.map_bb.cdb =================================================================== --- syn/db/mesi_isc.map_bb.cdb (revision 4) +++ syn/db/mesi_isc.map_bb.cdb (nonexistent)
syn/db/mesi_isc.map_bb.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.pow.qmsg =================================================================== --- syn/db/mesi_isc.pow.qmsg (revision 4) +++ syn/db/mesi_isc.pow.qmsg (nonexistent) @@ -1,18 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1356256126919 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "PowerPlay Power Analyzer Quartus II 32-bit " "Running Quartus II 32-bit PowerPlay Power Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition " "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1356256126919 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 23 11:48:46 2012 " "Processing started: Sun Dec 23 11:48:46 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1356256126919 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1356256126919 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_pow --read_settings_files=on --write_settings_files=off mesi_isc -c mesi_isc " "Command: quartus_pow --read_settings_files=on --write_settings_files=off mesi_isc -c mesi_isc" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1356256126920 ""} -{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0 -1 1356256127452 ""} -{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0 -1 1356256127453 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "mesi_isc.sdc " "Synopsys Design Constraints File file not found: 'mesi_isc.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "" 0 -1 1356256128244 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk " "Node: clk was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1 1356256128250 "|mesi_isc|clk"} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "" 0 -1 1356256128251 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "" 0 -1 1356256128259 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "" 0 -1 1356256128259 ""} -{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "" 0 -1 1356256128284 ""} -{ "Warning" "WPUTIL_PUTIL_NO_CLK_DOMAINS_FOUND" "" "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" { } { } 0 222013 "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" 0 0 "" 0 -1 1356256128285 ""} -{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "" 0 -1 1356256128307 ""} -{ "Info" "IPATFAM_USING_ADVANCED_IO_POWER" "" "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" { } { } 0 218000 "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" 0 0 "" 0 -1 1356256128742 ""} -{ "Warning" "WPAN_PAN_NO_THERMAL_MODEL_SELECTED" "" "No board thermal model was selected. Analyzing without board thermal modeling." { } { } 0 215044 "No board thermal model was selected. Analyzing without board thermal modeling." 0 0 "" 0 -1 1356256128769 ""} -{ "Info" "IPAN_AVG_TOGGLE_RATE_PER_DESIGN" "0.000 millions of transitions / sec " "Average toggle rate for this design is 0.000 millions of transitions / sec" { } { } 0 215049 "Average toggle rate for this design is %1!s!" 0 0 "" 0 -1 1356256136718 ""} -{ "Info" "IPAN_PAN_TOTAL_POWER_ESTIMATION" "178.89 mW " "Total thermal power estimate for the design is 178.89 mW" { } { { "/opt/12.0sp2/quartus/linux/Report_Window_01.qrpt" "" { Report "/opt/12.0sp2/quartus/linux/Report_Window_01.qrpt" "Compiler" "" "" "" "" { } "PowerPlay Power Analyzer Summary" } } } 0 215031 "Total thermal power estimate for the design is %1!s!" 0 0 "" 0 -1 1356256136728 ""} -{ "Info" "IQEXE_ERROR_COUNT" "PowerPlay Power Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit PowerPlay Power Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "428 " "Peak virtual memory: 428 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1356256136835 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 23 11:48:56 2012 " "Processing ended: Sun Dec 23 11:48:56 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1356256136835 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1356256136835 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1356256136835 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1356256136835 ""} Index: syn/db/mesi_isc.(3).cnf.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.(3).cnf.cdb =================================================================== --- syn/db/mesi_isc.(3).cnf.cdb (revision 4) +++ syn/db/mesi_isc.(3).cnf.cdb (nonexistent)
syn/db/mesi_isc.(3).cnf.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.(1).cnf.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.(1).cnf.hdb =================================================================== --- syn/db/mesi_isc.(1).cnf.hdb (revision 4) +++ syn/db/mesi_isc.(1).cnf.hdb (nonexistent)
syn/db/mesi_isc.(1).cnf.hdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.lpc.rdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.lpc.rdb =================================================================== --- syn/db/mesi_isc.lpc.rdb (revision 4) +++ syn/db/mesi_isc.lpc.rdb (nonexistent)
syn/db/mesi_isc.lpc.rdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.(5).cnf.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.(5).cnf.hdb =================================================================== --- syn/db/mesi_isc.(5).cnf.hdb (revision 4) +++ syn/db/mesi_isc.(5).cnf.hdb (nonexistent)
syn/db/mesi_isc.(5).cnf.hdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.asm.qmsg =================================================================== --- syn/db/mesi_isc.asm.qmsg (revision 4) +++ syn/db/mesi_isc.asm.qmsg (nonexistent) @@ -1,6 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1356436494645 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition " "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1356436494646 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 25 13:54:54 2012 " "Processing started: Tue Dec 25 13:54:54 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1356436494646 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1356436494646 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off mesi_isc -c mesi_isc " "Command: quartus_asm --read_settings_files=off --write_settings_files=off mesi_isc -c mesi_isc" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1356436494647 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1 1356436499458 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "" 0 -1 1356436499566 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "375 " "Peak virtual memory: 375 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1356436500714 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 25 13:55:00 2012 " "Processing ended: Tue Dec 25 13:55:00 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1356436500714 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1356436500714 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1356436500714 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1356436500714 ""} Index: syn/db/logic_util_heursitic.dat =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/logic_util_heursitic.dat =================================================================== --- syn/db/logic_util_heursitic.dat (revision 4) +++ syn/db/logic_util_heursitic.dat (nonexistent)
syn/db/logic_util_heursitic.dat Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.stingray_io_sim_cache.45um_tt_1200mv_0c_slow.hsd =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.stingray_io_sim_cache.45um_tt_1200mv_0c_slow.hsd =================================================================== --- syn/db/mesi_isc.stingray_io_sim_cache.45um_tt_1200mv_0c_slow.hsd (revision 4) +++ syn/db/mesi_isc.stingray_io_sim_cache.45um_tt_1200mv_0c_slow.hsd (nonexistent)
syn/db/mesi_isc.stingray_io_sim_cache.45um_tt_1200mv_0c_slow.hsd Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.stingray_io_sim_cache.45um_tt_1200mv_85c_nom.hsd =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.stingray_io_sim_cache.45um_tt_1200mv_85c_nom.hsd =================================================================== --- syn/db/mesi_isc.stingray_io_sim_cache.45um_tt_1200mv_85c_nom.hsd (revision 4) +++ syn/db/mesi_isc.stingray_io_sim_cache.45um_tt_1200mv_85c_nom.hsd (nonexistent)
syn/db/mesi_isc.stingray_io_sim_cache.45um_tt_1200mv_85c_nom.hsd Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.sta.qmsg =================================================================== --- syn/db/mesi_isc.sta.qmsg (revision 4) +++ syn/db/mesi_isc.sta.qmsg (nonexistent) @@ -1,36 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1356437044306 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition " "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1356437044307 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 25 14:04:04 2012 " "Processing started: Tue Dec 25 14:04:04 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1356437044307 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1356437044307 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta mesi_isc -c mesi_isc " "Command: quartus_sta mesi_isc -c mesi_isc" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1356437044307 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #2" { } { } 0 0 "qsta_default_script.tcl version: #2" 0 0 "" 0 0 1356437044346 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "" 0 -1 1356437044513 ""} -{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0 -1 1356437044614 ""} -{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0 -1 1356437044614 ""} -{ "Info" "ISTA_SDC_FOUND" "mesi_isc.sdc " "Reading SDC File: 'mesi_isc.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1356437045082 ""} -{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "" 0 -1 1356437045436 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "" 0 0 1356437045446 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "" 0 0 1356437045460 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "" 0 -1 1356437045510 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -8.340 " "Worst-case setup slack is -8.340" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437045511 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437045511 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.340 -2724.862 clk " " -8.340 -2724.862 clk " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437045511 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1356437045511 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.278 " "Worst-case hold slack is -0.278" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437045531 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437045531 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.278 -0.443 clk " " -0.278 -0.443 clk " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437045531 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1356437045531 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "" 0 -1 1356437045532 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "" 0 -1 1356437045533 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437045535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437045535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -643.000 clk " " -3.000 -643.000 clk " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437045535 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1356437045535 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "" 0 0 1356437045685 ""} -{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "" 0 -1 1356437045928 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "" 0 -1 1356437045988 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -7.387 " "Worst-case setup slack is -7.387" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437045990 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437045990 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -7.387 -2375.975 clk " " -7.387 -2375.975 clk " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437045990 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1356437045990 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.237 " "Worst-case hold slack is -0.237" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437046010 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437046010 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.237 -0.279 clk " " -0.237 -0.279 clk " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437046010 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1356437046010 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "" 0 -1 1356437046013 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "" 0 -1 1356437046016 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437046020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437046020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -643.000 clk " " -3.000 -643.000 clk " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437046020 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1356437046020 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "" 0 0 1356437046176 ""} -{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "" 0 -1 1356437046506 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "" 0 -1 1356437046535 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.682 " "Worst-case setup slack is -4.682" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437046540 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437046540 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.682 -1313.549 clk " " -4.682 -1313.549 clk " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437046540 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1356437046540 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.271 " "Worst-case hold slack is -0.271" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437046561 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437046561 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.271 -3.470 clk " " -0.271 -3.470 clk " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437046561 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1356437046561 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "" 0 -1 1356437046566 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "" 0 -1 1356437046570 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437046575 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437046575 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -651.247 clk " " -3.000 -651.247 clk " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1356437046575 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1356437046575 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1 1356437047395 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1 1356437047399 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "371 " "Peak virtual memory: 371 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1356437047512 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 25 14:04:07 2012 " "Processing ended: Tue Dec 25 14:04:07 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1356437047512 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1356437047512 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1356437047512 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1356437047512 ""} Index: syn/db/mesi_isc.sgdiff.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.sgdiff.hdb =================================================================== --- syn/db/mesi_isc.sgdiff.hdb (revision 4) +++ syn/db/mesi_isc.sgdiff.hdb (nonexistent)
syn/db/mesi_isc.sgdiff.hdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.amm.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.amm.cdb =================================================================== --- syn/db/mesi_isc.amm.cdb (revision 4) +++ syn/db/mesi_isc.amm.cdb (nonexistent)
syn/db/mesi_isc.amm.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.tiscmp.slow_1200mv_0c.ddb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.tiscmp.slow_1200mv_0c.ddb =================================================================== --- syn/db/mesi_isc.tiscmp.slow_1200mv_0c.ddb (revision 4) +++ syn/db/mesi_isc.tiscmp.slow_1200mv_0c.ddb (nonexistent)
syn/db/mesi_isc.tiscmp.slow_1200mv_0c.ddb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.rtlv_sg_swap.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.rtlv_sg_swap.cdb =================================================================== --- syn/db/mesi_isc.rtlv_sg_swap.cdb (revision 4) +++ syn/db/mesi_isc.rtlv_sg_swap.cdb (nonexistent)
syn/db/mesi_isc.rtlv_sg_swap.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.map.logdb =================================================================== --- syn/db/mesi_isc.map.logdb (revision 4) +++ syn/db/mesi_isc.map.logdb (nonexistent) @@ -1 +0,0 @@ -v1 Index: syn/db/mesi_isc.map.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.map.cdb =================================================================== --- syn/db/mesi_isc.map.cdb (revision 4) +++ syn/db/mesi_isc.map.cdb (nonexistent)
syn/db/mesi_isc.map.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/db/mesi_isc.cmp.logdb =================================================================== --- syn/db/mesi_isc.cmp.logdb (revision 4) +++ syn/db/mesi_isc.cmp.logdb (nonexistent) @@ -1,236 +0,0 @@ -v1 -IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, -IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,PASS,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,0 such failures found.,,I/O,, -IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, -IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, -IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, -IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, -IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,, -IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, -IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, -IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, -IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, -IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, -IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, -IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, -IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, -IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, -IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, -IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, -IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, -IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, -IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, -IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,, -IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, -IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, -IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, -IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, -IO_RULES_MATRIX,Total Pass,0;36;0;0;0;194;0;0;194;194;0;48;0;0;146;0;48;146;0;0;0;48;0;0;0;0;0;194;0;0, -IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, -IO_RULES_MATRIX,Total Inapplicable,194;158;194;194;194;0;194;194;0;0;194;146;194;194;48;194;146;48;194;194;194;146;194;194;194;194;194;0;194;194, -IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, -IO_RULES_MATRIX,cbus_addr_o[0],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[1],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[2],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[3],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[4],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[5],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[6],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[7],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[8],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[9],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[10],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[11],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[12],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[13],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[14],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[15],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[16],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[17],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[18],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[19],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[20],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[21],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[22],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[23],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[24],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[25],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[26],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[27],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[28],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[29],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[30],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_addr_o[31],Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_cmd3_o[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_cmd3_o[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_cmd3_o[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_cmd2_o[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_cmd2_o[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_cmd2_o[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_cmd1_o[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_cmd1_o[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_cmd1_o[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_cmd0_o[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_cmd0_o[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_cmd0_o[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_ack3_o,Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_ack2_o,Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_ack1_o,Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_ack0_o,Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,clk,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,rst,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_ack3_i,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_ack2_i,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_ack1_i,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,cbus_ack0_i,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_cmd3_i[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_cmd3_i[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_cmd3_i[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_cmd2_i[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_cmd2_i[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_cmd2_i[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_cmd1_i[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_cmd1_i[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_cmd1_i[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_cmd0_i[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_cmd0_i[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_cmd0_i[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[16],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[16],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[16],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[16],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[17],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[17],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[17],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[17],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[18],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[18],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[18],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[18],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[19],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[19],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[19],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[19],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[20],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[20],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[20],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[20],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[21],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[21],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[21],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[21],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[22],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[22],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[22],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[22],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[23],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[23],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[23],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[23],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[24],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[24],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[24],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[24],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[25],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[25],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[25],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[25],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[26],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[26],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[26],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[26],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[27],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[27],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[27],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[27],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[28],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[28],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[28],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[28],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[29],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[29],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[29],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[29],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[30],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[30],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[30],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[30],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr2_i[31],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr3_i[31],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr0_i[31],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,mbus_addr1_i[31],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_SUMMARY,Total I/O Rules,30, -IO_RULES_SUMMARY,Number of I/O Rules Passed,10, -IO_RULES_SUMMARY,Number of I/O Rules Failed,0, -IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, -IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,20, Index: syn/db/mesi_isc.cmp.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/db/mesi_isc.cmp.cdb =================================================================== --- syn/db/mesi_isc.cmp.cdb (revision 4) +++ syn/db/mesi_isc.cmp.cdb (nonexistent)
syn/db/mesi_isc.cmp.cdb Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: syn/mesi_isc.sta.rpt =================================================================== --- syn/mesi_isc.sta.rpt (revision 4) +++ syn/mesi_isc.sta.rpt (nonexistent) @@ -1,3550 +0,0 @@ -TimeQuest Timing Analyzer report for mesi_isc -Tue Dec 25 14:04:07 2012 -Quartus II 32-bit Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. TimeQuest Timing Analyzer Summary - 3. Parallel Compilation - 4. SDC File List - 5. Clocks - 6. Slow 1200mV 85C Model Fmax Summary - 7. Slow 1200mV 85C Model Setup Summary - 8. Slow 1200mV 85C Model Hold Summary - 9. Slow 1200mV 85C Model Recovery Summary - 10. Slow 1200mV 85C Model Removal Summary - 11. Slow 1200mV 85C Model Minimum Pulse Width Summary - 12. Slow 1200mV 85C Model Setup: 'clk' - 13. Slow 1200mV 85C Model Hold: 'clk' - 14. Slow 1200mV 85C Model Minimum Pulse Width: 'clk' - 15. Setup Times - 16. Hold Times - 17. Clock to Output Times - 18. Minimum Clock to Output Times - 19. Slow 1200mV 85C Model Metastability Report - 20. Slow 1200mV 0C Model Fmax Summary - 21. Slow 1200mV 0C Model Setup Summary - 22. Slow 1200mV 0C Model Hold Summary - 23. Slow 1200mV 0C Model Recovery Summary - 24. Slow 1200mV 0C Model Removal Summary - 25. Slow 1200mV 0C Model Minimum Pulse Width Summary - 26. Slow 1200mV 0C Model Setup: 'clk' - 27. Slow 1200mV 0C Model Hold: 'clk' - 28. Slow 1200mV 0C Model Minimum Pulse Width: 'clk' - 29. Setup Times - 30. Hold Times - 31. Clock to Output Times - 32. Minimum Clock to Output Times - 33. Slow 1200mV 0C Model Metastability Report - 34. Fast 1200mV 0C Model Setup Summary - 35. Fast 1200mV 0C Model Hold Summary - 36. Fast 1200mV 0C Model Recovery Summary - 37. Fast 1200mV 0C Model Removal Summary - 38. Fast 1200mV 0C Model Minimum Pulse Width Summary - 39. Fast 1200mV 0C Model Setup: 'clk' - 40. Fast 1200mV 0C Model Hold: 'clk' - 41. Fast 1200mV 0C Model Minimum Pulse Width: 'clk' - 42. Setup Times - 43. Hold Times - 44. Clock to Output Times - 45. Minimum Clock to Output Times - 46. Fast 1200mV 0C Model Metastability Report - 47. Multicorner Timing Analysis Summary - 48. Setup Times - 49. Hold Times - 50. Clock to Output Times - 51. Minimum Clock to Output Times - 52. Board Trace Model Assignments - 53. Input Transition Times - 54. Signal Integrity Metrics (Slow 1200mv 0c Model) - 55. Signal Integrity Metrics (Slow 1200mv 85c Model) - 56. Signal Integrity Metrics (Fast 1200mv 0c Model) - 57. Setup Transfers - 58. Hold Transfers - 59. Report TCCS - 60. Report RSKM - 61. Unconstrained Paths - 62. TimeQuest Timing Analyzer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2012 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+--------------------------------------------------------------------------------------+ -; TimeQuest Timing Analyzer Summary ; -+--------------------+-----------------------------------------------------------------+ -; Quartus II Version ; Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition ; -; Revision Name ; mesi_isc ; -; Device Family ; Cyclone IV GX ; -; Device Name ; EP4CGX30CF23C6 ; -; Timing Models ; Final ; -; Delay Model ; Combined ; -; Rise/Fall Delays ; Enabled ; -+--------------------+-----------------------------------------------------------------+ - - -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ - - -+---------------------------------------------------+ -; SDC File List ; -+---------------+--------+--------------------------+ -; SDC File Path ; Status ; Read at ; -+---------------+--------+--------------------------+ -; mesi_isc.sdc ; OK ; Tue Dec 25 14:04:05 2012 ; -+---------------+--------+--------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clocks ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ -; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ -; clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clk } ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ - - -+--------------------------------------------------+ -; Slow 1200mV 85C Model Fmax Summary ; -+------------+-----------------+------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+------------+-----------------+------------+------+ -; 107.07 MHz ; 107.07 MHz ; clk ; ; -+------------+-----------------+------------+------+ -This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. - - -+-------------------------------------+ -; Slow 1200mV 85C Model Setup Summary ; -+-------+--------+--------------------+ -; Clock ; Slack ; End Point TNS ; -+-------+--------+--------------------+ -; clk ; -8.340 ; -2724.862 ; -+-------+--------+--------------------+ - - -+------------------------------------+ -; Slow 1200mV 85C Model Hold Summary ; -+-------+--------+-------------------+ -; Clock ; Slack ; End Point TNS ; -+-------+--------+-------------------+ -; clk ; -0.278 ; -0.443 ; -+-------+--------+-------------------+ - - ------------------------------------------- -; Slow 1200mV 85C Model Recovery Summary ; ------------------------------------------- -No paths to report. - - ------------------------------------------ -; Slow 1200mV 85C Model Removal Summary ; ------------------------------------------ -No paths to report. - - -+---------------------------------------------------+ -; Slow 1200mV 85C Model Minimum Pulse Width Summary ; -+-------+--------+----------------------------------+ -; Clock ; Slack ; End Point TNS ; -+-------+--------+----------------------------------+ -; clk ; -3.000 ; -643.000 ; -+-------+--------+----------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Setup: 'clk' ; -+--------+------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -8.340 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -3.151 ; 6.069 ; -; -8.340 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -3.151 ; 6.069 ; -; -8.334 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -3.151 ; 6.063 ; -; -8.334 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -3.151 ; 6.063 ; -; -8.254 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -3.149 ; 5.985 ; -; -8.239 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -3.151 ; 5.968 ; -; -8.239 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -3.151 ; 5.968 ; -; -8.230 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -3.151 ; 5.959 ; -; -8.230 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -3.151 ; 5.959 ; -; -8.225 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -3.151 ; 5.954 ; -; -8.225 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -3.151 ; 5.954 ; -; -8.219 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -3.149 ; 5.950 ; -; -8.217 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -3.149 ; 5.948 ; -; -8.215 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -3.151 ; 5.944 ; -; -8.215 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -3.151 ; 5.944 ; -; -8.212 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -3.150 ; 5.942 ; -; -8.210 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -3.150 ; 5.940 ; -; -8.189 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -3.151 ; 5.918 ; -; -8.183 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -3.151 ; 5.912 ; -; -8.165 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -3.150 ; 5.895 ; -; -8.148 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -3.150 ; 5.878 ; -; -8.135 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[2] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -3.150 ; 5.865 ; -; -8.132 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -3.150 ; 5.862 ; -; -8.097 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -3.150 ; 5.827 ; -; -8.088 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -3.151 ; 5.817 ; -; -8.079 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -3.151 ; 5.808 ; -; -8.074 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -3.151 ; 5.803 ; -; -8.064 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -3.151 ; 5.793 ; -; -8.062 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -3.151 ; 5.791 ; -; -8.058 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[1] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -3.149 ; 5.789 ; -; -8.057 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[0] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -3.149 ; 5.788 ; -; -8.056 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -3.151 ; 5.785 ; -; -8.042 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -3.150 ; 5.772 ; -; -8.037 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[1] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -3.149 ; 5.768 ; -; -8.035 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -3.150 ; 5.765 ; -; -8.033 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -3.150 ; 5.763 ; -; -8.020 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -3.151 ; 5.749 ; -; -8.020 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -3.151 ; 5.749 ; -; -8.001 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -3.151 ; 5.730 ; -; -8.001 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -3.151 ; 5.730 ; -; -7.991 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -3.150 ; 5.721 ; -; -7.968 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -3.150 ; 5.698 ; -; -7.965 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -3.150 ; 5.695 ; -; -7.964 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -3.151 ; 5.693 ; -; -7.964 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -3.151 ; 5.693 ; -; -7.961 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -3.151 ; 5.690 ; -; -7.960 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -3.149 ; 5.691 ; -; -7.952 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -3.151 ; 5.681 ; -; -7.947 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -3.151 ; 5.676 ; -; -7.943 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -3.151 ; 5.672 ; -; -7.943 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -3.151 ; 5.672 ; -; -7.937 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -3.151 ; 5.666 ; -; -7.923 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -3.151 ; 5.652 ; -; -7.923 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -3.151 ; 5.652 ; -; -7.906 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -3.149 ; 5.637 ; -; -7.904 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -3.150 ; 5.634 ; -; -7.895 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -3.150 ; 5.625 ; -; -7.893 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -3.151 ; 5.622 ; -; -7.893 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -3.151 ; 5.622 ; -; -7.871 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -3.150 ; 5.601 ; -; -7.869 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -3.151 ; 5.598 ; -; -7.864 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -3.150 ; 5.594 ; -; -7.850 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -3.151 ; 5.579 ; -; -7.844 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -3.149 ; 5.575 ; -; -7.838 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[2] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -3.150 ; 5.568 ; -; -7.835 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[2] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -3.150 ; 5.565 ; -; -7.830 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -3.150 ; 5.560 ; -; -7.813 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -3.151 ; 5.542 ; -; -7.792 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -3.151 ; 5.521 ; -; -7.784 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -3.150 ; 5.514 ; -; -7.781 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -3.150 ; 5.511 ; -; -7.772 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -3.151 ; 5.501 ; -; -7.759 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -3.149 ; 5.490 ; -; -7.742 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -3.151 ; 5.471 ; -; -7.742 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -3.151 ; 5.471 ; -; -7.733 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[3] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -3.149 ; 5.464 ; -; -7.723 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -3.149 ; 5.454 ; -; -7.723 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -3.151 ; 5.452 ; -; -7.711 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -3.150 ; 5.441 ; -; -7.705 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -3.150 ; 5.435 ; -; -7.691 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -3.150 ; 5.421 ; -; -7.686 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -3.151 ; 5.415 ; -; -7.670 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -3.150 ; 5.400 ; -; -7.665 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -3.151 ; 5.394 ; -; -7.645 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -3.151 ; 5.374 ; -; -7.639 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -3.150 ; 5.369 ; -; -7.618 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[3] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -3.149 ; 5.349 ; -; -7.615 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -3.151 ; 5.344 ; -; -7.608 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -3.149 ; 5.339 ; -; -7.571 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -3.149 ; 5.302 ; -; -7.509 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[0] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -3.149 ; 5.240 ; -; -7.497 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -3.149 ; 5.228 ; -; -7.484 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[3] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -3.149 ; 5.215 ; -; -7.378 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[1] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -3.149 ; 5.109 ; -; -7.341 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[0] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -3.149 ; 5.072 ; -; -7.147 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -3.149 ; 4.878 ; -; -6.379 ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|status_empty ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[11] ; clk ; clk ; 1.000 ; -0.124 ; 7.153 ; -; -6.364 ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|status_empty ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[11] ; clk ; clk ; 1.000 ; -0.124 ; 7.138 ; -; -6.340 ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|status_empty ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[27] ; clk ; clk ; 1.000 ; -0.122 ; 7.116 ; -; -6.328 ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|status_empty ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[33] ; clk ; clk ; 1.000 ; -0.120 ; 7.106 ; -+--------+------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Hold: 'clk' ; -+--------+------------------+--------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+------------------+--------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -0.278 ; mbus_addr1_i[7] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][16] ; clk ; clk ; 0.000 ; 3.162 ; 2.941 ; -; -0.033 ; mbus_addr2_i[25] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][34] ; clk ; clk ; 0.000 ; 3.145 ; 3.169 ; -; -0.026 ; mbus_cmd3_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[7] ; clk ; clk ; 0.000 ; 3.151 ; 3.182 ; -; -0.019 ; mbus_addr1_i[27] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][36] ; clk ; clk ; 0.000 ; 3.132 ; 3.170 ; -; -0.018 ; mbus_addr1_i[4] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][13] ; clk ; clk ; 0.000 ; 3.132 ; 3.171 ; -; -0.018 ; mbus_addr1_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][14] ; clk ; clk ; 0.000 ; 3.137 ; 3.176 ; -; -0.018 ; mbus_addr1_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][14] ; clk ; clk ; 0.000 ; 3.137 ; 3.176 ; -; -0.015 ; mbus_addr0_i[30] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][39] ; clk ; clk ; 0.000 ; 3.167 ; 3.209 ; -; -0.015 ; mbus_addr0_i[30] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][39] ; clk ; clk ; 0.000 ; 3.167 ; 3.209 ; -; -0.003 ; mbus_addr0_i[8] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][17] ; clk ; clk ; 0.000 ; 3.100 ; 3.154 ; -; 0.003 ; mbus_cmd1_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[1]~_Duplicate_1 ; clk ; clk ; 0.000 ; 3.173 ; 3.233 ; -; 0.011 ; mbus_addr2_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][31] ; clk ; clk ; 0.000 ; 3.165 ; 3.233 ; -; 0.014 ; mbus_addr0_i[15] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][24] ; clk ; clk ; 0.000 ; 3.094 ; 3.165 ; -; 0.015 ; mbus_addr2_i[4] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][13] ; clk ; clk ; 0.000 ; 3.121 ; 3.193 ; -; 0.019 ; mbus_addr2_i[3] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][12] ; clk ; clk ; 0.000 ; 3.123 ; 3.199 ; -; 0.029 ; mbus_cmd0_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[0] ; clk ; clk ; 0.000 ; 3.115 ; 3.201 ; -; 0.034 ; mbus_cmd0_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[0]~_Duplicate_1 ; clk ; clk ; 0.000 ; 3.115 ; 3.206 ; -; 0.036 ; mbus_addr2_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][21] ; clk ; clk ; 0.000 ; 3.130 ; 3.223 ; -; 0.037 ; mbus_addr0_i[21] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][30] ; clk ; clk ; 0.000 ; 3.126 ; 3.220 ; -; 0.038 ; mbus_cmd0_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[0]~_Duplicate_1 ; clk ; clk ; 0.000 ; 3.115 ; 3.210 ; -; 0.045 ; mbus_addr1_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][21] ; clk ; clk ; 0.000 ; 3.132 ; 3.234 ; -; 0.048 ; mbus_addr0_i[7] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][16] ; clk ; clk ; 0.000 ; 3.173 ; 3.278 ; -; 0.050 ; mbus_addr1_i[30] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][39] ; clk ; clk ; 0.000 ; 3.118 ; 3.225 ; -; 0.052 ; mbus_addr1_i[30] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][39] ; clk ; clk ; 0.000 ; 3.117 ; 3.226 ; -; 0.054 ; mbus_addr3_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][21] ; clk ; clk ; 0.000 ; 3.107 ; 3.218 ; -; 0.056 ; mbus_addr3_i[11] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][20] ; clk ; clk ; 0.000 ; 3.132 ; 3.245 ; -; 0.058 ; mbus_cmd1_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[3] ; clk ; clk ; 0.000 ; 3.172 ; 3.287 ; -; 0.059 ; mbus_addr3_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][14] ; clk ; clk ; 0.000 ; 3.105 ; 3.221 ; -; 0.060 ; mbus_addr2_i[3] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[12] ; clk ; clk ; 0.000 ; 3.123 ; 3.240 ; -; 0.065 ; mbus_addr1_i[9] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][18] ; clk ; clk ; 0.000 ; 3.131 ; 3.253 ; -; 0.069 ; mbus_addr1_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[21] ; clk ; clk ; 0.000 ; 3.127 ; 3.253 ; -; 0.071 ; cbus_ack0_i ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; clk ; clk ; 0.000 ; 3.149 ; 3.277 ; -; 0.077 ; mbus_addr1_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][21] ; clk ; clk ; 0.000 ; 3.133 ; 3.267 ; -; 0.078 ; mbus_addr1_i[31] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][40] ; clk ; clk ; 0.000 ; 3.132 ; 3.267 ; -; 0.084 ; mbus_cmd0_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[1] ; clk ; clk ; 0.000 ; 3.115 ; 3.256 ; -; 0.088 ; mbus_addr2_i[3] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][12] ; clk ; clk ; 0.000 ; 3.121 ; 3.266 ; -; 0.088 ; mbus_addr2_i[4] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][13] ; clk ; clk ; 0.000 ; 3.123 ; 3.268 ; -; 0.089 ; mbus_addr0_i[8] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][17] ; clk ; clk ; 0.000 ; 3.126 ; 3.272 ; -; 0.090 ; mbus_addr0_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][21] ; clk ; clk ; 0.000 ; 3.097 ; 3.244 ; -; 0.094 ; mbus_addr2_i[9] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][18] ; clk ; clk ; 0.000 ; 3.105 ; 3.256 ; -; 0.095 ; mbus_addr0_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][31] ; clk ; clk ; 0.000 ; 3.100 ; 3.252 ; -; 0.096 ; mbus_addr0_i[26] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][35] ; clk ; clk ; 0.000 ; 3.094 ; 3.247 ; -; 0.097 ; mbus_addr3_i[23] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][32] ; clk ; clk ; 0.000 ; 3.089 ; 3.243 ; -; 0.098 ; mbus_addr2_i[17] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][26] ; clk ; clk ; 0.000 ; 3.132 ; 3.287 ; -; 0.098 ; mbus_addr0_i[29] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][38] ; clk ; clk ; 0.000 ; 3.108 ; 3.263 ; -; 0.099 ; mbus_addr2_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][31] ; clk ; clk ; 0.000 ; 3.139 ; 3.295 ; -; 0.105 ; mbus_cmd2_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[4] ; clk ; clk ; 0.000 ; 3.144 ; 3.306 ; -; 0.107 ; mbus_addr1_i[10] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][19] ; clk ; clk ; 0.000 ; 3.147 ; 3.311 ; -; 0.108 ; mbus_addr0_i[19] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][28] ; clk ; clk ; 0.000 ; 3.126 ; 3.291 ; -; 0.108 ; mbus_addr2_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][14] ; clk ; clk ; 0.000 ; 3.141 ; 3.306 ; -; 0.109 ; mbus_addr0_i[20] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][29] ; clk ; clk ; 0.000 ; 3.124 ; 3.290 ; -; 0.114 ; mbus_addr1_i[28] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][37] ; clk ; clk ; 0.000 ; 3.117 ; 3.288 ; -; 0.114 ; mbus_cmd1_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[2] ; clk ; clk ; 0.000 ; 3.172 ; 3.343 ; -; 0.114 ; mbus_addr2_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][14] ; clk ; clk ; 0.000 ; 3.127 ; 3.298 ; -; 0.115 ; mbus_addr0_i[25] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][34] ; clk ; clk ; 0.000 ; 3.106 ; 3.278 ; -; 0.115 ; mbus_addr1_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][31] ; clk ; clk ; 0.000 ; 3.144 ; 3.316 ; -; 0.116 ; mbus_addr3_i[7] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][16] ; clk ; clk ; 0.000 ; 3.160 ; 3.333 ; -; 0.118 ; mbus_addr3_i[19] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][28] ; clk ; clk ; 0.000 ; 3.087 ; 3.262 ; -; 0.118 ; mbus_addr1_i[23] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][32] ; clk ; clk ; 0.000 ; 3.135 ; 3.310 ; -; 0.120 ; mbus_addr0_i[29] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][38] ; clk ; clk ; 0.000 ; 3.126 ; 3.303 ; -; 0.120 ; mbus_addr2_i[9] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][18] ; clk ; clk ; 0.000 ; 3.102 ; 3.279 ; -; 0.120 ; mbus_addr1_i[23] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][32] ; clk ; clk ; 0.000 ; 3.140 ; 3.317 ; -; 0.121 ; mbus_addr2_i[6] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][15] ; clk ; clk ; 0.000 ; 3.137 ; 3.315 ; -; 0.123 ; mbus_addr1_i[10] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][19] ; clk ; clk ; 0.000 ; 3.124 ; 3.304 ; -; 0.123 ; mbus_addr0_i[21] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][30] ; clk ; clk ; 0.000 ; 3.124 ; 3.304 ; -; 0.123 ; mbus_addr1_i[27] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][36] ; clk ; clk ; 0.000 ; 3.124 ; 3.304 ; -; 0.123 ; mbus_cmd1_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[1] ; clk ; clk ; 0.000 ; 3.131 ; 3.255 ; -; 0.124 ; mbus_addr1_i[9] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][18] ; clk ; clk ; 0.000 ; 3.135 ; 3.316 ; -; 0.125 ; mbus_addr2_i[4] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[13] ; clk ; clk ; 0.000 ; 3.123 ; 3.305 ; -; 0.126 ; mbus_cmd3_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[6] ; clk ; clk ; 0.000 ; 3.151 ; 3.334 ; -; 0.127 ; mbus_addr3_i[14] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][23] ; clk ; clk ; 0.000 ; 3.124 ; 3.308 ; -; 0.127 ; mbus_addr2_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][21] ; clk ; clk ; 0.000 ; 3.105 ; 3.289 ; -; 0.129 ; mbus_addr0_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][31] ; clk ; clk ; 0.000 ; 3.101 ; 3.287 ; -; 0.130 ; mbus_addr2_i[16] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][25] ; clk ; clk ; 0.000 ; 3.140 ; 3.327 ; -; 0.131 ; mbus_addr2_i[9] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[18] ; clk ; clk ; 0.000 ; 3.105 ; 3.293 ; -; 0.132 ; mbus_addr2_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][11] ; clk ; clk ; 0.000 ; 3.123 ; 3.312 ; -; 0.133 ; mbus_addr0_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[31] ; clk ; clk ; 0.000 ; 3.100 ; 3.290 ; -; 0.133 ; mbus_addr2_i[25] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][34] ; clk ; clk ; 0.000 ; 3.137 ; 3.327 ; -; 0.134 ; mbus_addr0_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][21] ; clk ; clk ; 0.000 ; 3.095 ; 3.286 ; -; 0.135 ; mbus_addr3_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][10] ; clk ; clk ; 0.000 ; 3.090 ; 3.282 ; -; 0.135 ; mbus_addr1_i[20] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][29] ; clk ; clk ; 0.000 ; 3.135 ; 3.327 ; -; 0.135 ; mbus_addr2_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[31] ; clk ; clk ; 0.000 ; 3.165 ; 3.357 ; -; 0.135 ; mbus_addr1_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][31] ; clk ; clk ; 0.000 ; 3.141 ; 3.333 ; -; 0.137 ; mbus_addr2_i[18] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][27] ; clk ; clk ; 0.000 ; 3.132 ; 3.326 ; -; 0.137 ; mbus_addr1_i[26] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][35] ; clk ; clk ; 0.000 ; 3.128 ; 3.322 ; -; 0.138 ; mbus_addr2_i[17] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][26] ; clk ; clk ; 0.000 ; 3.113 ; 3.308 ; -; 0.138 ; mbus_addr2_i[8] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][17] ; clk ; clk ; 0.000 ; 3.105 ; 3.300 ; -; 0.141 ; mbus_addr0_i[9] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][18] ; clk ; clk ; 0.000 ; 3.124 ; 3.322 ; -; 0.143 ; mbus_addr3_i[20] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][29] ; clk ; clk ; 0.000 ; 3.107 ; 3.307 ; -; 0.143 ; mbus_addr0_i[28] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][37] ; clk ; clk ; 0.000 ; 3.106 ; 3.306 ; -; 0.144 ; mbus_cmd2_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[4] ; clk ; clk ; 0.000 ; 3.144 ; 3.345 ; -; 0.145 ; mbus_addr0_i[20] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][29] ; clk ; clk ; 0.000 ; 3.126 ; 3.328 ; -; 0.145 ; mbus_addr0_i[27] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][36] ; clk ; clk ; 0.000 ; 3.108 ; 3.310 ; -; 0.145 ; mbus_addr2_i[7] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][16] ; clk ; clk ; 0.000 ; 3.127 ; 3.329 ; -; 0.146 ; mbus_addr0_i[16] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][25] ; clk ; clk ; 0.000 ; 3.095 ; 3.298 ; -; 0.146 ; mbus_addr2_i[14] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][23] ; clk ; clk ; 0.000 ; 3.121 ; 3.324 ; -; 0.147 ; mbus_addr2_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[14] ; clk ; clk ; 0.000 ; 3.141 ; 3.345 ; -; 0.151 ; mbus_addr1_i[28] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[37] ; clk ; clk ; 0.000 ; 3.117 ; 3.325 ; -; 0.151 ; mbus_addr0_i[29] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[38] ; clk ; clk ; 0.000 ; 3.122 ; 3.330 ; -; 0.151 ; mbus_cmd2_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[4] ; clk ; clk ; 0.000 ; 3.144 ; 3.352 ; -+--------+------------------+--------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Minimum Pulse Width: 'clk' ; -+--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------------------------+ -; -3.000 ; 1.000 ; 4.000 ; Port Rate ; clk ; Rise ; clk ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[10] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[11] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[12] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[13] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[14] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[15] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[16] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[17] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[18] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[19] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[20] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[21] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[22] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[23] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[24] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[25] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[26] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[27] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[28] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[29] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[30] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[31] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[32] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[33] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[34] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[35] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[36] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[37] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[38] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[39] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[40] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[7] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[8] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[9] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][10] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][11] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][12] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][13] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][14] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][15] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][16] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][17] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][18] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][19] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][20] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][21] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][22] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][23] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][24] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][25] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][26] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][27] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][28] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][29] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][30] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][31] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][32] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][33] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][34] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][35] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][36] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][37] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][38] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][39] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][40] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][7] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][8] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][9] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][10] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][11] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][12] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][13] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][14] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][15] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][16] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][17] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][18] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][19] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][20] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][21] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][22] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][23] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][24] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][25] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][26] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][27] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][28] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][29] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][30] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][31] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][32] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][33] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][34] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][35] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][36] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][37] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][38] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][39] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][40] ; -+--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------+ -; Setup Times ; -+-------------------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-------------------+------------+-------+-------+------------+-----------------+ -; cbus_ack0_i ; clk ; 0.517 ; 0.748 ; Rise ; clk ; -; cbus_ack1_i ; clk ; 0.631 ; 0.820 ; Rise ; clk ; -; cbus_ack2_i ; clk ; 0.850 ; 0.811 ; Rise ; clk ; -; cbus_ack3_i ; clk ; 0.769 ; 0.740 ; Rise ; clk ; -; mbus_addr0_i[*] ; clk ; 0.799 ; 0.938 ; Rise ; clk ; -; mbus_addr0_i[0] ; clk ; 0.638 ; 0.872 ; Rise ; clk ; -; mbus_addr0_i[1] ; clk ; 0.551 ; 0.779 ; Rise ; clk ; -; mbus_addr0_i[2] ; clk ; 0.649 ; 0.885 ; Rise ; clk ; -; mbus_addr0_i[3] ; clk ; 0.609 ; 0.829 ; Rise ; clk ; -; mbus_addr0_i[4] ; clk ; 0.662 ; 0.895 ; Rise ; clk ; -; mbus_addr0_i[5] ; clk ; 0.572 ; 0.800 ; Rise ; clk ; -; mbus_addr0_i[6] ; clk ; 0.616 ; 0.862 ; Rise ; clk ; -; mbus_addr0_i[7] ; clk ; 0.518 ; 0.868 ; Rise ; clk ; -; mbus_addr0_i[8] ; clk ; 0.528 ; 0.883 ; Rise ; clk ; -; mbus_addr0_i[9] ; clk ; 0.595 ; 0.833 ; Rise ; clk ; -; mbus_addr0_i[10] ; clk ; 0.619 ; 0.835 ; Rise ; clk ; -; mbus_addr0_i[11] ; clk ; 0.687 ; 0.871 ; Rise ; clk ; -; mbus_addr0_i[12] ; clk ; 0.456 ; 0.742 ; Rise ; clk ; -; mbus_addr0_i[13] ; clk ; 0.585 ; 0.781 ; Rise ; clk ; -; mbus_addr0_i[14] ; clk ; 0.616 ; 0.854 ; Rise ; clk ; -; mbus_addr0_i[15] ; clk ; 0.560 ; 0.938 ; Rise ; clk ; -; mbus_addr0_i[16] ; clk ; 0.555 ; 0.788 ; Rise ; clk ; -; mbus_addr0_i[17] ; clk ; 0.799 ; 0.824 ; Rise ; clk ; -; mbus_addr0_i[18] ; clk ; 0.627 ; 0.882 ; Rise ; clk ; -; mbus_addr0_i[19] ; clk ; 0.616 ; 0.845 ; Rise ; clk ; -; mbus_addr0_i[20] ; clk ; 0.566 ; 0.807 ; Rise ; clk ; -; mbus_addr0_i[21] ; clk ; 0.451 ; 0.745 ; Rise ; clk ; -; mbus_addr0_i[22] ; clk ; 0.428 ; 0.709 ; Rise ; clk ; -; mbus_addr0_i[23] ; clk ; 0.636 ; 0.846 ; Rise ; clk ; -; mbus_addr0_i[24] ; clk ; 0.618 ; 0.864 ; Rise ; clk ; -; mbus_addr0_i[25] ; clk ; 0.531 ; 0.802 ; Rise ; clk ; -; mbus_addr0_i[26] ; clk ; 0.504 ; 0.784 ; Rise ; clk ; -; mbus_addr0_i[27] ; clk ; 0.635 ; 0.888 ; Rise ; clk ; -; mbus_addr0_i[28] ; clk ; 0.551 ; 0.761 ; Rise ; clk ; -; mbus_addr0_i[29] ; clk ; 0.438 ; 0.740 ; Rise ; clk ; -; mbus_addr0_i[30] ; clk ; 0.511 ; 0.853 ; Rise ; clk ; -; mbus_addr0_i[31] ; clk ; 0.519 ; 0.756 ; Rise ; clk ; -; mbus_addr1_i[*] ; clk ; 0.883 ; 1.090 ; Rise ; clk ; -; mbus_addr1_i[0] ; clk ; 0.531 ; 0.741 ; Rise ; clk ; -; mbus_addr1_i[1] ; clk ; 0.627 ; 0.900 ; Rise ; clk ; -; mbus_addr1_i[2] ; clk ; 0.527 ; 0.800 ; Rise ; clk ; -; mbus_addr1_i[3] ; clk ; 0.632 ; 0.883 ; Rise ; clk ; -; mbus_addr1_i[4] ; clk ; 0.517 ; 0.839 ; Rise ; clk ; -; mbus_addr1_i[5] ; clk ; 0.475 ; 0.818 ; Rise ; clk ; -; mbus_addr1_i[6] ; clk ; 0.699 ; 0.940 ; Rise ; clk ; -; mbus_addr1_i[7] ; clk ; 0.603 ; 0.934 ; Rise ; clk ; -; mbus_addr1_i[8] ; clk ; 0.542 ; 0.787 ; Rise ; clk ; -; mbus_addr1_i[9] ; clk ; 0.451 ; 0.769 ; Rise ; clk ; -; mbus_addr1_i[10] ; clk ; 0.450 ; 0.760 ; Rise ; clk ; -; mbus_addr1_i[11] ; clk ; 0.574 ; 0.838 ; Rise ; clk ; -; mbus_addr1_i[12] ; clk ; 0.375 ; 0.670 ; Rise ; clk ; -; mbus_addr1_i[13] ; clk ; 0.546 ; 0.781 ; Rise ; clk ; -; mbus_addr1_i[14] ; clk ; 0.649 ; 0.823 ; Rise ; clk ; -; mbus_addr1_i[15] ; clk ; 0.832 ; 1.040 ; Rise ; clk ; -; mbus_addr1_i[16] ; clk ; 0.530 ; 0.778 ; Rise ; clk ; -; mbus_addr1_i[17] ; clk ; 0.634 ; 0.727 ; Rise ; clk ; -; mbus_addr1_i[18] ; clk ; 0.693 ; 0.783 ; Rise ; clk ; -; mbus_addr1_i[19] ; clk ; 0.610 ; 0.793 ; Rise ; clk ; -; mbus_addr1_i[20] ; clk ; 0.535 ; 0.810 ; Rise ; clk ; -; mbus_addr1_i[21] ; clk ; 0.633 ; 0.795 ; Rise ; clk ; -; mbus_addr1_i[22] ; clk ; 0.458 ; 0.696 ; Rise ; clk ; -; mbus_addr1_i[23] ; clk ; 0.444 ; 0.746 ; Rise ; clk ; -; mbus_addr1_i[24] ; clk ; 0.508 ; 0.763 ; Rise ; clk ; -; mbus_addr1_i[25] ; clk ; 0.883 ; 1.090 ; Rise ; clk ; -; mbus_addr1_i[26] ; clk ; 0.501 ; 0.818 ; Rise ; clk ; -; mbus_addr1_i[27] ; clk ; 0.446 ; 0.721 ; Rise ; clk ; -; mbus_addr1_i[28] ; clk ; 0.440 ; 0.634 ; Rise ; clk ; -; mbus_addr1_i[29] ; clk ; 0.633 ; 0.894 ; Rise ; clk ; -; mbus_addr1_i[30] ; clk ; 0.541 ; 0.828 ; Rise ; clk ; -; mbus_addr1_i[31] ; clk ; 0.605 ; 0.873 ; Rise ; clk ; -; mbus_addr2_i[*] ; clk ; 0.807 ; 1.054 ; Rise ; clk ; -; mbus_addr2_i[0] ; clk ; 0.533 ; 0.846 ; Rise ; clk ; -; mbus_addr2_i[1] ; clk ; 0.577 ; 0.802 ; Rise ; clk ; -; mbus_addr2_i[2] ; clk ; 0.560 ; 0.794 ; Rise ; clk ; -; mbus_addr2_i[3] ; clk ; 0.371 ; 0.687 ; Rise ; clk ; -; mbus_addr2_i[4] ; clk ; 0.409 ; 0.777 ; Rise ; clk ; -; mbus_addr2_i[5] ; clk ; 0.435 ; 0.748 ; Rise ; clk ; -; mbus_addr2_i[6] ; clk ; 0.476 ; 0.741 ; Rise ; clk ; -; mbus_addr2_i[7] ; clk ; 0.570 ; 0.694 ; Rise ; clk ; -; mbus_addr2_i[8] ; clk ; 0.459 ; 0.775 ; Rise ; clk ; -; mbus_addr2_i[9] ; clk ; 0.415 ; 0.702 ; Rise ; clk ; -; mbus_addr2_i[10] ; clk ; 0.685 ; 0.918 ; Rise ; clk ; -; mbus_addr2_i[11] ; clk ; 0.593 ; 0.857 ; Rise ; clk ; -; mbus_addr2_i[12] ; clk ; 0.497 ; 0.854 ; Rise ; clk ; -; mbus_addr2_i[13] ; clk ; 0.515 ; 0.852 ; Rise ; clk ; -; mbus_addr2_i[14] ; clk ; 0.533 ; 0.780 ; Rise ; clk ; -; mbus_addr2_i[15] ; clk ; 0.520 ; 0.787 ; Rise ; clk ; -; mbus_addr2_i[16] ; clk ; 0.636 ; 0.868 ; Rise ; clk ; -; mbus_addr2_i[17] ; clk ; 0.463 ; 0.790 ; Rise ; clk ; -; mbus_addr2_i[18] ; clk ; 0.496 ; 0.821 ; Rise ; clk ; -; mbus_addr2_i[19] ; clk ; 0.557 ; 0.701 ; Rise ; clk ; -; mbus_addr2_i[20] ; clk ; 0.547 ; 0.661 ; Rise ; clk ; -; mbus_addr2_i[21] ; clk ; 0.559 ; 0.802 ; Rise ; clk ; -; mbus_addr2_i[22] ; clk ; 0.460 ; 0.790 ; Rise ; clk ; -; mbus_addr2_i[23] ; clk ; 0.591 ; 0.863 ; Rise ; clk ; -; mbus_addr2_i[24] ; clk ; 0.493 ; 0.724 ; Rise ; clk ; -; mbus_addr2_i[25] ; clk ; 0.462 ; 0.818 ; Rise ; clk ; -; mbus_addr2_i[26] ; clk ; 0.519 ; 0.805 ; Rise ; clk ; -; mbus_addr2_i[27] ; clk ; 0.807 ; 1.054 ; Rise ; clk ; -; mbus_addr2_i[28] ; clk ; 0.483 ; 0.829 ; Rise ; clk ; -; mbus_addr2_i[29] ; clk ; 0.600 ; 0.872 ; Rise ; clk ; -; mbus_addr2_i[30] ; clk ; 0.547 ; 0.774 ; Rise ; clk ; -; mbus_addr2_i[31] ; clk ; 0.682 ; 0.961 ; Rise ; clk ; -; mbus_addr3_i[*] ; clk ; 0.779 ; 1.045 ; Rise ; clk ; -; mbus_addr3_i[0] ; clk ; 0.620 ; 0.860 ; Rise ; clk ; -; mbus_addr3_i[1] ; clk ; 0.578 ; 0.796 ; Rise ; clk ; -; mbus_addr3_i[2] ; clk ; 0.616 ; 0.884 ; Rise ; clk ; -; mbus_addr3_i[3] ; clk ; 0.649 ; 0.844 ; Rise ; clk ; -; mbus_addr3_i[4] ; clk ; 0.658 ; 0.899 ; Rise ; clk ; -; mbus_addr3_i[5] ; clk ; 0.512 ; 0.843 ; Rise ; clk ; -; mbus_addr3_i[6] ; clk ; 0.562 ; 0.812 ; Rise ; clk ; -; mbus_addr3_i[7] ; clk ; 0.779 ; 1.045 ; Rise ; clk ; -; mbus_addr3_i[8] ; clk ; 0.568 ; 0.834 ; Rise ; clk ; -; mbus_addr3_i[9] ; clk ; 0.589 ; 0.824 ; Rise ; clk ; -; mbus_addr3_i[10] ; clk ; 0.600 ; 0.858 ; Rise ; clk ; -; mbus_addr3_i[11] ; clk ; 0.650 ; 0.889 ; Rise ; clk ; -; mbus_addr3_i[12] ; clk ; 0.536 ; 0.869 ; Rise ; clk ; -; mbus_addr3_i[13] ; clk ; 0.599 ; 0.800 ; Rise ; clk ; -; mbus_addr3_i[14] ; clk ; 0.522 ; 0.814 ; Rise ; clk ; -; mbus_addr3_i[15] ; clk ; 0.560 ; 0.781 ; Rise ; clk ; -; mbus_addr3_i[16] ; clk ; 0.692 ; 0.856 ; Rise ; clk ; -; mbus_addr3_i[17] ; clk ; 0.563 ; 0.835 ; Rise ; clk ; -; mbus_addr3_i[18] ; clk ; 0.649 ; 0.886 ; Rise ; clk ; -; mbus_addr3_i[19] ; clk ; 0.679 ; 0.959 ; Rise ; clk ; -; mbus_addr3_i[20] ; clk ; 0.603 ; 0.859 ; Rise ; clk ; -; mbus_addr3_i[21] ; clk ; 0.545 ; 0.787 ; Rise ; clk ; -; mbus_addr3_i[22] ; clk ; 0.614 ; 0.794 ; Rise ; clk ; -; mbus_addr3_i[23] ; clk ; 0.526 ; 0.847 ; Rise ; clk ; -; mbus_addr3_i[24] ; clk ; 0.581 ; 0.872 ; Rise ; clk ; -; mbus_addr3_i[25] ; clk ; 0.515 ; 0.803 ; Rise ; clk ; -; mbus_addr3_i[26] ; clk ; 0.613 ; 0.973 ; Rise ; clk ; -; mbus_addr3_i[27] ; clk ; 0.703 ; 0.926 ; Rise ; clk ; -; mbus_addr3_i[28] ; clk ; 0.580 ; 0.804 ; Rise ; clk ; -; mbus_addr3_i[29] ; clk ; 0.708 ; 0.952 ; Rise ; clk ; -; mbus_addr3_i[30] ; clk ; 0.514 ; 0.807 ; Rise ; clk ; -; mbus_addr3_i[31] ; clk ; 0.535 ; 0.885 ; Rise ; clk ; -; mbus_cmd0_i[*] ; clk ; 0.746 ; 0.907 ; Rise ; clk ; -; mbus_cmd0_i[0] ; clk ; 0.654 ; 0.838 ; Rise ; clk ; -; mbus_cmd0_i[1] ; clk ; 0.746 ; 0.907 ; Rise ; clk ; -; mbus_cmd0_i[2] ; clk ; 0.602 ; 0.752 ; Rise ; clk ; -; mbus_cmd1_i[*] ; clk ; 0.803 ; 1.064 ; Rise ; clk ; -; mbus_cmd1_i[0] ; clk ; 0.731 ; 0.996 ; Rise ; clk ; -; mbus_cmd1_i[1] ; clk ; 0.621 ; 0.908 ; Rise ; clk ; -; mbus_cmd1_i[2] ; clk ; 0.803 ; 1.064 ; Rise ; clk ; -; mbus_cmd2_i[*] ; clk ; 0.643 ; 0.788 ; Rise ; clk ; -; mbus_cmd2_i[0] ; clk ; 0.594 ; 0.775 ; Rise ; clk ; -; mbus_cmd2_i[1] ; clk ; 0.633 ; 0.735 ; Rise ; clk ; -; mbus_cmd2_i[2] ; clk ; 0.643 ; 0.788 ; Rise ; clk ; -; mbus_cmd3_i[*] ; clk ; 0.687 ; 0.970 ; Rise ; clk ; -; mbus_cmd3_i[0] ; clk ; 0.630 ; 0.950 ; Rise ; clk ; -; mbus_cmd3_i[1] ; clk ; 0.642 ; 0.863 ; Rise ; clk ; -; mbus_cmd3_i[2] ; clk ; 0.687 ; 0.970 ; Rise ; clk ; -+-------------------+------------+-------+-------+------------+-----------------+ - - -+---------------------------------------------------------------------------------+ -; Hold Times ; -+-------------------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-------------------+------------+--------+--------+------------+-----------------+ -; cbus_ack0_i ; clk ; 0.029 ; -0.226 ; Rise ; clk ; -; cbus_ack1_i ; clk ; -0.082 ; -0.297 ; Rise ; clk ; -; cbus_ack2_i ; clk ; -0.228 ; -0.341 ; Rise ; clk ; -; cbus_ack3_i ; clk ; -0.143 ; -0.135 ; Rise ; clk ; -; mbus_addr0_i[*] ; clk ; 0.115 ; -0.176 ; Rise ; clk ; -; mbus_addr0_i[0] ; clk ; -0.162 ; -0.410 ; Rise ; clk ; -; mbus_addr0_i[1] ; clk ; -0.063 ; -0.297 ; Rise ; clk ; -; mbus_addr0_i[2] ; clk ; -0.073 ; -0.299 ; Rise ; clk ; -; mbus_addr0_i[3] ; clk ; -0.071 ; -0.290 ; Rise ; clk ; -; mbus_addr0_i[4] ; clk ; -0.078 ; -0.326 ; Rise ; clk ; -; mbus_addr0_i[5] ; clk ; -0.141 ; -0.368 ; Rise ; clk ; -; mbus_addr0_i[6] ; clk ; -0.162 ; -0.396 ; Rise ; clk ; -; mbus_addr0_i[7] ; clk ; 0.052 ; -0.259 ; Rise ; clk ; -; mbus_addr0_i[8] ; clk ; 0.103 ; -0.217 ; Rise ; clk ; -; mbus_addr0_i[9] ; clk ; -0.041 ; -0.266 ; Rise ; clk ; -; mbus_addr0_i[10] ; clk ; -0.151 ; -0.350 ; Rise ; clk ; -; mbus_addr0_i[11] ; clk ; -0.138 ; -0.357 ; Rise ; clk ; -; mbus_addr0_i[12] ; clk ; 0.010 ; -0.299 ; Rise ; clk ; -; mbus_addr0_i[13] ; clk ; -0.083 ; -0.283 ; Rise ; clk ; -; mbus_addr0_i[14] ; clk ; -0.119 ; -0.353 ; Rise ; clk ; -; mbus_addr0_i[15] ; clk ; 0.086 ; -0.246 ; Rise ; clk ; -; mbus_addr0_i[16] ; clk ; -0.046 ; -0.298 ; Rise ; clk ; -; mbus_addr0_i[17] ; clk ; -0.274 ; -0.322 ; Rise ; clk ; -; mbus_addr0_i[18] ; clk ; -0.087 ; -0.249 ; Rise ; clk ; -; mbus_addr0_i[19] ; clk ; -0.008 ; -0.250 ; Rise ; clk ; -; mbus_addr0_i[20] ; clk ; -0.009 ; -0.240 ; Rise ; clk ; -; mbus_addr0_i[21] ; clk ; 0.063 ; -0.229 ; Rise ; clk ; -; mbus_addr0_i[22] ; clk ; 0.005 ; -0.281 ; Rise ; clk ; -; mbus_addr0_i[23] ; clk ; -0.100 ; -0.316 ; Rise ; clk ; -; mbus_addr0_i[24] ; clk ; -0.188 ; -0.410 ; Rise ; clk ; -; mbus_addr0_i[25] ; clk ; -0.015 ; -0.248 ; Rise ; clk ; -; mbus_addr0_i[26] ; clk ; 0.004 ; -0.280 ; Rise ; clk ; -; mbus_addr0_i[27] ; clk ; -0.045 ; -0.289 ; Rise ; clk ; -; mbus_addr0_i[28] ; clk ; -0.043 ; -0.279 ; Rise ; clk ; -; mbus_addr0_i[29] ; clk ; 0.002 ; -0.299 ; Rise ; clk ; -; mbus_addr0_i[30] ; clk ; 0.115 ; -0.176 ; Rise ; clk ; -; mbus_addr0_i[31] ; clk ; -0.094 ; -0.325 ; Rise ; clk ; -; mbus_addr1_i[*] ; clk ; 0.378 ; 0.110 ; Rise ; clk ; -; mbus_addr1_i[0] ; clk ; -0.067 ; -0.275 ; Rise ; clk ; -; mbus_addr1_i[1] ; clk ; -0.111 ; -0.355 ; Rise ; clk ; -; mbus_addr1_i[2] ; clk ; -0.103 ; -0.355 ; Rise ; clk ; -; mbus_addr1_i[3] ; clk ; -0.116 ; -0.364 ; Rise ; clk ; -; mbus_addr1_i[4] ; clk ; 0.118 ; -0.168 ; Rise ; clk ; -; mbus_addr1_i[5] ; clk ; 0.118 ; -0.198 ; Rise ; clk ; -; mbus_addr1_i[6] ; clk ; -0.136 ; -0.365 ; Rise ; clk ; -; mbus_addr1_i[7] ; clk ; 0.378 ; 0.110 ; Rise ; clk ; -; mbus_addr1_i[8] ; clk ; -0.078 ; -0.312 ; Rise ; clk ; -; mbus_addr1_i[9] ; clk ; 0.035 ; -0.244 ; Rise ; clk ; -; mbus_addr1_i[10] ; clk ; -0.007 ; -0.279 ; Rise ; clk ; -; mbus_addr1_i[11] ; clk ; -0.082 ; -0.269 ; Rise ; clk ; -; mbus_addr1_i[12] ; clk ; 0.055 ; -0.253 ; Rise ; clk ; -; mbus_addr1_i[13] ; clk ; -0.099 ; -0.317 ; Rise ; clk ; -; mbus_addr1_i[14] ; clk ; -0.102 ; -0.294 ; Rise ; clk ; -; mbus_addr1_i[15] ; clk ; -0.081 ; -0.296 ; Rise ; clk ; -; mbus_addr1_i[16] ; clk ; -0.073 ; -0.315 ; Rise ; clk ; -; mbus_addr1_i[17] ; clk ; -0.214 ; -0.318 ; Rise ; clk ; -; mbus_addr1_i[18] ; clk ; -0.199 ; -0.292 ; Rise ; clk ; -; mbus_addr1_i[19] ; clk ; -0.145 ; -0.334 ; Rise ; clk ; -; mbus_addr1_i[20] ; clk ; -0.035 ; -0.279 ; Rise ; clk ; -; mbus_addr1_i[21] ; clk ; -0.204 ; -0.378 ; Rise ; clk ; -; mbus_addr1_i[22] ; clk ; -0.015 ; -0.194 ; Rise ; clk ; -; mbus_addr1_i[23] ; clk ; -0.018 ; -0.308 ; Rise ; clk ; -; mbus_addr1_i[24] ; clk ; -0.056 ; -0.302 ; Rise ; clk ; -; mbus_addr1_i[25] ; clk ; -0.057 ; -0.214 ; Rise ; clk ; -; mbus_addr1_i[26] ; clk ; -0.037 ; -0.356 ; Rise ; clk ; -; mbus_addr1_i[27] ; clk ; 0.119 ; -0.151 ; Rise ; clk ; -; mbus_addr1_i[28] ; clk ; -0.014 ; -0.224 ; Rise ; clk ; -; mbus_addr1_i[29] ; clk ; -0.099 ; -0.282 ; Rise ; clk ; -; mbus_addr1_i[30] ; clk ; 0.050 ; -0.214 ; Rise ; clk ; -; mbus_addr1_i[31] ; clk ; 0.022 ; -0.208 ; Rise ; clk ; -; mbus_addr2_i[*] ; clk ; 0.133 ; -0.176 ; Rise ; clk ; -; mbus_addr2_i[0] ; clk ; -0.070 ; -0.251 ; Rise ; clk ; -; mbus_addr2_i[1] ; clk ; -0.134 ; -0.352 ; Rise ; clk ; -; mbus_addr2_i[2] ; clk ; -0.032 ; -0.283 ; Rise ; clk ; -; mbus_addr2_i[3] ; clk ; 0.081 ; -0.248 ; Rise ; clk ; -; mbus_addr2_i[4] ; clk ; 0.085 ; -0.285 ; Rise ; clk ; -; mbus_addr2_i[5] ; clk ; -0.008 ; -0.317 ; Rise ; clk ; -; mbus_addr2_i[6] ; clk ; -0.021 ; -0.286 ; Rise ; clk ; -; mbus_addr2_i[7] ; clk ; -0.045 ; -0.176 ; Rise ; clk ; -; mbus_addr2_i[8] ; clk ; -0.038 ; -0.315 ; Rise ; clk ; -; mbus_addr2_i[9] ; clk ; 0.006 ; -0.290 ; Rise ; clk ; -; mbus_addr2_i[10] ; clk ; -0.118 ; -0.373 ; Rise ; clk ; -; mbus_addr2_i[11] ; clk ; -0.133 ; -0.383 ; Rise ; clk ; -; mbus_addr2_i[12] ; clk ; 0.064 ; -0.304 ; Rise ; clk ; -; mbus_addr2_i[13] ; clk ; -0.082 ; -0.399 ; Rise ; clk ; -; mbus_addr2_i[14] ; clk ; -0.046 ; -0.307 ; Rise ; clk ; -; mbus_addr2_i[15] ; clk ; -0.094 ; -0.369 ; Rise ; clk ; -; mbus_addr2_i[16] ; clk ; -0.030 ; -0.302 ; Rise ; clk ; -; mbus_addr2_i[17] ; clk ; 0.002 ; -0.335 ; Rise ; clk ; -; mbus_addr2_i[18] ; clk ; -0.037 ; -0.312 ; Rise ; clk ; -; mbus_addr2_i[19] ; clk ; -0.131 ; -0.245 ; Rise ; clk ; -; mbus_addr2_i[20] ; clk ; -0.084 ; -0.231 ; Rise ; clk ; -; mbus_addr2_i[21] ; clk ; -0.126 ; -0.365 ; Rise ; clk ; -; mbus_addr2_i[22] ; clk ; 0.089 ; -0.211 ; Rise ; clk ; -; mbus_addr2_i[23] ; clk ; -0.154 ; -0.433 ; Rise ; clk ; -; mbus_addr2_i[24] ; clk ; -0.058 ; -0.305 ; Rise ; clk ; -; mbus_addr2_i[25] ; clk ; 0.133 ; -0.221 ; Rise ; clk ; -; mbus_addr2_i[26] ; clk ; -0.092 ; -0.384 ; Rise ; clk ; -; mbus_addr2_i[27] ; clk ; -0.215 ; -0.434 ; Rise ; clk ; -; mbus_addr2_i[28] ; clk ; -0.058 ; -0.323 ; Rise ; clk ; -; mbus_addr2_i[29] ; clk ; -0.118 ; -0.372 ; Rise ; clk ; -; mbus_addr2_i[30] ; clk ; -0.066 ; -0.273 ; Rise ; clk ; -; mbus_addr2_i[31] ; clk ; -0.236 ; -0.518 ; Rise ; clk ; -; mbus_addr3_i[*] ; clk ; 0.046 ; -0.136 ; Rise ; clk ; -; mbus_addr3_i[0] ; clk ; -0.143 ; -0.423 ; Rise ; clk ; -; mbus_addr3_i[1] ; clk ; -0.035 ; -0.279 ; Rise ; clk ; -; mbus_addr3_i[2] ; clk ; -0.108 ; -0.359 ; Rise ; clk ; -; mbus_addr3_i[3] ; clk ; -0.194 ; -0.418 ; Rise ; clk ; -; mbus_addr3_i[4] ; clk ; -0.223 ; -0.475 ; Rise ; clk ; -; mbus_addr3_i[5] ; clk ; 0.041 ; -0.254 ; Rise ; clk ; -; mbus_addr3_i[6] ; clk ; -0.134 ; -0.378 ; Rise ; clk ; -; mbus_addr3_i[7] ; clk ; -0.016 ; -0.225 ; Rise ; clk ; -; mbus_addr3_i[8] ; clk ; -0.130 ; -0.385 ; Rise ; clk ; -; mbus_addr3_i[9] ; clk ; -0.071 ; -0.298 ; Rise ; clk ; -; mbus_addr3_i[10] ; clk ; -0.066 ; -0.293 ; Rise ; clk ; -; mbus_addr3_i[11] ; clk ; 0.044 ; -0.136 ; Rise ; clk ; -; mbus_addr3_i[12] ; clk ; 0.046 ; -0.267 ; Rise ; clk ; -; mbus_addr3_i[13] ; clk ; -0.116 ; -0.339 ; Rise ; clk ; -; mbus_addr3_i[14] ; clk ; -0.027 ; -0.302 ; Rise ; clk ; -; mbus_addr3_i[15] ; clk ; -0.085 ; -0.304 ; Rise ; clk ; -; mbus_addr3_i[16] ; clk ; -0.139 ; -0.302 ; Rise ; clk ; -; mbus_addr3_i[17] ; clk ; -0.128 ; -0.377 ; Rise ; clk ; -; mbus_addr3_i[18] ; clk ; -0.133 ; -0.367 ; Rise ; clk ; -; mbus_addr3_i[19] ; clk ; -0.018 ; -0.321 ; Rise ; clk ; -; mbus_addr3_i[20] ; clk ; -0.043 ; -0.282 ; Rise ; clk ; -; mbus_addr3_i[21] ; clk ; -0.108 ; -0.294 ; Rise ; clk ; -; mbus_addr3_i[22] ; clk ; -0.145 ; -0.342 ; Rise ; clk ; -; mbus_addr3_i[23] ; clk ; 0.003 ; -0.309 ; Rise ; clk ; -; mbus_addr3_i[24] ; clk ; -0.123 ; -0.435 ; Rise ; clk ; -; mbus_addr3_i[25] ; clk ; -0.083 ; -0.371 ; Rise ; clk ; -; mbus_addr3_i[26] ; clk ; -0.083 ; -0.419 ; Rise ; clk ; -; mbus_addr3_i[27] ; clk ; -0.092 ; -0.260 ; Rise ; clk ; -; mbus_addr3_i[28] ; clk ; -0.120 ; -0.373 ; Rise ; clk ; -; mbus_addr3_i[29] ; clk ; -0.067 ; -0.245 ; Rise ; clk ; -; mbus_addr3_i[30] ; clk ; -0.080 ; -0.391 ; Rise ; clk ; -; mbus_addr3_i[31] ; clk ; -0.101 ; -0.428 ; Rise ; clk ; -; mbus_cmd0_i[*] ; clk ; 0.071 ; -0.071 ; Rise ; clk ; -; mbus_cmd0_i[0] ; clk ; 0.066 ; -0.096 ; Rise ; clk ; -; mbus_cmd0_i[1] ; clk ; -0.134 ; -0.300 ; Rise ; clk ; -; mbus_cmd0_i[2] ; clk ; 0.071 ; -0.071 ; Rise ; clk ; -; mbus_cmd1_i[*] ; clk ; 0.097 ; -0.077 ; Rise ; clk ; -; mbus_cmd1_i[0] ; clk ; -0.014 ; -0.303 ; Rise ; clk ; -; mbus_cmd1_i[1] ; clk ; 0.097 ; -0.077 ; Rise ; clk ; -; mbus_cmd1_i[2] ; clk ; 0.042 ; -0.246 ; Rise ; clk ; -; mbus_cmd2_i[*] ; clk ; -0.005 ; -0.130 ; Rise ; clk ; -; mbus_cmd2_i[0] ; clk ; -0.051 ; -0.186 ; Rise ; clk ; -; mbus_cmd2_i[1] ; clk ; -0.005 ; -0.130 ; Rise ; clk ; -; mbus_cmd2_i[2] ; clk ; -0.044 ; -0.211 ; Rise ; clk ; -; mbus_cmd3_i[*] ; clk ; 0.126 ; -0.137 ; Rise ; clk ; -; mbus_cmd3_i[0] ; clk ; 0.126 ; -0.137 ; Rise ; clk ; -; mbus_cmd3_i[1] ; clk ; -0.026 ; -0.262 ; Rise ; clk ; -; mbus_cmd3_i[2] ; clk ; -0.153 ; -0.412 ; Rise ; clk ; -+-------------------+------------+--------+--------+------------+-----------------+ - - -+------------------------------------------------------------------------------+ -; Clock to Output Times ; -+------------------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+------------------+------------+-------+-------+------------+-----------------+ -; cbus_addr_o[*] ; clk ; 6.105 ; 6.062 ; Rise ; clk ; -; cbus_addr_o[0] ; clk ; 6.025 ; 5.982 ; Rise ; clk ; -; cbus_addr_o[1] ; clk ; 6.050 ; 6.007 ; Rise ; clk ; -; cbus_addr_o[2] ; clk ; 6.002 ; 5.959 ; Rise ; clk ; -; cbus_addr_o[3] ; clk ; 5.992 ; 5.949 ; Rise ; clk ; -; cbus_addr_o[4] ; clk ; 6.014 ; 5.971 ; Rise ; clk ; -; cbus_addr_o[5] ; clk ; 5.986 ; 5.943 ; Rise ; clk ; -; cbus_addr_o[6] ; clk ; 6.024 ; 5.981 ; Rise ; clk ; -; cbus_addr_o[7] ; clk ; 6.071 ; 6.028 ; Rise ; clk ; -; cbus_addr_o[8] ; clk ; 6.037 ; 5.994 ; Rise ; clk ; -; cbus_addr_o[9] ; clk ; 6.002 ; 5.959 ; Rise ; clk ; -; cbus_addr_o[10] ; clk ; 6.060 ; 6.017 ; Rise ; clk ; -; cbus_addr_o[11] ; clk ; 5.995 ; 5.952 ; Rise ; clk ; -; cbus_addr_o[12] ; clk ; 6.105 ; 6.062 ; Rise ; clk ; -; cbus_addr_o[13] ; clk ; 5.987 ; 5.944 ; Rise ; clk ; -; cbus_addr_o[14] ; clk ; 6.046 ; 6.003 ; Rise ; clk ; -; cbus_addr_o[15] ; clk ; 6.055 ; 6.012 ; Rise ; clk ; -; cbus_addr_o[16] ; clk ; 6.058 ; 6.015 ; Rise ; clk ; -; cbus_addr_o[17] ; clk ; 6.003 ; 5.960 ; Rise ; clk ; -; cbus_addr_o[18] ; clk ; 6.004 ; 5.961 ; Rise ; clk ; -; cbus_addr_o[19] ; clk ; 6.005 ; 5.962 ; Rise ; clk ; -; cbus_addr_o[20] ; clk ; 6.012 ; 5.969 ; Rise ; clk ; -; cbus_addr_o[21] ; clk ; 5.994 ; 5.951 ; Rise ; clk ; -; cbus_addr_o[22] ; clk ; 6.012 ; 5.969 ; Rise ; clk ; -; cbus_addr_o[23] ; clk ; 5.999 ; 5.956 ; Rise ; clk ; -; cbus_addr_o[24] ; clk ; 6.006 ; 5.963 ; Rise ; clk ; -; cbus_addr_o[25] ; clk ; 5.993 ; 5.957 ; Rise ; clk ; -; cbus_addr_o[26] ; clk ; 6.004 ; 5.961 ; Rise ; clk ; -; cbus_addr_o[27] ; clk ; 6.033 ; 5.990 ; Rise ; clk ; -; cbus_addr_o[28] ; clk ; 6.005 ; 5.962 ; Rise ; clk ; -; cbus_addr_o[29] ; clk ; 6.027 ; 5.984 ; Rise ; clk ; -; cbus_addr_o[30] ; clk ; 6.059 ; 6.016 ; Rise ; clk ; -; cbus_addr_o[31] ; clk ; 5.995 ; 5.952 ; Rise ; clk ; -; cbus_cmd0_o[*] ; clk ; 9.110 ; 9.097 ; Rise ; clk ; -; cbus_cmd0_o[0] ; clk ; 9.110 ; 8.961 ; Rise ; clk ; -; cbus_cmd0_o[1] ; clk ; 9.095 ; 9.097 ; Rise ; clk ; -; cbus_cmd0_o[2] ; clk ; 8.955 ; 9.012 ; Rise ; clk ; -; cbus_cmd1_o[*] ; clk ; 9.220 ; 9.075 ; Rise ; clk ; -; cbus_cmd1_o[0] ; clk ; 9.220 ; 9.075 ; Rise ; clk ; -; cbus_cmd1_o[1] ; clk ; 9.105 ; 9.047 ; Rise ; clk ; -; cbus_cmd1_o[2] ; clk ; 8.844 ; 8.748 ; Rise ; clk ; -; cbus_cmd2_o[*] ; clk ; 9.214 ; 9.167 ; Rise ; clk ; -; cbus_cmd2_o[0] ; clk ; 8.900 ; 8.767 ; Rise ; clk ; -; cbus_cmd2_o[1] ; clk ; 9.119 ; 9.092 ; Rise ; clk ; -; cbus_cmd2_o[2] ; clk ; 9.214 ; 9.167 ; Rise ; clk ; -; cbus_cmd3_o[*] ; clk ; 8.881 ; 8.977 ; Rise ; clk ; -; cbus_cmd3_o[0] ; clk ; 8.823 ; 8.697 ; Rise ; clk ; -; cbus_cmd3_o[1] ; clk ; 8.786 ; 8.716 ; Rise ; clk ; -; cbus_cmd3_o[2] ; clk ; 8.881 ; 8.977 ; Rise ; clk ; -; mbus_ack0_o ; clk ; 6.000 ; 5.957 ; Rise ; clk ; -; mbus_ack1_o ; clk ; 6.008 ; 5.965 ; Rise ; clk ; -; mbus_ack2_o ; clk ; 6.040 ; 5.997 ; Rise ; clk ; -; mbus_ack3_o ; clk ; 6.047 ; 6.004 ; Rise ; clk ; -+------------------+------------+-------+-------+------------+-----------------+ - - -+------------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+------------------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+------------------+------------+-------+-------+------------+-----------------+ -; cbus_addr_o[*] ; clk ; 5.861 ; 5.819 ; Rise ; clk ; -; cbus_addr_o[0] ; clk ; 5.900 ; 5.858 ; Rise ; clk ; -; cbus_addr_o[1] ; clk ; 5.926 ; 5.884 ; Rise ; clk ; -; cbus_addr_o[2] ; clk ; 5.878 ; 5.836 ; Rise ; clk ; -; cbus_addr_o[3] ; clk ; 5.868 ; 5.826 ; Rise ; clk ; -; cbus_addr_o[4] ; clk ; 5.890 ; 5.848 ; Rise ; clk ; -; cbus_addr_o[5] ; clk ; 5.861 ; 5.819 ; Rise ; clk ; -; cbus_addr_o[6] ; clk ; 5.900 ; 5.858 ; Rise ; clk ; -; cbus_addr_o[7] ; clk ; 5.948 ; 5.906 ; Rise ; clk ; -; cbus_addr_o[8] ; clk ; 5.914 ; 5.872 ; Rise ; clk ; -; cbus_addr_o[9] ; clk ; 5.878 ; 5.836 ; Rise ; clk ; -; cbus_addr_o[10] ; clk ; 5.936 ; 5.894 ; Rise ; clk ; -; cbus_addr_o[11] ; clk ; 5.871 ; 5.829 ; Rise ; clk ; -; cbus_addr_o[12] ; clk ; 5.981 ; 5.939 ; Rise ; clk ; -; cbus_addr_o[13] ; clk ; 5.863 ; 5.821 ; Rise ; clk ; -; cbus_addr_o[14] ; clk ; 5.923 ; 5.881 ; Rise ; clk ; -; cbus_addr_o[15] ; clk ; 5.933 ; 5.891 ; Rise ; clk ; -; cbus_addr_o[16] ; clk ; 5.935 ; 5.893 ; Rise ; clk ; -; cbus_addr_o[17] ; clk ; 5.878 ; 5.836 ; Rise ; clk ; -; cbus_addr_o[18] ; clk ; 5.880 ; 5.838 ; Rise ; clk ; -; cbus_addr_o[19] ; clk ; 5.881 ; 5.839 ; Rise ; clk ; -; cbus_addr_o[20] ; clk ; 5.888 ; 5.846 ; Rise ; clk ; -; cbus_addr_o[21] ; clk ; 5.870 ; 5.828 ; Rise ; clk ; -; cbus_addr_o[22] ; clk ; 5.887 ; 5.845 ; Rise ; clk ; -; cbus_addr_o[23] ; clk ; 5.875 ; 5.833 ; Rise ; clk ; -; cbus_addr_o[24] ; clk ; 5.882 ; 5.840 ; Rise ; clk ; -; cbus_addr_o[25] ; clk ; 5.869 ; 5.834 ; Rise ; clk ; -; cbus_addr_o[26] ; clk ; 5.880 ; 5.838 ; Rise ; clk ; -; cbus_addr_o[27] ; clk ; 5.908 ; 5.866 ; Rise ; clk ; -; cbus_addr_o[28] ; clk ; 5.880 ; 5.838 ; Rise ; clk ; -; cbus_addr_o[29] ; clk ; 5.903 ; 5.861 ; Rise ; clk ; -; cbus_addr_o[30] ; clk ; 5.935 ; 5.893 ; Rise ; clk ; -; cbus_addr_o[31] ; clk ; 5.871 ; 5.829 ; Rise ; clk ; -; cbus_cmd0_o[*] ; clk ; 7.909 ; 7.938 ; Rise ; clk ; -; cbus_cmd0_o[0] ; clk ; 8.048 ; 8.062 ; Rise ; clk ; -; cbus_cmd0_o[1] ; clk ; 8.047 ; 8.132 ; Rise ; clk ; -; cbus_cmd0_o[2] ; clk ; 7.909 ; 7.938 ; Rise ; clk ; -; cbus_cmd1_o[*] ; clk ; 7.754 ; 7.673 ; Rise ; clk ; -; cbus_cmd1_o[0] ; clk ; 8.327 ; 8.341 ; Rise ; clk ; -; cbus_cmd1_o[1] ; clk ; 8.157 ; 8.168 ; Rise ; clk ; -; cbus_cmd1_o[2] ; clk ; 7.754 ; 7.673 ; Rise ; clk ; -; cbus_cmd2_o[*] ; clk ; 8.073 ; 8.110 ; Rise ; clk ; -; cbus_cmd2_o[0] ; clk ; 8.073 ; 8.110 ; Rise ; clk ; -; cbus_cmd2_o[1] ; clk ; 8.265 ; 8.350 ; Rise ; clk ; -; cbus_cmd2_o[2] ; clk ; 8.201 ; 8.117 ; Rise ; clk ; -; cbus_cmd3_o[*] ; clk ; 8.001 ; 7.986 ; Rise ; clk ; -; cbus_cmd3_o[0] ; clk ; 8.164 ; 8.155 ; Rise ; clk ; -; cbus_cmd3_o[1] ; clk ; 8.001 ; 7.986 ; Rise ; clk ; -; cbus_cmd3_o[2] ; clk ; 8.011 ; 8.062 ; Rise ; clk ; -; mbus_ack0_o ; clk ; 5.876 ; 5.834 ; Rise ; clk ; -; mbus_ack1_o ; clk ; 5.882 ; 5.840 ; Rise ; clk ; -; mbus_ack2_o ; clk ; 5.917 ; 5.875 ; Rise ; clk ; -; mbus_ack3_o ; clk ; 5.923 ; 5.881 ; Rise ; clk ; -+------------------+------------+-------+-------+------------+-----------------+ - - ----------------------------------------------- -; Slow 1200mV 85C Model Metastability Report ; ----------------------------------------------- -No synchronizer chains to report. - - -+--------------------------------------------------+ -; Slow 1200mV 0C Model Fmax Summary ; -+------------+-----------------+------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+------------+-----------------+------------+------+ -; 119.23 MHz ; 119.23 MHz ; clk ; ; -+------------+-----------------+------------+------+ -This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. - - -+------------------------------------+ -; Slow 1200mV 0C Model Setup Summary ; -+-------+--------+-------------------+ -; Clock ; Slack ; End Point TNS ; -+-------+--------+-------------------+ -; clk ; -7.387 ; -2375.975 ; -+-------+--------+-------------------+ - - -+-----------------------------------+ -; Slow 1200mV 0C Model Hold Summary ; -+-------+--------+------------------+ -; Clock ; Slack ; End Point TNS ; -+-------+--------+------------------+ -; clk ; -0.237 ; -0.279 ; -+-------+--------+------------------+ - - ------------------------------------------ -; Slow 1200mV 0C Model Recovery Summary ; ------------------------------------------ -No paths to report. - - ----------------------------------------- -; Slow 1200mV 0C Model Removal Summary ; ----------------------------------------- -No paths to report. - - -+--------------------------------------------------+ -; Slow 1200mV 0C Model Minimum Pulse Width Summary ; -+-------+--------+---------------------------------+ -; Clock ; Slack ; End Point TNS ; -+-------+--------+---------------------------------+ -; clk ; -3.000 ; -643.000 ; -+-------+--------+---------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Setup: 'clk' ; -+--------+------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -7.387 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 5.418 ; -; -7.387 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 5.418 ; -; -7.349 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 5.380 ; -; -7.349 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 5.380 ; -; -7.324 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -2.848 ; 5.356 ; -; -7.314 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -2.848 ; 5.346 ; -; -7.308 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 5.339 ; -; -7.308 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 5.339 ; -; -7.305 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 5.336 ; -; -7.305 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 5.336 ; -; -7.294 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 5.325 ; -; -7.294 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 5.325 ; -; -7.274 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -2.848 ; 5.306 ; -; -7.261 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 5.292 ; -; -7.258 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 5.289 ; -; -7.256 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 5.287 ; -; -7.241 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 5.272 ; -; -7.241 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 5.272 ; -; -7.240 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 5.271 ; -; -7.220 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 5.251 ; -; -7.208 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 5.239 ; -; -7.190 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 5.221 ; -; -7.179 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 5.210 ; -; -7.176 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 5.207 ; -; -7.170 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[2] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 5.201 ; -; -7.170 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 5.201 ; -; -7.165 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 5.196 ; -; -7.141 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 5.172 ; -; -7.141 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[1] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -2.848 ; 5.173 ; -; -7.137 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 5.168 ; -; -7.116 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[1] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -2.848 ; 5.148 ; -; -7.113 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[0] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -2.848 ; 5.145 ; -; -7.112 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 5.143 ; -; -7.103 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 5.134 ; -; -7.102 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 5.133 ; -; -7.102 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 5.133 ; -; -7.099 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 5.130 ; -; -7.098 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 5.129 ; -; -7.096 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 5.127 ; -; -7.096 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 5.127 ; -; -7.065 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 5.096 ; -; -7.065 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 5.096 ; -; -7.064 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 5.095 ; -; -7.064 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 5.095 ; -; -7.062 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 5.093 ; -; -7.060 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -2.848 ; 5.092 ; -; -7.059 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 5.090 ; -; -7.048 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 5.079 ; -; -7.032 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -2.848 ; 5.064 ; -; -7.027 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 5.058 ; -; -7.027 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 5.058 ; -; -7.019 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 5.050 ; -; -6.998 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 5.029 ; -; -6.998 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 5.029 ; -; -6.995 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 5.026 ; -; -6.988 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 5.019 ; -; -6.988 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 5.019 ; -; -6.973 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 5.004 ; -; -6.968 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[2] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 4.999 ; -; -6.964 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 4.995 ; -; -6.949 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 4.980 ; -; -6.942 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 4.973 ; -; -6.936 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 4.967 ; -; -6.935 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 4.966 ; -; -6.932 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[2] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 4.963 ; -; -6.928 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 4.959 ; -; -6.921 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 4.952 ; -; -6.915 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 4.946 ; -; -6.908 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -2.848 ; 4.940 ; -; -6.906 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 4.937 ; -; -6.898 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 4.929 ; -; -6.869 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 4.900 ; -; -6.859 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 4.890 ; -; -6.856 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 4.887 ; -; -6.855 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 4.886 ; -; -6.840 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -2.848 ; 4.872 ; -; -6.828 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[3] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -2.848 ; 4.860 ; -; -6.826 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 4.857 ; -; -6.819 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 4.850 ; -; -6.818 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 4.849 ; -; -6.816 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 4.847 ; -; -6.795 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -2.848 ; 4.827 ; -; -6.783 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 4.814 ; -; -6.781 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -2.849 ; 4.812 ; -; -6.762 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[3] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -2.848 ; 4.794 ; -; -6.752 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 4.783 ; -; -6.747 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -2.849 ; 4.778 ; -; -6.736 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -2.848 ; 4.768 ; -; -6.736 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -2.849 ; 4.767 ; -; -6.723 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -2.848 ; 4.755 ; -; -6.659 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[0] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -2.848 ; 4.691 ; -; -6.652 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -2.848 ; 4.684 ; -; -6.599 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[3] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -2.848 ; 4.631 ; -; -6.504 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[0] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -2.848 ; 4.536 ; -; -6.487 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[1] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -2.848 ; 4.519 ; -; -6.343 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -2.848 ; 4.375 ; -; -5.625 ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|status_empty ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[11] ; clk ; clk ; 1.000 ; -0.115 ; 6.413 ; -; -5.610 ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|status_empty ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[11] ; clk ; clk ; 1.000 ; -0.115 ; 6.398 ; -; -5.578 ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|status_empty ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[27] ; clk ; clk ; 1.000 ; -0.113 ; 6.368 ; -; -5.574 ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|status_empty ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[33] ; clk ; clk ; 1.000 ; -0.111 ; 6.366 ; -+--------+------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Hold: 'clk' ; -+--------+------------------+--------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+------------------+--------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -0.237 ; mbus_addr1_i[7] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][16] ; clk ; clk ; 0.000 ; 2.858 ; 2.665 ; -; -0.028 ; mbus_addr2_i[25] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][34] ; clk ; clk ; 0.000 ; 2.842 ; 2.858 ; -; -0.014 ; mbus_cmd3_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[7] ; clk ; clk ; 0.000 ; 2.848 ; 2.878 ; -; 0.003 ; mbus_addr0_i[30] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][39] ; clk ; clk ; 0.000 ; 2.864 ; 2.911 ; -; 0.003 ; mbus_addr0_i[30] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][39] ; clk ; clk ; 0.000 ; 2.864 ; 2.911 ; -; 0.021 ; mbus_addr1_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][14] ; clk ; clk ; 0.000 ; 2.836 ; 2.901 ; -; 0.022 ; mbus_addr1_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][14] ; clk ; clk ; 0.000 ; 2.836 ; 2.902 ; -; 0.029 ; mbus_addr1_i[27] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][36] ; clk ; clk ; 0.000 ; 2.828 ; 2.901 ; -; 0.032 ; mbus_addr0_i[8] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][17] ; clk ; clk ; 0.000 ; 2.797 ; 2.873 ; -; 0.033 ; mbus_addr1_i[4] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][13] ; clk ; clk ; 0.000 ; 2.828 ; 2.905 ; -; 0.036 ; mbus_addr1_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][21] ; clk ; clk ; 0.000 ; 2.828 ; 2.908 ; -; 0.042 ; mbus_cmd0_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[0]~_Duplicate_1 ; clk ; clk ; 0.000 ; 2.817 ; 2.903 ; -; 0.043 ; mbus_cmd0_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[0] ; clk ; clk ; 0.000 ; 2.817 ; 2.904 ; -; 0.046 ; mbus_addr2_i[4] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][13] ; clk ; clk ; 0.000 ; 2.818 ; 2.908 ; -; 0.050 ; mbus_addr1_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[21] ; clk ; clk ; 0.000 ; 2.824 ; 2.918 ; -; 0.050 ; mbus_cmd0_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[0]~_Duplicate_1 ; clk ; clk ; 0.000 ; 2.817 ; 2.911 ; -; 0.056 ; mbus_addr2_i[3] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][12] ; clk ; clk ; 0.000 ; 2.820 ; 2.920 ; -; 0.059 ; mbus_addr0_i[15] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][24] ; clk ; clk ; 0.000 ; 2.792 ; 2.895 ; -; 0.060 ; mbus_addr2_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][31] ; clk ; clk ; 0.000 ; 2.862 ; 2.966 ; -; 0.064 ; mbus_addr2_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][21] ; clk ; clk ; 0.000 ; 2.828 ; 2.936 ; -; 0.066 ; mbus_cmd1_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[1]~_Duplicate_1 ; clk ; clk ; 0.000 ; 2.872 ; 2.982 ; -; 0.069 ; mbus_addr1_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][21] ; clk ; clk ; 0.000 ; 2.829 ; 2.942 ; -; 0.073 ; mbus_addr0_i[21] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][30] ; clk ; clk ; 0.000 ; 2.821 ; 2.938 ; -; 0.074 ; mbus_addr0_i[7] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][16] ; clk ; clk ; 0.000 ; 2.871 ; 2.989 ; -; 0.085 ; mbus_cmd1_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[3] ; clk ; clk ; 0.000 ; 2.872 ; 3.001 ; -; 0.091 ; mbus_cmd0_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[1] ; clk ; clk ; 0.000 ; 2.817 ; 2.952 ; -; 0.093 ; mbus_addr2_i[3] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[12] ; clk ; clk ; 0.000 ; 2.820 ; 2.957 ; -; 0.095 ; mbus_addr3_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][21] ; clk ; clk ; 0.000 ; 2.804 ; 2.943 ; -; 0.098 ; mbus_addr1_i[10] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][19] ; clk ; clk ; 0.000 ; 2.820 ; 2.962 ; -; 0.099 ; mbus_addr1_i[10] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][19] ; clk ; clk ; 0.000 ; 2.842 ; 2.985 ; -; 0.105 ; mbus_addr1_i[30] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][39] ; clk ; clk ; 0.000 ; 2.814 ; 2.963 ; -; 0.109 ; mbus_addr3_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][14] ; clk ; clk ; 0.000 ; 2.803 ; 2.956 ; -; 0.109 ; mbus_addr1_i[9] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][18] ; clk ; clk ; 0.000 ; 2.829 ; 2.982 ; -; 0.111 ; mbus_addr2_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][31] ; clk ; clk ; 0.000 ; 2.834 ; 2.989 ; -; 0.114 ; mbus_addr2_i[4] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][13] ; clk ; clk ; 0.000 ; 2.820 ; 2.978 ; -; 0.117 ; mbus_addr0_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][31] ; clk ; clk ; 0.000 ; 2.797 ; 2.958 ; -; 0.117 ; mbus_addr1_i[30] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][39] ; clk ; clk ; 0.000 ; 2.815 ; 2.976 ; -; 0.119 ; mbus_addr2_i[3] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][12] ; clk ; clk ; 0.000 ; 2.818 ; 2.981 ; -; 0.121 ; mbus_addr0_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][21] ; clk ; clk ; 0.000 ; 2.794 ; 2.959 ; -; 0.122 ; mbus_addr0_i[8] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][17] ; clk ; clk ; 0.000 ; 2.821 ; 2.987 ; -; 0.122 ; mbus_addr2_i[9] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][18] ; clk ; clk ; 0.000 ; 2.802 ; 2.968 ; -; 0.124 ; mbus_addr0_i[29] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][38] ; clk ; clk ; 0.000 ; 2.803 ; 2.971 ; -; 0.126 ; mbus_addr2_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][14] ; clk ; clk ; 0.000 ; 2.838 ; 3.008 ; -; 0.129 ; mbus_addr2_i[25] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][34] ; clk ; clk ; 0.000 ; 2.835 ; 3.008 ; -; 0.130 ; mbus_addr3_i[23] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][32] ; clk ; clk ; 0.000 ; 2.786 ; 2.960 ; -; 0.130 ; mbus_addr2_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][14] ; clk ; clk ; 0.000 ; 2.822 ; 2.996 ; -; 0.131 ; mbus_addr1_i[10] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[19] ; clk ; clk ; 0.000 ; 2.820 ; 2.995 ; -; 0.133 ; mbus_cmd1_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[2] ; clk ; clk ; 0.000 ; 2.872 ; 3.049 ; -; 0.136 ; mbus_addr3_i[11] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][20] ; clk ; clk ; 0.000 ; 2.828 ; 3.008 ; -; 0.136 ; mbus_addr2_i[17] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][26] ; clk ; clk ; 0.000 ; 2.829 ; 3.009 ; -; 0.137 ; cbus_ack0_i ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; clk ; clk ; 0.000 ; 2.848 ; 3.029 ; -; 0.140 ; mbus_addr0_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][31] ; clk ; clk ; 0.000 ; 2.798 ; 2.982 ; -; 0.141 ; mbus_addr1_i[23] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][32] ; clk ; clk ; 0.000 ; 2.832 ; 3.017 ; -; 0.142 ; mbus_addr0_i[21] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][30] ; clk ; clk ; 0.000 ; 2.819 ; 3.005 ; -; 0.143 ; mbus_cmd1_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[2] ; clk ; clk ; 0.000 ; 2.872 ; 3.059 ; -; 0.146 ; mbus_addr2_i[9] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][18] ; clk ; clk ; 0.000 ; 2.799 ; 2.989 ; -; 0.147 ; mbus_addr3_i[14] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][23] ; clk ; clk ; 0.000 ; 2.820 ; 3.011 ; -; 0.147 ; mbus_addr3_i[19] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][28] ; clk ; clk ; 0.000 ; 2.783 ; 2.974 ; -; 0.147 ; mbus_addr2_i[4] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[13] ; clk ; clk ; 0.000 ; 2.820 ; 3.011 ; -; 0.150 ; mbus_addr2_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][21] ; clk ; clk ; 0.000 ; 2.802 ; 2.996 ; -; 0.150 ; mbus_addr1_i[23] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][32] ; clk ; clk ; 0.000 ; 2.836 ; 3.030 ; -; 0.151 ; mbus_addr0_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[31] ; clk ; clk ; 0.000 ; 2.797 ; 2.992 ; -; 0.151 ; mbus_addr0_i[29] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][38] ; clk ; clk ; 0.000 ; 2.821 ; 3.016 ; -; 0.154 ; mbus_addr0_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][21] ; clk ; clk ; 0.000 ; 2.793 ; 2.991 ; -; 0.155 ; mbus_addr2_i[9] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[18] ; clk ; clk ; 0.000 ; 2.802 ; 3.001 ; -; 0.156 ; mbus_addr1_i[9] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][18] ; clk ; clk ; 0.000 ; 2.833 ; 3.033 ; -; 0.158 ; mbus_cmd3_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[7] ; clk ; clk ; 0.000 ; 2.848 ; 3.050 ; -; 0.159 ; mbus_addr1_i[26] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][35] ; clk ; clk ; 0.000 ; 2.824 ; 3.027 ; -; 0.160 ; mbus_addr1_i[31] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][40] ; clk ; clk ; 0.000 ; 2.828 ; 3.032 ; -; 0.160 ; mbus_addr2_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[14] ; clk ; clk ; 0.000 ; 2.838 ; 3.042 ; -; 0.160 ; mbus_cmd2_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[4] ; clk ; clk ; 0.000 ; 2.841 ; 3.045 ; -; 0.164 ; mbus_cmd3_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[6] ; clk ; clk ; 0.000 ; 2.848 ; 3.056 ; -; 0.166 ; mbus_addr2_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[31] ; clk ; clk ; 0.000 ; 2.862 ; 3.072 ; -; 0.166 ; mbus_addr2_i[25] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[34] ; clk ; clk ; 0.000 ; 2.835 ; 3.045 ; -; 0.169 ; mbus_addr0_i[19] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][28] ; clk ; clk ; 0.000 ; 2.821 ; 3.034 ; -; 0.171 ; mbus_addr2_i[17] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][26] ; clk ; clk ; 0.000 ; 2.809 ; 3.024 ; -; 0.172 ; mbus_addr1_i[27] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][36] ; clk ; clk ; 0.000 ; 2.820 ; 3.036 ; -; 0.172 ; mbus_cmd1_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[3] ; clk ; clk ; 0.000 ; 2.872 ; 3.088 ; -; 0.172 ; mbus_addr2_i[6] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][15] ; clk ; clk ; 0.000 ; 2.835 ; 3.051 ; -; 0.173 ; mbus_addr1_i[7] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][16] ; clk ; clk ; 0.000 ; 2.835 ; 3.052 ; -; 0.174 ; mbus_addr0_i[26] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][35] ; clk ; clk ; 0.000 ; 2.792 ; 3.010 ; -; 0.174 ; mbus_cmd1_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[1] ; clk ; clk ; 0.000 ; 2.830 ; 2.993 ; -; 0.174 ; mbus_addr2_i[8] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][17] ; clk ; clk ; 0.000 ; 2.802 ; 3.020 ; -; 0.174 ; mbus_addr2_i[8] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][17] ; clk ; clk ; 0.000 ; 2.799 ; 3.017 ; -; 0.174 ; mbus_addr1_i[23] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[32] ; clk ; clk ; 0.000 ; 2.832 ; 3.050 ; -; 0.175 ; mbus_addr1_i[28] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][37] ; clk ; clk ; 0.000 ; 2.814 ; 3.033 ; -; 0.176 ; mbus_addr0_i[29] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[38] ; clk ; clk ; 0.000 ; 2.816 ; 3.036 ; -; 0.177 ; mbus_addr2_i[18] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][27] ; clk ; clk ; 0.000 ; 2.829 ; 3.050 ; -; 0.178 ; mbus_addr0_i[20] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][29] ; clk ; clk ; 0.000 ; 2.819 ; 3.041 ; -; 0.179 ; mbus_addr0_i[21] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[30] ; clk ; clk ; 0.000 ; 2.819 ; 3.042 ; -; 0.184 ; mbus_cmd2_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[4] ; clk ; clk ; 0.000 ; 2.841 ; 3.069 ; -; 0.185 ; mbus_addr3_i[7] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][16] ; clk ; clk ; 0.000 ; 2.853 ; 3.082 ; -; 0.185 ; mbus_addr0_i[25] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][34] ; clk ; clk ; 0.000 ; 2.804 ; 3.033 ; -; 0.186 ; mbus_addr0_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[21] ; clk ; clk ; 0.000 ; 2.793 ; 3.023 ; -; 0.189 ; mbus_addr2_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][11] ; clk ; clk ; 0.000 ; 2.820 ; 3.053 ; -; 0.191 ; mbus_addr3_i[19] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][28] ; clk ; clk ; 0.000 ; 2.781 ; 3.016 ; -; 0.191 ; mbus_addr2_i[28] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][37] ; clk ; clk ; 0.000 ; 2.821 ; 3.056 ; -; 0.191 ; mbus_addr1_i[9] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[18] ; clk ; clk ; 0.000 ; 2.833 ; 3.068 ; -; 0.192 ; mbus_addr2_i[8] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[17] ; clk ; clk ; 0.000 ; 2.802 ; 3.038 ; -; 0.192 ; mbus_cmd2_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[5] ; clk ; clk ; 0.000 ; 2.841 ; 3.077 ; -+--------+------------------+--------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Minimum Pulse Width: 'clk' ; -+--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------------------------+ -; -3.000 ; 1.000 ; 4.000 ; Port Rate ; clk ; Rise ; clk ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[10] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[11] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[12] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[13] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[14] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[15] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[16] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[17] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[18] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[19] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[20] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[21] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[22] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[23] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[24] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[25] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[26] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[27] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[28] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[29] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[30] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[31] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[32] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[33] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[34] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[35] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[36] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[37] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[38] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[39] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[40] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[7] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[8] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[9] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][10] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][11] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][12] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][13] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][14] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][15] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][16] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][17] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][18] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][19] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][20] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][21] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][22] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][23] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][24] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][25] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][26] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][27] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][28] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][29] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][30] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][31] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][32] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][33] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][34] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][35] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][36] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][37] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][38] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][39] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][40] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][7] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][8] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][9] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][10] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][11] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][12] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][13] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][14] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][15] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][16] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][17] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][18] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][19] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][20] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][21] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][22] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][23] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][24] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][25] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][26] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][27] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][28] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][29] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][30] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][31] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][32] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][33] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][34] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][35] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][36] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][37] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][38] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][39] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][40] ; -+--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------+ -; Setup Times ; -+-------------------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-------------------+------------+-------+-------+------------+-----------------+ -; cbus_ack0_i ; clk ; 0.487 ; 0.701 ; Rise ; clk ; -; cbus_ack1_i ; clk ; 0.610 ; 0.742 ; Rise ; clk ; -; cbus_ack2_i ; clk ; 0.764 ; 0.796 ; Rise ; clk ; -; cbus_ack3_i ; clk ; 0.690 ; 0.731 ; Rise ; clk ; -; mbus_addr0_i[*] ; clk ; 0.730 ; 0.820 ; Rise ; clk ; -; mbus_addr0_i[0] ; clk ; 0.644 ; 0.774 ; Rise ; clk ; -; mbus_addr0_i[1] ; clk ; 0.558 ; 0.701 ; Rise ; clk ; -; mbus_addr0_i[2] ; clk ; 0.651 ; 0.799 ; Rise ; clk ; -; mbus_addr0_i[3] ; clk ; 0.611 ; 0.755 ; Rise ; clk ; -; mbus_addr0_i[4] ; clk ; 0.660 ; 0.815 ; Rise ; clk ; -; mbus_addr0_i[5] ; clk ; 0.583 ; 0.728 ; Rise ; clk ; -; mbus_addr0_i[6] ; clk ; 0.630 ; 0.775 ; Rise ; clk ; -; mbus_addr0_i[7] ; clk ; 0.493 ; 0.766 ; Rise ; clk ; -; mbus_addr0_i[8] ; clk ; 0.509 ; 0.780 ; Rise ; clk ; -; mbus_addr0_i[9] ; clk ; 0.608 ; 0.756 ; Rise ; clk ; -; mbus_addr0_i[10] ; clk ; 0.626 ; 0.768 ; Rise ; clk ; -; mbus_addr0_i[11] ; clk ; 0.690 ; 0.780 ; Rise ; clk ; -; mbus_addr0_i[12] ; clk ; 0.431 ; 0.651 ; Rise ; clk ; -; mbus_addr0_i[13] ; clk ; 0.603 ; 0.692 ; Rise ; clk ; -; mbus_addr0_i[14] ; clk ; 0.618 ; 0.771 ; Rise ; clk ; -; mbus_addr0_i[15] ; clk ; 0.485 ; 0.767 ; Rise ; clk ; -; mbus_addr0_i[16] ; clk ; 0.569 ; 0.706 ; Rise ; clk ; -; mbus_addr0_i[17] ; clk ; 0.730 ; 0.820 ; Rise ; clk ; -; mbus_addr0_i[18] ; clk ; 0.631 ; 0.795 ; Rise ; clk ; -; mbus_addr0_i[19] ; clk ; 0.611 ; 0.760 ; Rise ; clk ; -; mbus_addr0_i[20] ; clk ; 0.579 ; 0.729 ; Rise ; clk ; -; mbus_addr0_i[21] ; clk ; 0.425 ; 0.658 ; Rise ; clk ; -; mbus_addr0_i[22] ; clk ; 0.396 ; 0.625 ; Rise ; clk ; -; mbus_addr0_i[23] ; clk ; 0.627 ; 0.773 ; Rise ; clk ; -; mbus_addr0_i[24] ; clk ; 0.637 ; 0.785 ; Rise ; clk ; -; mbus_addr0_i[25] ; clk ; 0.543 ; 0.735 ; Rise ; clk ; -; mbus_addr0_i[26] ; clk ; 0.521 ; 0.713 ; Rise ; clk ; -; mbus_addr0_i[27] ; clk ; 0.650 ; 0.807 ; Rise ; clk ; -; mbus_addr0_i[28] ; clk ; 0.565 ; 0.690 ; Rise ; clk ; -; mbus_addr0_i[29] ; clk ; 0.422 ; 0.644 ; Rise ; clk ; -; mbus_addr0_i[30] ; clk ; 0.489 ; 0.758 ; Rise ; clk ; -; mbus_addr0_i[31] ; clk ; 0.529 ; 0.681 ; Rise ; clk ; -; mbus_addr1_i[*] ; clk ; 0.890 ; 0.976 ; Rise ; clk ; -; mbus_addr1_i[0] ; clk ; 0.549 ; 0.661 ; Rise ; clk ; -; mbus_addr1_i[1] ; clk ; 0.638 ; 0.808 ; Rise ; clk ; -; mbus_addr1_i[2] ; clk ; 0.543 ; 0.715 ; Rise ; clk ; -; mbus_addr1_i[3] ; clk ; 0.644 ; 0.797 ; Rise ; clk ; -; mbus_addr1_i[4] ; clk ; 0.497 ; 0.733 ; Rise ; clk ; -; mbus_addr1_i[5] ; clk ; 0.461 ; 0.705 ; Rise ; clk ; -; mbus_addr1_i[6] ; clk ; 0.715 ; 0.841 ; Rise ; clk ; -; mbus_addr1_i[7] ; clk ; 0.549 ; 0.801 ; Rise ; clk ; -; mbus_addr1_i[8] ; clk ; 0.549 ; 0.710 ; Rise ; clk ; -; mbus_addr1_i[9] ; clk ; 0.438 ; 0.667 ; Rise ; clk ; -; mbus_addr1_i[10] ; clk ; 0.376 ; 0.620 ; Rise ; clk ; -; mbus_addr1_i[11] ; clk ; 0.589 ; 0.749 ; Rise ; clk ; -; mbus_addr1_i[12] ; clk ; 0.325 ; 0.529 ; Rise ; clk ; -; mbus_addr1_i[13] ; clk ; 0.547 ; 0.704 ; Rise ; clk ; -; mbus_addr1_i[14] ; clk ; 0.642 ; 0.747 ; Rise ; clk ; -; mbus_addr1_i[15] ; clk ; 0.810 ; 0.941 ; Rise ; clk ; -; mbus_addr1_i[16] ; clk ; 0.535 ; 0.696 ; Rise ; clk ; -; mbus_addr1_i[17] ; clk ; 0.582 ; 0.728 ; Rise ; clk ; -; mbus_addr1_i[18] ; clk ; 0.625 ; 0.767 ; Rise ; clk ; -; mbus_addr1_i[19] ; clk ; 0.617 ; 0.720 ; Rise ; clk ; -; mbus_addr1_i[20] ; clk ; 0.559 ; 0.729 ; Rise ; clk ; -; mbus_addr1_i[21] ; clk ; 0.639 ; 0.725 ; Rise ; clk ; -; mbus_addr1_i[22] ; clk ; 0.491 ; 0.627 ; Rise ; clk ; -; mbus_addr1_i[23] ; clk ; 0.421 ; 0.649 ; Rise ; clk ; -; mbus_addr1_i[24] ; clk ; 0.528 ; 0.681 ; Rise ; clk ; -; mbus_addr1_i[25] ; clk ; 0.890 ; 0.976 ; Rise ; clk ; -; mbus_addr1_i[26] ; clk ; 0.475 ; 0.709 ; Rise ; clk ; -; mbus_addr1_i[27] ; clk ; 0.451 ; 0.619 ; Rise ; clk ; -; mbus_addr1_i[28] ; clk ; 0.453 ; 0.574 ; Rise ; clk ; -; mbus_addr1_i[29] ; clk ; 0.641 ; 0.792 ; Rise ; clk ; -; mbus_addr1_i[30] ; clk ; 0.542 ; 0.723 ; Rise ; clk ; -; mbus_addr1_i[31] ; clk ; 0.628 ; 0.782 ; Rise ; clk ; -; mbus_addr2_i[*] ; clk ; 0.799 ; 0.946 ; Rise ; clk ; -; mbus_addr2_i[0] ; clk ; 0.560 ; 0.757 ; Rise ; clk ; -; mbus_addr2_i[1] ; clk ; 0.588 ; 0.726 ; Rise ; clk ; -; mbus_addr2_i[2] ; clk ; 0.568 ; 0.710 ; Rise ; clk ; -; mbus_addr2_i[3] ; clk ; 0.363 ; 0.604 ; Rise ; clk ; -; mbus_addr2_i[4] ; clk ; 0.391 ; 0.674 ; Rise ; clk ; -; mbus_addr2_i[5] ; clk ; 0.408 ; 0.658 ; Rise ; clk ; -; mbus_addr2_i[6] ; clk ; 0.470 ; 0.637 ; Rise ; clk ; -; mbus_addr2_i[7] ; clk ; 0.570 ; 0.634 ; Rise ; clk ; -; mbus_addr2_i[8] ; clk ; 0.437 ; 0.677 ; Rise ; clk ; -; mbus_addr2_i[9] ; clk ; 0.398 ; 0.621 ; Rise ; clk ; -; mbus_addr2_i[10] ; clk ; 0.678 ; 0.831 ; Rise ; clk ; -; mbus_addr2_i[11] ; clk ; 0.613 ; 0.769 ; Rise ; clk ; -; mbus_addr2_i[12] ; clk ; 0.472 ; 0.750 ; Rise ; clk ; -; mbus_addr2_i[13] ; clk ; 0.497 ; 0.742 ; Rise ; clk ; -; mbus_addr2_i[14] ; clk ; 0.524 ; 0.680 ; Rise ; clk ; -; mbus_addr2_i[15] ; clk ; 0.538 ; 0.712 ; Rise ; clk ; -; mbus_addr2_i[16] ; clk ; 0.661 ; 0.778 ; Rise ; clk ; -; mbus_addr2_i[17] ; clk ; 0.452 ; 0.685 ; Rise ; clk ; -; mbus_addr2_i[18] ; clk ; 0.495 ; 0.705 ; Rise ; clk ; -; mbus_addr2_i[19] ; clk ; 0.510 ; 0.732 ; Rise ; clk ; -; mbus_addr2_i[20] ; clk ; 0.559 ; 0.585 ; Rise ; clk ; -; mbus_addr2_i[21] ; clk ; 0.572 ; 0.723 ; Rise ; clk ; -; mbus_addr2_i[22] ; clk ; 0.427 ; 0.654 ; Rise ; clk ; -; mbus_addr2_i[23] ; clk ; 0.605 ; 0.768 ; Rise ; clk ; -; mbus_addr2_i[24] ; clk ; 0.509 ; 0.648 ; Rise ; clk ; -; mbus_addr2_i[25] ; clk ; 0.411 ; 0.690 ; Rise ; clk ; -; mbus_addr2_i[26] ; clk ; 0.545 ; 0.716 ; Rise ; clk ; -; mbus_addr2_i[27] ; clk ; 0.799 ; 0.946 ; Rise ; clk ; -; mbus_addr2_i[28] ; clk ; 0.471 ; 0.717 ; Rise ; clk ; -; mbus_addr2_i[29] ; clk ; 0.605 ; 0.774 ; Rise ; clk ; -; mbus_addr2_i[30] ; clk ; 0.564 ; 0.688 ; Rise ; clk ; -; mbus_addr2_i[31] ; clk ; 0.693 ; 0.869 ; Rise ; clk ; -; mbus_addr3_i[*] ; clk ; 0.786 ; 0.939 ; Rise ; clk ; -; mbus_addr3_i[0] ; clk ; 0.629 ; 0.777 ; Rise ; clk ; -; mbus_addr3_i[1] ; clk ; 0.581 ; 0.714 ; Rise ; clk ; -; mbus_addr3_i[2] ; clk ; 0.621 ; 0.787 ; Rise ; clk ; -; mbus_addr3_i[3] ; clk ; 0.672 ; 0.762 ; Rise ; clk ; -; mbus_addr3_i[4] ; clk ; 0.669 ; 0.812 ; Rise ; clk ; -; mbus_addr3_i[5] ; clk ; 0.509 ; 0.737 ; Rise ; clk ; -; mbus_addr3_i[6] ; clk ; 0.570 ; 0.728 ; Rise ; clk ; -; mbus_addr3_i[7] ; clk ; 0.786 ; 0.939 ; Rise ; clk ; -; mbus_addr3_i[8] ; clk ; 0.591 ; 0.749 ; Rise ; clk ; -; mbus_addr3_i[9] ; clk ; 0.619 ; 0.730 ; Rise ; clk ; -; mbus_addr3_i[10] ; clk ; 0.608 ; 0.780 ; Rise ; clk ; -; mbus_addr3_i[11] ; clk ; 0.662 ; 0.792 ; Rise ; clk ; -; mbus_addr3_i[12] ; clk ; 0.504 ; 0.757 ; Rise ; clk ; -; mbus_addr3_i[13] ; clk ; 0.614 ; 0.721 ; Rise ; clk ; -; mbus_addr3_i[14] ; clk ; 0.519 ; 0.705 ; Rise ; clk ; -; mbus_addr3_i[15] ; clk ; 0.562 ; 0.701 ; Rise ; clk ; -; mbus_addr3_i[16] ; clk ; 0.692 ; 0.782 ; Rise ; clk ; -; mbus_addr3_i[17] ; clk ; 0.577 ; 0.740 ; Rise ; clk ; -; mbus_addr3_i[18] ; clk ; 0.655 ; 0.803 ; Rise ; clk ; -; mbus_addr3_i[19] ; clk ; 0.634 ; 0.841 ; Rise ; clk ; -; mbus_addr3_i[20] ; clk ; 0.615 ; 0.773 ; Rise ; clk ; -; mbus_addr3_i[21] ; clk ; 0.555 ; 0.703 ; Rise ; clk ; -; mbus_addr3_i[22] ; clk ; 0.647 ; 0.706 ; Rise ; clk ; -; mbus_addr3_i[23] ; clk ; 0.504 ; 0.748 ; Rise ; clk ; -; mbus_addr3_i[24] ; clk ; 0.603 ; 0.781 ; Rise ; clk ; -; mbus_addr3_i[25] ; clk ; 0.486 ; 0.704 ; Rise ; clk ; -; mbus_addr3_i[26] ; clk ; 0.587 ; 0.851 ; Rise ; clk ; -; mbus_addr3_i[27] ; clk ; 0.716 ; 0.829 ; Rise ; clk ; -; mbus_addr3_i[28] ; clk ; 0.586 ; 0.728 ; Rise ; clk ; -; mbus_addr3_i[29] ; clk ; 0.730 ; 0.856 ; Rise ; clk ; -; mbus_addr3_i[30] ; clk ; 0.482 ; 0.708 ; Rise ; clk ; -; mbus_addr3_i[31] ; clk ; 0.516 ; 0.789 ; Rise ; clk ; -; mbus_cmd0_i[*] ; clk ; 0.700 ; 0.839 ; Rise ; clk ; -; mbus_cmd0_i[0] ; clk ; 0.638 ; 0.770 ; Rise ; clk ; -; mbus_cmd0_i[1] ; clk ; 0.700 ; 0.839 ; Rise ; clk ; -; mbus_cmd0_i[2] ; clk ; 0.601 ; 0.684 ; Rise ; clk ; -; mbus_cmd1_i[*] ; clk ; 0.755 ; 0.959 ; Rise ; clk ; -; mbus_cmd1_i[0] ; clk ; 0.686 ; 0.908 ; Rise ; clk ; -; mbus_cmd1_i[1] ; clk ; 0.533 ; 0.768 ; Rise ; clk ; -; mbus_cmd1_i[2] ; clk ; 0.755 ; 0.959 ; Rise ; clk ; -; mbus_cmd2_i[*] ; clk ; 0.599 ; 0.688 ; Rise ; clk ; -; mbus_cmd2_i[0] ; clk ; 0.583 ; 0.676 ; Rise ; clk ; -; mbus_cmd2_i[1] ; clk ; 0.585 ; 0.688 ; Rise ; clk ; -; mbus_cmd2_i[2] ; clk ; 0.599 ; 0.685 ; Rise ; clk ; -; mbus_cmd3_i[*] ; clk ; 0.629 ; 0.808 ; Rise ; clk ; -; mbus_cmd3_i[0] ; clk ; 0.558 ; 0.784 ; Rise ; clk ; -; mbus_cmd3_i[1] ; clk ; 0.619 ; 0.752 ; Rise ; clk ; -; mbus_cmd3_i[2] ; clk ; 0.629 ; 0.808 ; Rise ; clk ; -+-------------------+------------+-------+-------+------------+-----------------+ - - -+---------------------------------------------------------------------------------+ -; Hold Times ; -+-------------------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-------------------+------------+--------+--------+------------+-----------------+ -; cbus_ack0_i ; clk ; -0.037 ; -0.198 ; Rise ; clk ; -; cbus_ack1_i ; clk ; -0.133 ; -0.265 ; Rise ; clk ; -; cbus_ack2_i ; clk ; -0.205 ; -0.359 ; Rise ; clk ; -; cbus_ack3_i ; clk ; -0.152 ; -0.170 ; Rise ; clk ; -; mbus_addr0_i[*] ; clk ; 0.097 ; -0.103 ; Rise ; clk ; -; mbus_addr0_i[0] ; clk ; -0.211 ; -0.372 ; Rise ; clk ; -; mbus_addr0_i[1] ; clk ; -0.128 ; -0.265 ; Rise ; clk ; -; mbus_addr0_i[2] ; clk ; -0.134 ; -0.265 ; Rise ; clk ; -; mbus_addr0_i[3] ; clk ; -0.133 ; -0.267 ; Rise ; clk ; -; mbus_addr0_i[4] ; clk ; -0.137 ; -0.296 ; Rise ; clk ; -; mbus_addr0_i[5] ; clk ; -0.194 ; -0.338 ; Rise ; clk ; -; mbus_addr0_i[6] ; clk ; -0.219 ; -0.358 ; Rise ; clk ; -; mbus_addr0_i[7] ; clk ; 0.026 ; -0.200 ; Rise ; clk ; -; mbus_addr0_i[8] ; clk ; 0.068 ; -0.171 ; Rise ; clk ; -; mbus_addr0_i[9] ; clk ; -0.112 ; -0.241 ; Rise ; clk ; -; mbus_addr0_i[10] ; clk ; -0.196 ; -0.330 ; Rise ; clk ; -; mbus_addr0_i[11] ; clk ; -0.203 ; -0.325 ; Rise ; clk ; -; mbus_addr0_i[12] ; clk ; -0.021 ; -0.251 ; Rise ; clk ; -; mbus_addr0_i[13] ; clk ; -0.145 ; -0.250 ; Rise ; clk ; -; mbus_addr0_i[14] ; clk ; -0.175 ; -0.319 ; Rise ; clk ; -; mbus_addr0_i[15] ; clk ; 0.041 ; -0.201 ; Rise ; clk ; -; mbus_addr0_i[16] ; clk ; -0.113 ; -0.268 ; Rise ; clk ; -; mbus_addr0_i[17] ; clk ; -0.259 ; -0.363 ; Rise ; clk ; -; mbus_addr0_i[18] ; clk ; -0.141 ; -0.219 ; Rise ; clk ; -; mbus_addr0_i[19] ; clk ; -0.069 ; -0.222 ; Rise ; clk ; -; mbus_addr0_i[20] ; clk ; -0.078 ; -0.215 ; Rise ; clk ; -; mbus_addr0_i[21] ; clk ; 0.027 ; -0.181 ; Rise ; clk ; -; mbus_addr0_i[22] ; clk ; -0.017 ; -0.231 ; Rise ; clk ; -; mbus_addr0_i[23] ; clk ; -0.156 ; -0.291 ; Rise ; clk ; -; mbus_addr0_i[24] ; clk ; -0.249 ; -0.372 ; Rise ; clk ; -; mbus_addr0_i[25] ; clk ; -0.085 ; -0.237 ; Rise ; clk ; -; mbus_addr0_i[26] ; clk ; -0.074 ; -0.256 ; Rise ; clk ; -; mbus_addr0_i[27] ; clk ; -0.110 ; -0.266 ; Rise ; clk ; -; mbus_addr0_i[28] ; clk ; -0.109 ; -0.251 ; Rise ; clk ; -; mbus_addr0_i[29] ; clk ; -0.024 ; -0.257 ; Rise ; clk ; -; mbus_addr0_i[30] ; clk ; 0.097 ; -0.103 ; Rise ; clk ; -; mbus_addr0_i[31] ; clk ; -0.149 ; -0.301 ; Rise ; clk ; -; mbus_addr1_i[*] ; clk ; 0.337 ; 0.156 ; Rise ; clk ; -; mbus_addr1_i[0] ; clk ; -0.139 ; -0.242 ; Rise ; clk ; -; mbus_addr1_i[1] ; clk ; -0.169 ; -0.320 ; Rise ; clk ; -; mbus_addr1_i[2] ; clk ; -0.166 ; -0.323 ; Rise ; clk ; -; mbus_addr1_i[3] ; clk ; -0.180 ; -0.331 ; Rise ; clk ; -; mbus_addr1_i[4] ; clk ; 0.067 ; -0.126 ; Rise ; clk ; -; mbus_addr1_i[5] ; clk ; 0.079 ; -0.146 ; Rise ; clk ; -; mbus_addr1_i[6] ; clk ; -0.202 ; -0.324 ; Rise ; clk ; -; mbus_addr1_i[7] ; clk ; 0.337 ; 0.156 ; Rise ; clk ; -; mbus_addr1_i[8] ; clk ; -0.139 ; -0.286 ; Rise ; clk ; -; mbus_addr1_i[9] ; clk ; -0.009 ; -0.191 ; Rise ; clk ; -; mbus_addr1_i[10] ; clk ; 0.002 ; -0.183 ; Rise ; clk ; -; mbus_addr1_i[11] ; clk ; -0.143 ; -0.245 ; Rise ; clk ; -; mbus_addr1_i[12] ; clk ; 0.064 ; -0.160 ; Rise ; clk ; -; mbus_addr1_i[13] ; clk ; -0.141 ; -0.287 ; Rise ; clk ; -; mbus_addr1_i[14] ; clk ; -0.150 ; -0.266 ; Rise ; clk ; -; mbus_addr1_i[15] ; clk ; -0.136 ; -0.264 ; Rise ; clk ; -; mbus_addr1_i[16] ; clk ; -0.131 ; -0.279 ; Rise ; clk ; -; mbus_addr1_i[17] ; clk ; -0.205 ; -0.357 ; Rise ; clk ; -; mbus_addr1_i[18] ; clk ; -0.179 ; -0.327 ; Rise ; clk ; -; mbus_addr1_i[19] ; clk ; -0.206 ; -0.308 ; Rise ; clk ; -; mbus_addr1_i[20] ; clk ; -0.107 ; -0.251 ; Rise ; clk ; -; mbus_addr1_i[21] ; clk ; -0.253 ; -0.350 ; Rise ; clk ; -; mbus_addr1_i[22] ; clk ; -0.093 ; -0.173 ; Rise ; clk ; -; mbus_addr1_i[23] ; clk ; -0.041 ; -0.260 ; Rise ; clk ; -; mbus_addr1_i[24] ; clk ; -0.119 ; -0.268 ; Rise ; clk ; -; mbus_addr1_i[25] ; clk ; -0.127 ; -0.196 ; Rise ; clk ; -; mbus_addr1_i[26] ; clk ; -0.059 ; -0.291 ; Rise ; clk ; -; mbus_addr1_i[27] ; clk ; 0.071 ; -0.100 ; Rise ; clk ; -; mbus_addr1_i[28] ; clk ; -0.075 ; -0.203 ; Rise ; clk ; -; mbus_addr1_i[29] ; clk ; -0.164 ; -0.252 ; Rise ; clk ; -; mbus_addr1_i[30] ; clk ; -0.005 ; -0.170 ; Rise ; clk ; -; mbus_addr1_i[31] ; clk ; -0.060 ; -0.188 ; Rise ; clk ; -; mbus_addr2_i[*] ; clk ; 0.128 ; -0.157 ; Rise ; clk ; -; mbus_addr2_i[0] ; clk ; -0.128 ; -0.233 ; Rise ; clk ; -; mbus_addr2_i[1] ; clk ; -0.197 ; -0.324 ; Rise ; clk ; -; mbus_addr2_i[2] ; clk ; -0.089 ; -0.249 ; Rise ; clk ; -; mbus_addr2_i[3] ; clk ; 0.044 ; -0.211 ; Rise ; clk ; -; mbus_addr2_i[4] ; clk ; 0.054 ; -0.234 ; Rise ; clk ; -; mbus_addr2_i[5] ; clk ; -0.026 ; -0.269 ; Rise ; clk ; -; mbus_addr2_i[6] ; clk ; -0.072 ; -0.226 ; Rise ; clk ; -; mbus_addr2_i[7] ; clk ; -0.108 ; -0.167 ; Rise ; clk ; -; mbus_addr2_i[8] ; clk ; -0.074 ; -0.274 ; Rise ; clk ; -; mbus_addr2_i[9] ; clk ; -0.022 ; -0.250 ; Rise ; clk ; -; mbus_addr2_i[10] ; clk ; -0.172 ; -0.337 ; Rise ; clk ; -; mbus_addr2_i[11] ; clk ; -0.188 ; -0.347 ; Rise ; clk ; -; mbus_addr2_i[12] ; clk ; 0.036 ; -0.253 ; Rise ; clk ; -; mbus_addr2_i[13] ; clk ; -0.108 ; -0.336 ; Rise ; clk ; -; mbus_addr2_i[14] ; clk ; -0.095 ; -0.253 ; Rise ; clk ; -; mbus_addr2_i[15] ; clk ; -0.156 ; -0.334 ; Rise ; clk ; -; mbus_addr2_i[16] ; clk ; -0.096 ; -0.271 ; Rise ; clk ; -; mbus_addr2_i[17] ; clk ; -0.036 ; -0.274 ; Rise ; clk ; -; mbus_addr2_i[18] ; clk ; -0.077 ; -0.254 ; Rise ; clk ; -; mbus_addr2_i[19] ; clk ; -0.126 ; -0.305 ; Rise ; clk ; -; mbus_addr2_i[20] ; clk ; -0.134 ; -0.209 ; Rise ; clk ; -; mbus_addr2_i[21] ; clk ; -0.185 ; -0.331 ; Rise ; clk ; -; mbus_addr2_i[22] ; clk ; 0.040 ; -0.161 ; Rise ; clk ; -; mbus_addr2_i[23] ; clk ; -0.218 ; -0.387 ; Rise ; clk ; -; mbus_addr2_i[24] ; clk ; -0.124 ; -0.271 ; Rise ; clk ; -; mbus_addr2_i[25] ; clk ; 0.128 ; -0.157 ; Rise ; clk ; -; mbus_addr2_i[26] ; clk ; -0.160 ; -0.338 ; Rise ; clk ; -; mbus_addr2_i[27] ; clk ; -0.262 ; -0.388 ; Rise ; clk ; -; mbus_addr2_i[28] ; clk ; -0.091 ; -0.266 ; Rise ; clk ; -; mbus_addr2_i[29] ; clk ; -0.171 ; -0.329 ; Rise ; clk ; -; mbus_addr2_i[30] ; clk ; -0.133 ; -0.247 ; Rise ; clk ; -; mbus_addr2_i[31] ; clk ; -0.290 ; -0.471 ; Rise ; clk ; -; mbus_addr3_i[*] ; clk ; 0.005 ; -0.116 ; Rise ; clk ; -; mbus_addr3_i[0] ; clk ; -0.208 ; -0.379 ; Rise ; clk ; -; mbus_addr3_i[1] ; clk ; -0.101 ; -0.254 ; Rise ; clk ; -; mbus_addr3_i[2] ; clk ; -0.168 ; -0.324 ; Rise ; clk ; -; mbus_addr3_i[3] ; clk ; -0.259 ; -0.366 ; Rise ; clk ; -; mbus_addr3_i[4] ; clk ; -0.272 ; -0.424 ; Rise ; clk ; -; mbus_addr3_i[5] ; clk ; -0.009 ; -0.210 ; Rise ; clk ; -; mbus_addr3_i[6] ; clk ; -0.186 ; -0.341 ; Rise ; clk ; -; mbus_addr3_i[7] ; clk ; -0.085 ; -0.200 ; Rise ; clk ; -; mbus_addr3_i[8] ; clk ; -0.183 ; -0.344 ; Rise ; clk ; -; mbus_addr3_i[9] ; clk ; -0.132 ; -0.261 ; Rise ; clk ; -; mbus_addr3_i[10] ; clk ; -0.126 ; -0.265 ; Rise ; clk ; -; mbus_addr3_i[11] ; clk ; -0.036 ; -0.116 ; Rise ; clk ; -; mbus_addr3_i[12] ; clk ; 0.005 ; -0.220 ; Rise ; clk ; -; mbus_addr3_i[13] ; clk ; -0.171 ; -0.304 ; Rise ; clk ; -; mbus_addr3_i[14] ; clk ; -0.047 ; -0.251 ; Rise ; clk ; -; mbus_addr3_i[15] ; clk ; -0.133 ; -0.274 ; Rise ; clk ; -; mbus_addr3_i[16] ; clk ; -0.201 ; -0.282 ; Rise ; clk ; -; mbus_addr3_i[17] ; clk ; -0.186 ; -0.336 ; Rise ; clk ; -; mbus_addr3_i[18] ; clk ; -0.193 ; -0.333 ; Rise ; clk ; -; mbus_addr3_i[19] ; clk ; -0.047 ; -0.265 ; Rise ; clk ; -; mbus_addr3_i[20] ; clk ; -0.118 ; -0.250 ; Rise ; clk ; -; mbus_addr3_i[21] ; clk ; -0.169 ; -0.267 ; Rise ; clk ; -; mbus_addr3_i[22] ; clk ; -0.212 ; -0.310 ; Rise ; clk ; -; mbus_addr3_i[23] ; clk ; -0.030 ; -0.260 ; Rise ; clk ; -; mbus_addr3_i[24] ; clk ; -0.184 ; -0.396 ; Rise ; clk ; -; mbus_addr3_i[25] ; clk ; -0.100 ; -0.317 ; Rise ; clk ; -; mbus_addr3_i[26] ; clk ; -0.113 ; -0.354 ; Rise ; clk ; -; mbus_addr3_i[27] ; clk ; -0.157 ; -0.232 ; Rise ; clk ; -; mbus_addr3_i[28] ; clk ; -0.182 ; -0.335 ; Rise ; clk ; -; mbus_addr3_i[29] ; clk ; -0.136 ; -0.226 ; Rise ; clk ; -; mbus_addr3_i[30] ; clk ; -0.096 ; -0.333 ; Rise ; clk ; -; mbus_addr3_i[31] ; clk ; -0.119 ; -0.373 ; Rise ; clk ; -; mbus_cmd0_i[*] ; clk ; 0.058 ; -0.084 ; Rise ; clk ; -; mbus_cmd0_i[0] ; clk ; 0.058 ; -0.118 ; Rise ; clk ; -; mbus_cmd0_i[1] ; clk ; -0.139 ; -0.258 ; Rise ; clk ; -; mbus_cmd0_i[2] ; clk ; 0.057 ; -0.084 ; Rise ; clk ; -; mbus_cmd1_i[*] ; clk ; 0.034 ; -0.047 ; Rise ; clk ; -; mbus_cmd1_i[0] ; clk ; -0.033 ; -0.238 ; Rise ; clk ; -; mbus_cmd1_i[1] ; clk ; 0.034 ; -0.047 ; Rise ; clk ; -; mbus_cmd1_i[2] ; clk ; 0.015 ; -0.181 ; Rise ; clk ; -; mbus_cmd2_i[*] ; clk ; -0.060 ; -0.103 ; Rise ; clk ; -; mbus_cmd2_i[0] ; clk ; -0.092 ; -0.159 ; Rise ; clk ; -; mbus_cmd2_i[1] ; clk ; -0.084 ; -0.103 ; Rise ; clk ; -; mbus_cmd2_i[2] ; clk ; -0.060 ; -0.196 ; Rise ; clk ; -; mbus_cmd3_i[*] ; clk ; 0.114 ; -0.121 ; Rise ; clk ; -; mbus_cmd3_i[0] ; clk ; 0.114 ; -0.121 ; Rise ; clk ; -; mbus_cmd3_i[1] ; clk ; -0.058 ; -0.208 ; Rise ; clk ; -; mbus_cmd3_i[2] ; clk ; -0.148 ; -0.352 ; Rise ; clk ; -+-------------------+------------+--------+--------+------------+-----------------+ - - -+------------------------------------------------------------------------------+ -; Clock to Output Times ; -+------------------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+------------------+------------+-------+-------+------------+-----------------+ -; cbus_addr_o[*] ; clk ; 5.453 ; 5.412 ; Rise ; clk ; -; cbus_addr_o[0] ; clk ; 5.354 ; 5.330 ; Rise ; clk ; -; cbus_addr_o[1] ; clk ; 5.398 ; 5.357 ; Rise ; clk ; -; cbus_addr_o[2] ; clk ; 5.329 ; 5.305 ; Rise ; clk ; -; cbus_addr_o[3] ; clk ; 5.321 ; 5.297 ; Rise ; clk ; -; cbus_addr_o[4] ; clk ; 5.341 ; 5.317 ; Rise ; clk ; -; cbus_addr_o[5] ; clk ; 5.312 ; 5.288 ; Rise ; clk ; -; cbus_addr_o[6] ; clk ; 5.351 ; 5.327 ; Rise ; clk ; -; cbus_addr_o[7] ; clk ; 5.420 ; 5.379 ; Rise ; clk ; -; cbus_addr_o[8] ; clk ; 5.382 ; 5.341 ; Rise ; clk ; -; cbus_addr_o[9] ; clk ; 5.331 ; 5.307 ; Rise ; clk ; -; cbus_addr_o[10] ; clk ; 5.408 ; 5.367 ; Rise ; clk ; -; cbus_addr_o[11] ; clk ; 5.325 ; 5.301 ; Rise ; clk ; -; cbus_addr_o[12] ; clk ; 5.453 ; 5.412 ; Rise ; clk ; -; cbus_addr_o[13] ; clk ; 5.314 ; 5.290 ; Rise ; clk ; -; cbus_addr_o[14] ; clk ; 5.393 ; 5.352 ; Rise ; clk ; -; cbus_addr_o[15] ; clk ; 5.401 ; 5.360 ; Rise ; clk ; -; cbus_addr_o[16] ; clk ; 5.405 ; 5.364 ; Rise ; clk ; -; cbus_addr_o[17] ; clk ; 5.332 ; 5.308 ; Rise ; clk ; -; cbus_addr_o[18] ; clk ; 5.330 ; 5.306 ; Rise ; clk ; -; cbus_addr_o[19] ; clk ; 5.334 ; 5.310 ; Rise ; clk ; -; cbus_addr_o[20] ; clk ; 5.339 ; 5.315 ; Rise ; clk ; -; cbus_addr_o[21] ; clk ; 5.321 ; 5.297 ; Rise ; clk ; -; cbus_addr_o[22] ; clk ; 5.341 ; 5.317 ; Rise ; clk ; -; cbus_addr_o[23] ; clk ; 5.327 ; 5.303 ; Rise ; clk ; -; cbus_addr_o[24] ; clk ; 5.333 ; 5.309 ; Rise ; clk ; -; cbus_addr_o[25] ; clk ; 5.330 ; 5.311 ; Rise ; clk ; -; cbus_addr_o[26] ; clk ; 5.331 ; 5.307 ; Rise ; clk ; -; cbus_addr_o[27] ; clk ; 5.362 ; 5.338 ; Rise ; clk ; -; cbus_addr_o[28] ; clk ; 5.334 ; 5.310 ; Rise ; clk ; -; cbus_addr_o[29] ; clk ; 5.354 ; 5.330 ; Rise ; clk ; -; cbus_addr_o[30] ; clk ; 5.406 ; 5.365 ; Rise ; clk ; -; cbus_addr_o[31] ; clk ; 5.325 ; 5.301 ; Rise ; clk ; -; cbus_cmd0_o[*] ; clk ; 8.194 ; 8.149 ; Rise ; clk ; -; cbus_cmd0_o[0] ; clk ; 8.121 ; 8.059 ; Rise ; clk ; -; cbus_cmd0_o[1] ; clk ; 8.194 ; 8.149 ; Rise ; clk ; -; cbus_cmd0_o[2] ; clk ; 8.088 ; 8.045 ; Rise ; clk ; -; cbus_cmd1_o[*] ; clk ; 8.229 ; 8.160 ; Rise ; clk ; -; cbus_cmd1_o[0] ; clk ; 8.229 ; 8.160 ; Rise ; clk ; -; cbus_cmd1_o[1] ; clk ; 8.204 ; 8.086 ; Rise ; clk ; -; cbus_cmd1_o[2] ; clk ; 7.945 ; 7.840 ; Rise ; clk ; -; cbus_cmd2_o[*] ; clk ; 8.267 ; 8.217 ; Rise ; clk ; -; cbus_cmd2_o[0] ; clk ; 7.944 ; 7.911 ; Rise ; clk ; -; cbus_cmd2_o[1] ; clk ; 8.174 ; 8.120 ; Rise ; clk ; -; cbus_cmd2_o[2] ; clk ; 8.267 ; 8.217 ; Rise ; clk ; -; cbus_cmd3_o[*] ; clk ; 8.017 ; 8.008 ; Rise ; clk ; -; cbus_cmd3_o[0] ; clk ; 7.868 ; 7.825 ; Rise ; clk ; -; cbus_cmd3_o[1] ; clk ; 7.912 ; 7.790 ; Rise ; clk ; -; cbus_cmd3_o[2] ; clk ; 8.017 ; 8.008 ; Rise ; clk ; -; mbus_ack0_o ; clk ; 5.329 ; 5.305 ; Rise ; clk ; -; mbus_ack1_o ; clk ; 5.336 ; 5.312 ; Rise ; clk ; -; mbus_ack2_o ; clk ; 5.387 ; 5.346 ; Rise ; clk ; -; mbus_ack3_o ; clk ; 5.395 ; 5.354 ; Rise ; clk ; -+------------------+------------+-------+-------+------------+-----------------+ - - -+------------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+------------------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+------------------+------------+-------+-------+------------+-----------------+ -; cbus_addr_o[*] ; clk ; 5.203 ; 5.180 ; Rise ; clk ; -; cbus_addr_o[0] ; clk ; 5.244 ; 5.221 ; Rise ; clk ; -; cbus_addr_o[1] ; clk ; 5.287 ; 5.247 ; Rise ; clk ; -; cbus_addr_o[2] ; clk ; 5.220 ; 5.197 ; Rise ; clk ; -; cbus_addr_o[3] ; clk ; 5.211 ; 5.188 ; Rise ; clk ; -; cbus_addr_o[4] ; clk ; 5.232 ; 5.209 ; Rise ; clk ; -; cbus_addr_o[5] ; clk ; 5.203 ; 5.180 ; Rise ; clk ; -; cbus_addr_o[6] ; clk ; 5.242 ; 5.219 ; Rise ; clk ; -; cbus_addr_o[7] ; clk ; 5.309 ; 5.269 ; Rise ; clk ; -; cbus_addr_o[8] ; clk ; 5.273 ; 5.233 ; Rise ; clk ; -; cbus_addr_o[9] ; clk ; 5.221 ; 5.198 ; Rise ; clk ; -; cbus_addr_o[10] ; clk ; 5.297 ; 5.257 ; Rise ; clk ; -; cbus_addr_o[11] ; clk ; 5.215 ; 5.192 ; Rise ; clk ; -; cbus_addr_o[12] ; clk ; 5.343 ; 5.303 ; Rise ; clk ; -; cbus_addr_o[13] ; clk ; 5.205 ; 5.182 ; Rise ; clk ; -; cbus_addr_o[14] ; clk ; 5.283 ; 5.243 ; Rise ; clk ; -; cbus_addr_o[15] ; clk ; 5.292 ; 5.252 ; Rise ; clk ; -; cbus_addr_o[16] ; clk ; 5.296 ; 5.256 ; Rise ; clk ; -; cbus_addr_o[17] ; clk ; 5.222 ; 5.199 ; Rise ; clk ; -; cbus_addr_o[18] ; clk ; 5.222 ; 5.199 ; Rise ; clk ; -; cbus_addr_o[19] ; clk ; 5.225 ; 5.202 ; Rise ; clk ; -; cbus_addr_o[20] ; clk ; 5.230 ; 5.207 ; Rise ; clk ; -; cbus_addr_o[21] ; clk ; 5.212 ; 5.189 ; Rise ; clk ; -; cbus_addr_o[22] ; clk ; 5.231 ; 5.208 ; Rise ; clk ; -; cbus_addr_o[23] ; clk ; 5.218 ; 5.195 ; Rise ; clk ; -; cbus_addr_o[24] ; clk ; 5.224 ; 5.201 ; Rise ; clk ; -; cbus_addr_o[25] ; clk ; 5.219 ; 5.201 ; Rise ; clk ; -; cbus_addr_o[26] ; clk ; 5.222 ; 5.199 ; Rise ; clk ; -; cbus_addr_o[27] ; clk ; 5.252 ; 5.229 ; Rise ; clk ; -; cbus_addr_o[28] ; clk ; 5.225 ; 5.202 ; Rise ; clk ; -; cbus_addr_o[29] ; clk ; 5.245 ; 5.222 ; Rise ; clk ; -; cbus_addr_o[30] ; clk ; 5.296 ; 5.256 ; Rise ; clk ; -; cbus_addr_o[31] ; clk ; 5.215 ; 5.192 ; Rise ; clk ; -; cbus_cmd0_o[*] ; clk ; 7.136 ; 7.098 ; Rise ; clk ; -; cbus_cmd0_o[0] ; clk ; 7.186 ; 7.230 ; Rise ; clk ; -; cbus_cmd0_o[1] ; clk ; 7.262 ; 7.281 ; Rise ; clk ; -; cbus_cmd0_o[2] ; clk ; 7.136 ; 7.098 ; Rise ; clk ; -; cbus_cmd1_o[*] ; clk ; 6.982 ; 6.860 ; Rise ; clk ; -; cbus_cmd1_o[0] ; clk ; 7.454 ; 7.482 ; Rise ; clk ; -; cbus_cmd1_o[1] ; clk ; 7.367 ; 7.317 ; Rise ; clk ; -; cbus_cmd1_o[2] ; clk ; 6.982 ; 6.860 ; Rise ; clk ; -; cbus_cmd2_o[*] ; clk ; 7.237 ; 7.256 ; Rise ; clk ; -; cbus_cmd2_o[0] ; clk ; 7.237 ; 7.297 ; Rise ; clk ; -; cbus_cmd2_o[1] ; clk ; 7.433 ; 7.482 ; Rise ; clk ; -; cbus_cmd2_o[2] ; clk ; 7.359 ; 7.256 ; Rise ; clk ; -; cbus_cmd3_o[*] ; clk ; 7.214 ; 7.158 ; Rise ; clk ; -; cbus_cmd3_o[0] ; clk ; 7.294 ; 7.336 ; Rise ; clk ; -; cbus_cmd3_o[1] ; clk ; 7.214 ; 7.158 ; Rise ; clk ; -; cbus_cmd3_o[2] ; clk ; 7.228 ; 7.213 ; Rise ; clk ; -; mbus_ack0_o ; clk ; 5.219 ; 5.196 ; Rise ; clk ; -; mbus_ack1_o ; clk ; 5.226 ; 5.203 ; Rise ; clk ; -; mbus_ack2_o ; clk ; 5.277 ; 5.237 ; Rise ; clk ; -; mbus_ack3_o ; clk ; 5.284 ; 5.244 ; Rise ; clk ; -+------------------+------------+-------+-------+------------+-----------------+ - - ---------------------------------------------- -; Slow 1200mV 0C Model Metastability Report ; ---------------------------------------------- -No synchronizer chains to report. - - -+------------------------------------+ -; Fast 1200mV 0C Model Setup Summary ; -+-------+--------+-------------------+ -; Clock ; Slack ; End Point TNS ; -+-------+--------+-------------------+ -; clk ; -4.682 ; -1313.549 ; -+-------+--------+-------------------+ - - -+-----------------------------------+ -; Fast 1200mV 0C Model Hold Summary ; -+-------+--------+------------------+ -; Clock ; Slack ; End Point TNS ; -+-------+--------+------------------+ -; clk ; -0.271 ; -3.470 ; -+-------+--------+------------------+ - - ------------------------------------------ -; Fast 1200mV 0C Model Recovery Summary ; ------------------------------------------ -No paths to report. - - ----------------------------------------- -; Fast 1200mV 0C Model Removal Summary ; ----------------------------------------- -No paths to report. - - -+--------------------------------------------------+ -; Fast 1200mV 0C Model Minimum Pulse Width Summary ; -+-------+--------+---------------------------------+ -; Clock ; Slack ; End Point TNS ; -+-------+--------+---------------------------------+ -; clk ; -3.000 ; -651.247 ; -+-------+--------+---------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Setup: 'clk' ; -+--------+------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -4.682 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -1.889 ; 3.673 ; -; -4.679 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -1.889 ; 3.670 ; -; -4.646 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -1.887 ; 3.639 ; -; -4.626 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -1.889 ; 3.617 ; -; -4.626 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -1.889 ; 3.617 ; -; -4.624 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -1.888 ; 3.616 ; -; -4.614 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -1.888 ; 3.606 ; -; -4.608 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -1.887 ; 3.601 ; -; -4.595 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -1.889 ; 3.586 ; -; -4.594 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -1.887 ; 3.587 ; -; -4.590 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -1.889 ; 3.581 ; -; -4.587 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -1.889 ; 3.578 ; -; -4.583 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -1.888 ; 3.575 ; -; -4.572 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -1.888 ; 3.564 ; -; -4.568 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[2] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -1.888 ; 3.560 ; -; -4.560 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -1.889 ; 3.551 ; -; -4.560 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -1.889 ; 3.551 ; -; -4.557 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -1.888 ; 3.549 ; -; -4.552 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -1.889 ; 3.543 ; -; -4.552 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -1.889 ; 3.543 ; -; -4.547 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -1.889 ; 3.538 ; -; -4.547 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -1.889 ; 3.538 ; -; -4.542 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -1.889 ; 3.533 ; -; -4.535 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[0] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -1.887 ; 3.528 ; -; -4.534 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -1.888 ; 3.526 ; -; -4.531 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[1] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -1.887 ; 3.524 ; -; -4.527 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -1.889 ; 3.518 ; -; -4.513 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -1.888 ; 3.505 ; -; -4.509 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -1.889 ; 3.500 ; -; -4.506 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -1.889 ; 3.497 ; -; -4.505 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -1.888 ; 3.497 ; -; -4.503 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -1.889 ; 3.494 ; -; -4.491 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[1] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -1.887 ; 3.484 ; -; -4.482 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -1.889 ; 3.473 ; -; -4.476 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -1.889 ; 3.467 ; -; -4.471 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd1_o[0] ; clk ; clk ; 1.000 ; -1.888 ; 3.463 ; -; -4.468 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -1.889 ; 3.459 ; -; -4.468 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -1.888 ; 3.460 ; -; -4.463 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -1.889 ; 3.454 ; -; -4.458 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -1.887 ; 3.451 ; -; -4.456 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -1.888 ; 3.448 ; -; -4.438 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -1.888 ; 3.430 ; -; -4.435 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -1.889 ; 3.426 ; -; -4.433 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -1.888 ; 3.425 ; -; -4.431 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -1.889 ; 3.422 ; -; -4.428 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -1.889 ; 3.419 ; -; -4.422 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -1.889 ; 3.413 ; -; -4.416 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd2_o[1] ; clk ; clk ; 1.000 ; -1.889 ; 3.407 ; -; -4.408 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -1.889 ; 3.399 ; -; -4.406 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[2] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -1.888 ; 3.398 ; -; -4.403 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd1_o[1] ; clk ; clk ; 1.000 ; -1.889 ; 3.394 ; -; -4.397 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -1.888 ; 3.389 ; -; -4.392 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -1.888 ; 3.384 ; -; -4.380 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -1.889 ; 3.371 ; -; -4.380 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -1.889 ; 3.371 ; -; -4.379 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -1.888 ; 3.371 ; -; -4.378 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[2] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -1.888 ; 3.370 ; -; -4.374 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -1.887 ; 3.367 ; -; -4.369 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -1.887 ; 3.362 ; -; -4.367 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -1.888 ; 3.359 ; -; -4.367 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -1.889 ; 3.358 ; -; -4.367 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -1.889 ; 3.358 ; -; -4.354 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -1.889 ; 3.345 ; -; -4.353 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -1.889 ; 3.344 ; -; -4.353 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd2_o[0] ; clk ; clk ; 1.000 ; -1.887 ; 3.346 ; -; -4.353 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -1.889 ; 3.344 ; -; -4.349 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -1.888 ; 3.341 ; -; -4.344 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -1.889 ; 3.335 ; -; -4.337 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -1.888 ; 3.329 ; -; -4.317 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[3] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -1.887 ; 3.310 ; -; -4.316 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -1.889 ; 3.307 ; -; -4.316 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[0] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -1.889 ; 3.307 ; -; -4.303 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[8] ; cbus_cmd0_o[1] ; clk ; clk ; 1.000 ; -1.888 ; 3.295 ; -; -4.302 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -1.887 ; 3.295 ; -; -4.296 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -1.888 ; 3.288 ; -; -4.296 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -1.889 ; 3.287 ; -; -4.291 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -1.888 ; 3.283 ; -; -4.283 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -1.889 ; 3.274 ; -; -4.278 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -1.888 ; 3.270 ; -; -4.276 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -1.889 ; 3.267 ; -; -4.271 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[7] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -1.888 ; 3.263 ; -; -4.269 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -1.889 ; 3.260 ; -; -4.236 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -1.889 ; 3.227 ; -; -4.232 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[1] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -1.889 ; 3.223 ; -; -4.223 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -1.889 ; 3.214 ; -; -4.222 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd2_o[2] ; clk ; clk ; 1.000 ; -1.887 ; 3.215 ; -; -4.215 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[3] ; cbus_cmd3_o[0] ; clk ; clk ; 1.000 ; -1.887 ; 3.208 ; -; -4.209 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -1.889 ; 3.200 ; -; -4.189 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[3] ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -1.887 ; 3.182 ; -; -4.184 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -1.887 ; 3.177 ; -; -4.172 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[3] ; cbus_cmd3_o[1] ; clk ; clk ; 1.000 ; -1.889 ; 3.163 ; -; -4.161 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd3_o[2] ; clk ; clk ; 1.000 ; -1.887 ; 3.154 ; -; -4.147 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[0] ; cbus_cmd0_o[0] ; clk ; clk ; 1.000 ; -1.887 ; 3.140 ; -; -4.122 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[1] ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -1.887 ; 3.115 ; -; -4.108 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[0] ; cbus_cmd0_o[2] ; clk ; clk ; 1.000 ; -1.887 ; 3.101 ; -; -3.944 ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; cbus_cmd1_o[2] ; clk ; clk ; 1.000 ; -1.887 ; 2.937 ; -; -3.275 ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|status_empty ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[11] ; clk ; clk ; 1.000 ; -0.078 ; 4.136 ; -; -3.269 ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|status_empty ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[33] ; clk ; clk ; 1.000 ; -0.073 ; 4.135 ; -; -3.266 ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|status_empty ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[11] ; clk ; clk ; 1.000 ; -0.078 ; 4.127 ; -; -3.260 ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|status_empty ; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[33] ; clk ; clk ; 1.000 ; -0.073 ; 4.126 ; -+--------+------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Hold: 'clk' ; -+--------+------------------+--------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+------------------+--------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -0.271 ; mbus_addr1_i[7] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][16] ; clk ; clk ; 0.000 ; 1.900 ; 1.613 ; -; -0.157 ; mbus_cmd1_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[1]~_Duplicate_1 ; clk ; clk ; 0.000 ; 1.911 ; 1.738 ; -; -0.121 ; mbus_addr1_i[27] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][36] ; clk ; clk ; 0.000 ; 1.872 ; 1.735 ; -; -0.119 ; mbus_cmd3_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[7] ; clk ; clk ; 0.000 ; 1.890 ; 1.755 ; -; -0.107 ; mbus_addr1_i[4] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][13] ; clk ; clk ; 0.000 ; 1.872 ; 1.749 ; -; -0.095 ; mbus_cmd1_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[3] ; clk ; clk ; 0.000 ; 1.911 ; 1.800 ; -; -0.095 ; mbus_cmd2_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[4] ; clk ; clk ; 0.000 ; 1.883 ; 1.772 ; -; -0.094 ; mbus_addr1_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][14] ; clk ; clk ; 0.000 ; 1.874 ; 1.764 ; -; -0.094 ; mbus_addr1_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][14] ; clk ; clk ; 0.000 ; 1.874 ; 1.764 ; -; -0.093 ; mbus_addr0_i[30] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][39] ; clk ; clk ; 0.000 ; 1.903 ; 1.794 ; -; -0.093 ; mbus_addr0_i[30] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][39] ; clk ; clk ; 0.000 ; 1.903 ; 1.794 ; -; -0.086 ; mbus_cmd0_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[0]~_Duplicate_1 ; clk ; clk ; 0.000 ; 1.871 ; 1.769 ; -; -0.084 ; mbus_addr0_i[7] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][16] ; clk ; clk ; 0.000 ; 1.910 ; 1.810 ; -; -0.083 ; mbus_addr2_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][31] ; clk ; clk ; 0.000 ; 1.904 ; 1.805 ; -; -0.082 ; mbus_addr3_i[11] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][20] ; clk ; clk ; 0.000 ; 1.871 ; 1.773 ; -; -0.077 ; mbus_cmd1_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[1] ; clk ; clk ; 0.000 ; 1.881 ; 1.762 ; -; -0.073 ; mbus_addr2_i[25] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][34] ; clk ; clk ; 0.000 ; 1.882 ; 1.793 ; -; -0.069 ; mbus_cmd2_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[2]~_Duplicate_1 ; clk ; clk ; 0.000 ; 1.883 ; 1.798 ; -; -0.064 ; mbus_cmd3_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[6] ; clk ; clk ; 0.000 ; 1.890 ; 1.810 ; -; -0.063 ; mbus_cmd0_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[0]~_Duplicate_1 ; clk ; clk ; 0.000 ; 1.871 ; 1.792 ; -; -0.061 ; mbus_addr1_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][21] ; clk ; clk ; 0.000 ; 1.872 ; 1.795 ; -; -0.058 ; mbus_addr0_i[8] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][17] ; clk ; clk ; 0.000 ; 1.850 ; 1.776 ; -; -0.057 ; mbus_cmd1_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[2] ; clk ; clk ; 0.000 ; 1.911 ; 1.838 ; -; -0.057 ; mbus_cmd2_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[4] ; clk ; clk ; 0.000 ; 1.883 ; 1.810 ; -; -0.054 ; cbus_ack0_i ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; clk ; clk ; 0.000 ; 1.887 ; 1.817 ; -; -0.054 ; mbus_cmd2_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[2]~_Duplicate_1 ; clk ; clk ; 0.000 ; 1.883 ; 1.813 ; -; -0.052 ; mbus_addr1_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[21] ; clk ; clk ; 0.000 ; 1.866 ; 1.798 ; -; -0.051 ; mbus_cmd2_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[5] ; clk ; clk ; 0.000 ; 1.883 ; 1.816 ; -; -0.050 ; mbus_addr1_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][21] ; clk ; clk ; 0.000 ; 1.872 ; 1.806 ; -; -0.049 ; mbus_addr1_i[9] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][18] ; clk ; clk ; 0.000 ; 1.869 ; 1.804 ; -; -0.048 ; mbus_addr0_i[15] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][24] ; clk ; clk ; 0.000 ; 1.844 ; 1.780 ; -; -0.047 ; mbus_addr1_i[10] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][19] ; clk ; clk ; 0.000 ; 1.882 ; 1.819 ; -; -0.047 ; mbus_cmd0_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[0] ; clk ; clk ; 0.000 ; 1.871 ; 1.808 ; -; -0.045 ; mbus_addr2_i[4] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][13] ; clk ; clk ; 0.000 ; 1.859 ; 1.798 ; -; -0.042 ; mbus_addr1_i[30] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][39] ; clk ; clk ; 0.000 ; 1.856 ; 1.798 ; -; -0.042 ; mbus_addr2_i[3] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][12] ; clk ; clk ; 0.000 ; 1.861 ; 1.803 ; -; -0.039 ; mbus_addr1_i[30] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][39] ; clk ; clk ; 0.000 ; 1.855 ; 1.800 ; -; -0.039 ; mbus_cmd0_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[1] ; clk ; clk ; 0.000 ; 1.871 ; 1.816 ; -; -0.038 ; mbus_addr0_i[21] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][30] ; clk ; clk ; 0.000 ; 1.859 ; 1.805 ; -; -0.036 ; mbus_cmd2_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[2] ; clk ; clk ; 0.000 ; 1.848 ; 1.770 ; -; -0.034 ; mbus_addr2_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][31] ; clk ; clk ; 0.000 ; 1.876 ; 1.826 ; -; -0.033 ; mbus_addr2_i[6] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][15] ; clk ; clk ; 0.000 ; 1.874 ; 1.825 ; -; -0.032 ; mbus_addr2_i[17] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][26] ; clk ; clk ; 0.000 ; 1.869 ; 1.821 ; -; -0.031 ; mbus_addr1_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][9] ; clk ; clk ; 0.000 ; 1.878 ; 1.831 ; -; -0.031 ; mbus_addr2_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][14] ; clk ; clk ; 0.000 ; 1.863 ; 1.816 ; -; -0.031 ; mbus_cmd2_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[2]~_Duplicate_1 ; clk ; clk ; 0.000 ; 1.883 ; 1.836 ; -; -0.028 ; mbus_addr3_i[7] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][16] ; clk ; clk ; 0.000 ; 1.892 ; 1.848 ; -; -0.028 ; mbus_addr1_i[31] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][40] ; clk ; clk ; 0.000 ; 1.872 ; 1.828 ; -; -0.027 ; mbus_addr3_i[14] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][23] ; clk ; clk ; 0.000 ; 1.863 ; 1.820 ; -; -0.027 ; mbus_addr2_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][21] ; clk ; clk ; 0.000 ; 1.868 ; 1.825 ; -; -0.027 ; mbus_addr1_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][31] ; clk ; clk ; 0.000 ; 1.881 ; 1.838 ; -; -0.025 ; mbus_addr2_i[3] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[12] ; clk ; clk ; 0.000 ; 1.861 ; 1.820 ; -; -0.023 ; mbus_addr1_i[23] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][32] ; clk ; clk ; 0.000 ; 1.872 ; 1.833 ; -; -0.023 ; cbus_ack1_i ; mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|broad_fifo_rd_o ; clk ; clk ; 0.000 ; 1.887 ; 1.848 ; -; -0.022 ; mbus_addr0_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][31] ; clk ; clk ; 0.000 ; 1.850 ; 1.812 ; -; -0.022 ; mbus_addr1_i[27] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][36] ; clk ; clk ; 0.000 ; 1.862 ; 1.824 ; -; -0.022 ; mbus_addr2_i[3] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][12] ; clk ; clk ; 0.000 ; 1.859 ; 1.821 ; -; -0.021 ; mbus_cmd2_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[2] ; clk ; clk ; 0.000 ; 1.848 ; 1.785 ; -; -0.020 ; mbus_cmd0_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[0] ; clk ; clk ; 0.000 ; 1.871 ; 1.835 ; -; -0.019 ; mbus_addr1_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[9] ; clk ; clk ; 0.000 ; 1.871 ; 1.836 ; -; -0.019 ; mbus_cmd3_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[7] ; clk ; clk ; 0.000 ; 1.890 ; 1.855 ; -; -0.018 ; mbus_addr2_i[18] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][27] ; clk ; clk ; 0.000 ; 1.869 ; 1.835 ; -; -0.018 ; mbus_addr2_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][14] ; clk ; clk ; 0.000 ; 1.878 ; 1.844 ; -; -0.018 ; mbus_addr2_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[31] ; clk ; clk ; 0.000 ; 1.904 ; 1.870 ; -; -0.016 ; mbus_addr2_i[4] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][13] ; clk ; clk ; 0.000 ; 1.861 ; 1.829 ; -; -0.016 ; mbus_addr2_i[6] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[15] ; clk ; clk ; 0.000 ; 1.874 ; 1.842 ; -; -0.015 ; mbus_addr2_i[28] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][37] ; clk ; clk ; 0.000 ; 1.864 ; 1.833 ; -; -0.015 ; mbus_addr1_i[23] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][32] ; clk ; clk ; 0.000 ; 1.878 ; 1.847 ; -; -0.013 ; mbus_addr1_i[25] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][34] ; clk ; clk ; 0.000 ; 1.881 ; 1.852 ; -; -0.013 ; mbus_addr1_i[9] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][18] ; clk ; clk ; 0.000 ; 1.871 ; 1.842 ; -; -0.011 ; mbus_addr3_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][14] ; clk ; clk ; 0.000 ; 1.843 ; 1.816 ; -; -0.011 ; mbus_addr1_i[27] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[36] ; clk ; clk ; 0.000 ; 1.862 ; 1.835 ; -; -0.011 ; mbus_addr2_i[6] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][15] ; clk ; clk ; 0.000 ; 1.875 ; 1.848 ; -; -0.011 ; mbus_addr3_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][21] ; clk ; clk ; 0.000 ; 1.845 ; 1.818 ; -; -0.009 ; mbus_addr1_i[23] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[32] ; clk ; clk ; 0.000 ; 1.872 ; 1.847 ; -; -0.007 ; mbus_addr0_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[31] ; clk ; clk ; 0.000 ; 1.850 ; 1.827 ; -; -0.007 ; mbus_addr2_i[24] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][33] ; clk ; clk ; 0.000 ; 1.873 ; 1.850 ; -; -0.006 ; mbus_cmd0_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[0]~_Duplicate_1 ; clk ; clk ; 0.000 ; 1.871 ; 1.849 ; -; -0.005 ; mbus_addr0_i[12] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][21] ; clk ; clk ; 0.000 ; 1.847 ; 1.826 ; -; -0.005 ; mbus_cmd0_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[1] ; clk ; clk ; 0.000 ; 1.871 ; 1.850 ; -; -0.003 ; mbus_addr3_i[27] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][36] ; clk ; clk ; 0.000 ; 1.872 ; 1.853 ; -; -0.003 ; mbus_cmd3_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[3] ; clk ; clk ; 0.000 ; 1.856 ; 1.811 ; -; -0.003 ; mbus_addr2_i[5] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[14] ; clk ; clk ; 0.000 ; 1.878 ; 1.859 ; -; -0.003 ; mbus_cmd3_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[3] ; clk ; clk ; 0.000 ; 1.856 ; 1.811 ; -; -0.002 ; mbus_addr2_i[4] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[13] ; clk ; clk ; 0.000 ; 1.861 ; 1.843 ; -; -0.002 ; mbus_addr1_i[24] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][33] ; clk ; clk ; 0.000 ; 1.880 ; 1.862 ; -; -0.001 ; mbus_cmd1_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[2] ; clk ; clk ; 0.000 ; 1.911 ; 1.894 ; -; 0.000 ; mbus_addr3_i[19] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[0][28] ; clk ; clk ; 0.000 ; 1.825 ; 1.809 ; -; 0.001 ; mbus_addr3_i[29] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][38] ; clk ; clk ; 0.000 ; 1.863 ; 1.848 ; -; 0.001 ; mbus_addr1_i[9] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[18] ; clk ; clk ; 0.000 ; 1.871 ; 1.856 ; -; 0.001 ; mbus_addr2_i[14] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][23] ; clk ; clk ; 0.000 ; 1.858 ; 1.843 ; -; 0.002 ; mbus_addr2_i[24] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][33] ; clk ; clk ; 0.000 ; 1.871 ; 1.857 ; -; 0.002 ; mbus_cmd2_i[0] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[2] ; clk ; clk ; 0.000 ; 1.848 ; 1.808 ; -; 0.003 ; mbus_addr2_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[1][11] ; clk ; clk ; 0.000 ; 1.861 ; 1.848 ; -; 0.003 ; mbus_addr3_i[9] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|entry[1][18] ; clk ; clk ; 0.000 ; 1.887 ; 1.874 ; -; 0.003 ; mbus_addr1_i[22] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[1][31] ; clk ; clk ; 0.000 ; 1.879 ; 1.866 ; -; 0.004 ; mbus_addr1_i[28] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|entry[0][37] ; clk ; clk ; 0.000 ; 1.855 ; 1.843 ; -; 0.004 ; mbus_cmd2_i[2] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|breq_type_array_o[4] ; clk ; clk ; 0.000 ; 1.883 ; 1.871 ; -; 0.004 ; mbus_cmd3_i[1] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|mbus_ack_array[3] ; clk ; clk ; 0.000 ; 1.856 ; 1.818 ; -; 0.005 ; mbus_addr2_i[17] ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|entry[0][26] ; clk ; clk ; 0.000 ; 1.850 ; 1.839 ; -+--------+------------------+--------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Minimum Pulse Width: 'clk' ; -+--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------------------------+ -; -3.000 ; 1.000 ; 4.000 ; Port Rate ; clk ; Rise ; clk ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[10] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[11] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[12] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[13] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[14] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[15] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[16] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[17] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[18] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[19] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[20] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[21] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[22] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[23] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[24] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[25] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[26] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[27] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[28] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[29] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[30] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[31] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[32] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[33] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[34] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[35] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[36] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[37] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[38] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[39] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[40] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[7] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[8] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[9] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][10] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][11] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][12] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][13] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][14] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][15] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][16] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][17] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][18] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][19] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][20] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][21] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][22] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][23] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][24] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][25] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][26] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][27] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][28] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][29] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][30] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][31] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][32] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][33] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][34] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][35] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][36] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][37] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][38] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][39] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][40] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][7] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][8] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[0][9] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][10] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][11] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][12] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][13] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][14] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][15] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][16] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][17] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][18] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][19] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][20] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][21] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][22] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][23] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][24] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][25] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][26] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][27] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][28] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][29] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][30] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][31] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][32] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][33] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][34] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][35] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][36] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][37] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][38] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][39] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; clk ; Rise ; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|entry[1][40] ; -+--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------+ -; Setup Times ; -+-------------------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-------------------+------------+-------+-------+------------+-----------------+ -; cbus_ack0_i ; clk ; 0.186 ; 0.650 ; Rise ; clk ; -; cbus_ack1_i ; clk ; 0.194 ; 0.665 ; Rise ; clk ; -; cbus_ack2_i ; clk ; 0.490 ; 0.649 ; Rise ; clk ; -; cbus_ack3_i ; clk ; 0.441 ; 0.602 ; Rise ; clk ; -; mbus_addr0_i[*] ; clk ; 0.486 ; 0.831 ; Rise ; clk ; -; mbus_addr0_i[0] ; clk ; 0.243 ; 0.800 ; Rise ; clk ; -; mbus_addr0_i[1] ; clk ; 0.190 ; 0.739 ; Rise ; clk ; -; mbus_addr0_i[2] ; clk ; 0.268 ; 0.813 ; Rise ; clk ; -; mbus_addr0_i[3] ; clk ; 0.243 ; 0.784 ; Rise ; clk ; -; mbus_addr0_i[4] ; clk ; 0.290 ; 0.824 ; Rise ; clk ; -; mbus_addr0_i[5] ; clk ; 0.232 ; 0.771 ; Rise ; clk ; -; mbus_addr0_i[6] ; clk ; 0.249 ; 0.797 ; Rise ; clk ; -; mbus_addr0_i[7] ; clk ; 0.190 ; 0.769 ; Rise ; clk ; -; mbus_addr0_i[8] ; clk ; 0.209 ; 0.773 ; Rise ; clk ; -; mbus_addr0_i[9] ; clk ; 0.245 ; 0.795 ; Rise ; clk ; -; mbus_addr0_i[10] ; clk ; 0.263 ; 0.812 ; Rise ; clk ; -; mbus_addr0_i[11] ; clk ; 0.238 ; 0.779 ; Rise ; clk ; -; mbus_addr0_i[12] ; clk ; 0.144 ; 0.688 ; Rise ; clk ; -; mbus_addr0_i[13] ; clk ; 0.172 ; 0.726 ; Rise ; clk ; -; mbus_addr0_i[14] ; clk ; 0.247 ; 0.798 ; Rise ; clk ; -; mbus_addr0_i[15] ; clk ; 0.194 ; 0.768 ; Rise ; clk ; -; mbus_addr0_i[16] ; clk ; 0.217 ; 0.752 ; Rise ; clk ; -; mbus_addr0_i[17] ; clk ; 0.486 ; 0.658 ; Rise ; clk ; -; mbus_addr0_i[18] ; clk ; 0.242 ; 0.797 ; Rise ; clk ; -; mbus_addr0_i[19] ; clk ; 0.239 ; 0.779 ; Rise ; clk ; -; mbus_addr0_i[20] ; clk ; 0.226 ; 0.757 ; Rise ; clk ; -; mbus_addr0_i[21] ; clk ; 0.152 ; 0.701 ; Rise ; clk ; -; mbus_addr0_i[22] ; clk ; 0.137 ; 0.681 ; Rise ; clk ; -; mbus_addr0_i[23] ; clk ; 0.264 ; 0.808 ; Rise ; clk ; -; mbus_addr0_i[24] ; clk ; 0.238 ; 0.803 ; Rise ; clk ; -; mbus_addr0_i[25] ; clk ; 0.219 ; 0.766 ; Rise ; clk ; -; mbus_addr0_i[26] ; clk ; 0.210 ; 0.744 ; Rise ; clk ; -; mbus_addr0_i[27] ; clk ; 0.271 ; 0.831 ; Rise ; clk ; -; mbus_addr0_i[28] ; clk ; 0.220 ; 0.740 ; Rise ; clk ; -; mbus_addr0_i[29] ; clk ; 0.148 ; 0.721 ; Rise ; clk ; -; mbus_addr0_i[30] ; clk ; 0.196 ; 0.763 ; Rise ; clk ; -; mbus_addr0_i[31] ; clk ; 0.194 ; 0.733 ; Rise ; clk ; -; mbus_addr1_i[*] ; clk ; 0.379 ; 0.907 ; Rise ; clk ; -; mbus_addr1_i[0] ; clk ; 0.146 ; 0.702 ; Rise ; clk ; -; mbus_addr1_i[1] ; clk ; 0.231 ; 0.802 ; Rise ; clk ; -; mbus_addr1_i[2] ; clk ; 0.168 ; 0.738 ; Rise ; clk ; -; mbus_addr1_i[3] ; clk ; 0.246 ; 0.801 ; Rise ; clk ; -; mbus_addr1_i[4] ; clk ; 0.180 ; 0.743 ; Rise ; clk ; -; mbus_addr1_i[5] ; clk ; 0.136 ; 0.698 ; Rise ; clk ; -; mbus_addr1_i[6] ; clk ; 0.275 ; 0.820 ; Rise ; clk ; -; mbus_addr1_i[7] ; clk ; 0.229 ; 0.775 ; Rise ; clk ; -; mbus_addr1_i[8] ; clk ; 0.177 ; 0.742 ; Rise ; clk ; -; mbus_addr1_i[9] ; clk ; 0.121 ; 0.688 ; Rise ; clk ; -; mbus_addr1_i[10] ; clk ; 0.140 ; 0.663 ; Rise ; clk ; -; mbus_addr1_i[11] ; clk ; 0.211 ; 0.770 ; Rise ; clk ; -; mbus_addr1_i[12] ; clk ; 0.073 ; 0.598 ; Rise ; clk ; -; mbus_addr1_i[13] ; clk ; 0.184 ; 0.736 ; Rise ; clk ; -; mbus_addr1_i[14] ; clk ; 0.215 ; 0.761 ; Rise ; clk ; -; mbus_addr1_i[15] ; clk ; 0.346 ; 0.895 ; Rise ; clk ; -; mbus_addr1_i[16] ; clk ; 0.180 ; 0.708 ; Rise ; clk ; -; mbus_addr1_i[17] ; clk ; 0.371 ; 0.580 ; Rise ; clk ; -; mbus_addr1_i[18] ; clk ; 0.379 ; 0.587 ; Rise ; clk ; -; mbus_addr1_i[19] ; clk ; 0.198 ; 0.747 ; Rise ; clk ; -; mbus_addr1_i[20] ; clk ; 0.187 ; 0.753 ; Rise ; clk ; -; mbus_addr1_i[21] ; clk ; 0.223 ; 0.756 ; Rise ; clk ; -; mbus_addr1_i[22] ; clk ; 0.135 ; 0.676 ; Rise ; clk ; -; mbus_addr1_i[23] ; clk ; 0.110 ; 0.674 ; Rise ; clk ; -; mbus_addr1_i[24] ; clk ; 0.166 ; 0.716 ; Rise ; clk ; -; mbus_addr1_i[25] ; clk ; 0.353 ; 0.907 ; Rise ; clk ; -; mbus_addr1_i[26] ; clk ; 0.165 ; 0.725 ; Rise ; clk ; -; mbus_addr1_i[27] ; clk ; 0.108 ; 0.647 ; Rise ; clk ; -; mbus_addr1_i[28] ; clk ; 0.133 ; 0.655 ; Rise ; clk ; -; mbus_addr1_i[29] ; clk ; 0.234 ; 0.793 ; Rise ; clk ; -; mbus_addr1_i[30] ; clk ; 0.179 ; 0.728 ; Rise ; clk ; -; mbus_addr1_i[31] ; clk ; 0.233 ; 0.789 ; Rise ; clk ; -; mbus_addr2_i[*] ; clk ; 0.309 ; 0.878 ; Rise ; clk ; -; mbus_addr2_i[0] ; clk ; 0.208 ; 0.780 ; Rise ; clk ; -; mbus_addr2_i[1] ; clk ; 0.229 ; 0.779 ; Rise ; clk ; -; mbus_addr2_i[2] ; clk ; 0.194 ; 0.755 ; Rise ; clk ; -; mbus_addr2_i[3] ; clk ; 0.094 ; 0.655 ; Rise ; clk ; -; mbus_addr2_i[4] ; clk ; 0.113 ; 0.710 ; Rise ; clk ; -; mbus_addr2_i[5] ; clk ; 0.116 ; 0.688 ; Rise ; clk ; -; mbus_addr2_i[6] ; clk ; 0.112 ; 0.660 ; Rise ; clk ; -; mbus_addr2_i[7] ; clk ; 0.190 ; 0.687 ; Rise ; clk ; -; mbus_addr2_i[8] ; clk ; 0.168 ; 0.727 ; Rise ; clk ; -; mbus_addr2_i[9] ; clk ; 0.141 ; 0.686 ; Rise ; clk ; -; mbus_addr2_i[10] ; clk ; 0.289 ; 0.839 ; Rise ; clk ; -; mbus_addr2_i[11] ; clk ; 0.202 ; 0.769 ; Rise ; clk ; -; mbus_addr2_i[12] ; clk ; 0.170 ; 0.747 ; Rise ; clk ; -; mbus_addr2_i[13] ; clk ; 0.169 ; 0.745 ; Rise ; clk ; -; mbus_addr2_i[14] ; clk ; 0.155 ; 0.687 ; Rise ; clk ; -; mbus_addr2_i[15] ; clk ; 0.212 ; 0.775 ; Rise ; clk ; -; mbus_addr2_i[16] ; clk ; 0.232 ; 0.786 ; Rise ; clk ; -; mbus_addr2_i[17] ; clk ; 0.138 ; 0.703 ; Rise ; clk ; -; mbus_addr2_i[18] ; clk ; 0.162 ; 0.739 ; Rise ; clk ; -; mbus_addr2_i[19] ; clk ; 0.308 ; 0.530 ; Rise ; clk ; -; mbus_addr2_i[20] ; clk ; 0.159 ; 0.661 ; Rise ; clk ; -; mbus_addr2_i[21] ; clk ; 0.204 ; 0.747 ; Rise ; clk ; -; mbus_addr2_i[22] ; clk ; 0.124 ; 0.680 ; Rise ; clk ; -; mbus_addr2_i[23] ; clk ; 0.230 ; 0.788 ; Rise ; clk ; -; mbus_addr2_i[24] ; clk ; 0.135 ; 0.675 ; Rise ; clk ; -; mbus_addr2_i[25] ; clk ; 0.142 ; 0.720 ; Rise ; clk ; -; mbus_addr2_i[26] ; clk ; 0.161 ; 0.724 ; Rise ; clk ; -; mbus_addr2_i[27] ; clk ; 0.309 ; 0.878 ; Rise ; clk ; -; mbus_addr2_i[28] ; clk ; 0.142 ; 0.723 ; Rise ; clk ; -; mbus_addr2_i[29] ; clk ; 0.212 ; 0.773 ; Rise ; clk ; -; mbus_addr2_i[30] ; clk ; 0.205 ; 0.739 ; Rise ; clk ; -; mbus_addr2_i[31] ; clk ; 0.289 ; 0.861 ; Rise ; clk ; -; mbus_addr3_i[*] ; clk ; 0.330 ; 0.894 ; Rise ; clk ; -; mbus_addr3_i[0] ; clk ; 0.256 ; 0.799 ; Rise ; clk ; -; mbus_addr3_i[1] ; clk ; 0.212 ; 0.748 ; Rise ; clk ; -; mbus_addr3_i[2] ; clk ; 0.237 ; 0.796 ; Rise ; clk ; -; mbus_addr3_i[3] ; clk ; 0.234 ; 0.770 ; Rise ; clk ; -; mbus_addr3_i[4] ; clk ; 0.247 ; 0.808 ; Rise ; clk ; -; mbus_addr3_i[5] ; clk ; 0.193 ; 0.749 ; Rise ; clk ; -; mbus_addr3_i[6] ; clk ; 0.220 ; 0.767 ; Rise ; clk ; -; mbus_addr3_i[7] ; clk ; 0.330 ; 0.894 ; Rise ; clk ; -; mbus_addr3_i[8] ; clk ; 0.214 ; 0.765 ; Rise ; clk ; -; mbus_addr3_i[9] ; clk ; 0.193 ; 0.735 ; Rise ; clk ; -; mbus_addr3_i[10] ; clk ; 0.224 ; 0.794 ; Rise ; clk ; -; mbus_addr3_i[11] ; clk ; 0.221 ; 0.770 ; Rise ; clk ; -; mbus_addr3_i[12] ; clk ; 0.182 ; 0.751 ; Rise ; clk ; -; mbus_addr3_i[13] ; clk ; 0.246 ; 0.785 ; Rise ; clk ; -; mbus_addr3_i[14] ; clk ; 0.153 ; 0.705 ; Rise ; clk ; -; mbus_addr3_i[15] ; clk ; 0.210 ; 0.752 ; Rise ; clk ; -; mbus_addr3_i[16] ; clk ; 0.290 ; 0.811 ; Rise ; clk ; -; mbus_addr3_i[17] ; clk ; 0.209 ; 0.765 ; Rise ; clk ; -; mbus_addr3_i[18] ; clk ; 0.281 ; 0.819 ; Rise ; clk ; -; mbus_addr3_i[19] ; clk ; 0.261 ; 0.810 ; Rise ; clk ; -; mbus_addr3_i[20] ; clk ; 0.216 ; 0.785 ; Rise ; clk ; -; mbus_addr3_i[21] ; clk ; 0.166 ; 0.719 ; Rise ; clk ; -; mbus_addr3_i[22] ; clk ; 0.212 ; 0.754 ; Rise ; clk ; -; mbus_addr3_i[23] ; clk ; 0.212 ; 0.766 ; Rise ; clk ; -; mbus_addr3_i[24] ; clk ; 0.252 ; 0.828 ; Rise ; clk ; -; mbus_addr3_i[25] ; clk ; 0.191 ; 0.729 ; Rise ; clk ; -; mbus_addr3_i[26] ; clk ; 0.249 ; 0.835 ; Rise ; clk ; -; mbus_addr3_i[27] ; clk ; 0.256 ; 0.796 ; Rise ; clk ; -; mbus_addr3_i[28] ; clk ; 0.234 ; 0.767 ; Rise ; clk ; -; mbus_addr3_i[29] ; clk ; 0.271 ; 0.833 ; Rise ; clk ; -; mbus_addr3_i[30] ; clk ; 0.187 ; 0.738 ; Rise ; clk ; -; mbus_addr3_i[31] ; clk ; 0.207 ; 0.810 ; Rise ; clk ; -; mbus_cmd0_i[*] ; clk ; 0.317 ; 0.703 ; Rise ; clk ; -; mbus_cmd0_i[0] ; clk ; 0.195 ; 0.665 ; Rise ; clk ; -; mbus_cmd0_i[1] ; clk ; 0.317 ; 0.703 ; Rise ; clk ; -; mbus_cmd0_i[2] ; clk ; 0.153 ; 0.634 ; Rise ; clk ; -; mbus_cmd1_i[*] ; clk ; 0.296 ; 0.782 ; Rise ; clk ; -; mbus_cmd1_i[0] ; clk ; 0.269 ; 0.742 ; Rise ; clk ; -; mbus_cmd1_i[1] ; clk ; 0.240 ; 0.720 ; Rise ; clk ; -; mbus_cmd1_i[2] ; clk ; 0.296 ; 0.782 ; Rise ; clk ; -; mbus_cmd2_i[*] ; clk ; 0.222 ; 0.639 ; Rise ; clk ; -; mbus_cmd2_i[0] ; clk ; 0.217 ; 0.623 ; Rise ; clk ; -; mbus_cmd2_i[1] ; clk ; 0.222 ; 0.569 ; Rise ; clk ; -; mbus_cmd2_i[2] ; clk ; 0.191 ; 0.639 ; Rise ; clk ; -; mbus_cmd3_i[*] ; clk ; 0.227 ; 0.721 ; Rise ; clk ; -; mbus_cmd3_i[0] ; clk ; 0.201 ; 0.721 ; Rise ; clk ; -; mbus_cmd3_i[1] ; clk ; 0.219 ; 0.671 ; Rise ; clk ; -; mbus_cmd3_i[2] ; clk ; 0.227 ; 0.710 ; Rise ; clk ; -+-------------------+------------+-------+-------+------------+-----------------+ - - -+---------------------------------------------------------------------------------+ -; Hold Times ; -+-------------------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-------------------+------------+--------+--------+------------+-----------------+ -; cbus_ack0_i ; clk ; 0.154 ; -0.387 ; Rise ; clk ; -; cbus_ack1_i ; clk ; 0.123 ; -0.400 ; Rise ; clk ; -; cbus_ack2_i ; clk ; -0.133 ; -0.365 ; Rise ; clk ; -; cbus_ack3_i ; clk ; -0.062 ; -0.286 ; Rise ; clk ; -; mbus_addr0_i[*] ; clk ; 0.193 ; -0.321 ; Rise ; clk ; -; mbus_addr0_i[0] ; clk ; 0.011 ; -0.531 ; Rise ; clk ; -; mbus_addr0_i[1] ; clk ; 0.063 ; -0.474 ; Rise ; clk ; -; mbus_addr0_i[2] ; clk ; 0.074 ; -0.461 ; Rise ; clk ; -; mbus_addr0_i[3] ; clk ; 0.055 ; -0.481 ; Rise ; clk ; -; mbus_addr0_i[4] ; clk ; 0.037 ; -0.495 ; Rise ; clk ; -; mbus_addr0_i[5] ; clk ; 0.017 ; -0.516 ; Rise ; clk ; -; mbus_addr0_i[6] ; clk ; 0.006 ; -0.525 ; Rise ; clk ; -; mbus_addr0_i[7] ; clk ; 0.184 ; -0.379 ; Rise ; clk ; -; mbus_addr0_i[8] ; clk ; 0.158 ; -0.378 ; Rise ; clk ; -; mbus_addr0_i[9] ; clk ; 0.063 ; -0.469 ; Rise ; clk ; -; mbus_addr0_i[10] ; clk ; 0.019 ; -0.501 ; Rise ; clk ; -; mbus_addr0_i[11] ; clk ; 0.055 ; -0.468 ; Rise ; clk ; -; mbus_addr0_i[12] ; clk ; 0.105 ; -0.437 ; Rise ; clk ; -; mbus_addr0_i[13] ; clk ; 0.094 ; -0.439 ; Rise ; clk ; -; mbus_addr0_i[14] ; clk ; 0.029 ; -0.520 ; Rise ; clk ; -; mbus_addr0_i[15] ; clk ; 0.148 ; -0.409 ; Rise ; clk ; -; mbus_addr0_i[16] ; clk ; 0.061 ; -0.472 ; Rise ; clk ; -; mbus_addr0_i[17] ; clk ; -0.185 ; -0.393 ; Rise ; clk ; -; mbus_addr0_i[18] ; clk ; 0.085 ; -0.422 ; Rise ; clk ; -; mbus_addr0_i[19] ; clk ; 0.083 ; -0.438 ; Rise ; clk ; -; mbus_addr0_i[20] ; clk ; 0.078 ; -0.446 ; Rise ; clk ; -; mbus_addr0_i[21] ; clk ; 0.138 ; -0.399 ; Rise ; clk ; -; mbus_addr0_i[22] ; clk ; 0.122 ; -0.410 ; Rise ; clk ; -; mbus_addr0_i[23] ; clk ; 0.028 ; -0.509 ; Rise ; clk ; -; mbus_addr0_i[24] ; clk ; -0.002 ; -0.552 ; Rise ; clk ; -; mbus_addr0_i[25] ; clk ; 0.056 ; -0.475 ; Rise ; clk ; -; mbus_addr0_i[26] ; clk ; 0.063 ; -0.479 ; Rise ; clk ; -; mbus_addr0_i[27] ; clk ; 0.053 ; -0.479 ; Rise ; clk ; -; mbus_addr0_i[28] ; clk ; 0.070 ; -0.469 ; Rise ; clk ; -; mbus_addr0_i[29] ; clk ; 0.091 ; -0.455 ; Rise ; clk ; -; mbus_addr0_i[30] ; clk ; 0.193 ; -0.321 ; Rise ; clk ; -; mbus_addr0_i[31] ; clk ; 0.052 ; -0.488 ; Rise ; clk ; -; mbus_addr1_i[*] ; clk ; 0.371 ; -0.118 ; Rise ; clk ; -; mbus_addr1_i[0] ; clk ; 0.131 ; -0.401 ; Rise ; clk ; -; mbus_addr1_i[1] ; clk ; 0.070 ; -0.478 ; Rise ; clk ; -; mbus_addr1_i[2] ; clk ; 0.075 ; -0.469 ; Rise ; clk ; -; mbus_addr1_i[3] ; clk ; 0.046 ; -0.499 ; Rise ; clk ; -; mbus_addr1_i[4] ; clk ; 0.207 ; -0.320 ; Rise ; clk ; -; mbus_addr1_i[5] ; clk ; 0.194 ; -0.350 ; Rise ; clk ; -; mbus_addr1_i[6] ; clk ; 0.058 ; -0.495 ; Rise ; clk ; -; mbus_addr1_i[7] ; clk ; 0.371 ; -0.118 ; Rise ; clk ; -; mbus_addr1_i[8] ; clk ; 0.073 ; -0.472 ; Rise ; clk ; -; mbus_addr1_i[9] ; clk ; 0.149 ; -0.384 ; Rise ; clk ; -; mbus_addr1_i[10] ; clk ; 0.147 ; -0.347 ; Rise ; clk ; -; mbus_addr1_i[11] ; clk ; 0.080 ; -0.438 ; Rise ; clk ; -; mbus_addr1_i[12] ; clk ; 0.161 ; -0.350 ; Rise ; clk ; -; mbus_addr1_i[13] ; clk ; 0.066 ; -0.457 ; Rise ; clk ; -; mbus_addr1_i[14] ; clk ; 0.078 ; -0.453 ; Rise ; clk ; -; mbus_addr1_i[15] ; clk ; 0.066 ; -0.456 ; Rise ; clk ; -; mbus_addr1_i[16] ; clk ; 0.079 ; -0.456 ; Rise ; clk ; -; mbus_addr1_i[17] ; clk ; -0.129 ; -0.345 ; Rise ; clk ; -; mbus_addr1_i[18] ; clk ; -0.097 ; -0.307 ; Rise ; clk ; -; mbus_addr1_i[19] ; clk ; 0.051 ; -0.483 ; Rise ; clk ; -; mbus_addr1_i[20] ; clk ; 0.090 ; -0.441 ; Rise ; clk ; -; mbus_addr1_i[21] ; clk ; 0.010 ; -0.510 ; Rise ; clk ; -; mbus_addr1_i[22] ; clk ; 0.127 ; -0.393 ; Rise ; clk ; -; mbus_addr1_i[23] ; clk ; 0.123 ; -0.427 ; Rise ; clk ; -; mbus_addr1_i[24] ; clk ; 0.102 ; -0.438 ; Rise ; clk ; -; mbus_addr1_i[25] ; clk ; 0.113 ; -0.409 ; Rise ; clk ; -; mbus_addr1_i[26] ; clk ; 0.095 ; -0.456 ; Rise ; clk ; -; mbus_addr1_i[27] ; clk ; 0.221 ; -0.298 ; Rise ; clk ; -; mbus_addr1_i[28] ; clk ; 0.096 ; -0.423 ; Rise ; clk ; -; mbus_addr1_i[29] ; clk ; 0.086 ; -0.433 ; Rise ; clk ; -; mbus_addr1_i[30] ; clk ; 0.142 ; -0.386 ; Rise ; clk ; -; mbus_addr1_i[31] ; clk ; 0.128 ; -0.403 ; Rise ; clk ; -; mbus_addr2_i[*] ; clk ; 0.183 ; -0.294 ; Rise ; clk ; -; mbus_addr2_i[0] ; clk ; 0.071 ; -0.440 ; Rise ; clk ; -; mbus_addr2_i[1] ; clk ; 0.002 ; -0.539 ; Rise ; clk ; -; mbus_addr2_i[2] ; clk ; 0.097 ; -0.441 ; Rise ; clk ; -; mbus_addr2_i[3] ; clk ; 0.142 ; -0.415 ; Rise ; clk ; -; mbus_addr2_i[4] ; clk ; 0.145 ; -0.432 ; Rise ; clk ; -; mbus_addr2_i[5] ; clk ; 0.131 ; -0.421 ; Rise ; clk ; -; mbus_addr2_i[6] ; clk ; 0.133 ; -0.398 ; Rise ; clk ; -; mbus_addr2_i[7] ; clk ; 0.081 ; -0.415 ; Rise ; clk ; -; mbus_addr2_i[8] ; clk ; 0.055 ; -0.475 ; Rise ; clk ; -; mbus_addr2_i[9] ; clk ; 0.088 ; -0.445 ; Rise ; clk ; -; mbus_addr2_i[10] ; clk ; 0.020 ; -0.531 ; Rise ; clk ; -; mbus_addr2_i[11] ; clk ; 0.045 ; -0.504 ; Rise ; clk ; -; mbus_addr2_i[12] ; clk ; 0.127 ; -0.445 ; Rise ; clk ; -; mbus_addr2_i[13] ; clk ; 0.071 ; -0.484 ; Rise ; clk ; -; mbus_addr2_i[14] ; clk ; 0.099 ; -0.431 ; Rise ; clk ; -; mbus_addr2_i[15] ; clk ; 0.021 ; -0.533 ; Rise ; clk ; -; mbus_addr2_i[16] ; clk ; 0.071 ; -0.472 ; Rise ; clk ; -; mbus_addr2_i[17] ; clk ; 0.132 ; -0.432 ; Rise ; clk ; -; mbus_addr2_i[18] ; clk ; 0.118 ; -0.421 ; Rise ; clk ; -; mbus_addr2_i[19] ; clk ; -0.073 ; -0.294 ; Rise ; clk ; -; mbus_addr2_i[20] ; clk ; 0.085 ; -0.412 ; Rise ; clk ; -; mbus_addr2_i[21] ; clk ; 0.055 ; -0.467 ; Rise ; clk ; -; mbus_addr2_i[22] ; clk ; 0.183 ; -0.365 ; Rise ; clk ; -; mbus_addr2_i[23] ; clk ; 0.023 ; -0.531 ; Rise ; clk ; -; mbus_addr2_i[24] ; clk ; 0.107 ; -0.437 ; Rise ; clk ; -; mbus_addr2_i[25] ; clk ; 0.173 ; -0.382 ; Rise ; clk ; -; mbus_addr2_i[26] ; clk ; 0.072 ; -0.476 ; Rise ; clk ; -; mbus_addr2_i[27] ; clk ; 0.009 ; -0.540 ; Rise ; clk ; -; mbus_addr2_i[28] ; clk ; 0.115 ; -0.412 ; Rise ; clk ; -; mbus_addr2_i[29] ; clk ; 0.067 ; -0.483 ; Rise ; clk ; -; mbus_addr2_i[30] ; clk ; 0.070 ; -0.440 ; Rise ; clk ; -; mbus_addr2_i[31] ; clk ; -0.042 ; -0.606 ; Rise ; clk ; -; mbus_addr3_i[*] ; clk ; 0.182 ; -0.336 ; Rise ; clk ; -; mbus_addr3_i[0] ; clk ; -0.004 ; -0.555 ; Rise ; clk ; -; mbus_addr3_i[1] ; clk ; 0.060 ; -0.482 ; Rise ; clk ; -; mbus_addr3_i[2] ; clk ; 0.035 ; -0.495 ; Rise ; clk ; -; mbus_addr3_i[3] ; clk ; 0.021 ; -0.522 ; Rise ; clk ; -; mbus_addr3_i[4] ; clk ; -0.007 ; -0.567 ; Rise ; clk ; -; mbus_addr3_i[5] ; clk ; 0.111 ; -0.430 ; Rise ; clk ; -; mbus_addr3_i[6] ; clk ; 0.015 ; -0.522 ; Rise ; clk ; -; mbus_addr3_i[7] ; clk ; 0.128 ; -0.390 ; Rise ; clk ; -; mbus_addr3_i[8] ; clk ; 0.042 ; -0.501 ; Rise ; clk ; -; mbus_addr3_i[9] ; clk ; 0.097 ; -0.432 ; Rise ; clk ; -; mbus_addr3_i[10] ; clk ; 0.087 ; -0.453 ; Rise ; clk ; -; mbus_addr3_i[11] ; clk ; 0.182 ; -0.336 ; Rise ; clk ; -; mbus_addr3_i[12] ; clk ; 0.111 ; -0.435 ; Rise ; clk ; -; mbus_addr3_i[13] ; clk ; 0.034 ; -0.485 ; Rise ; clk ; -; mbus_addr3_i[14] ; clk ; 0.127 ; -0.415 ; Rise ; clk ; -; mbus_addr3_i[15] ; clk ; 0.065 ; -0.462 ; Rise ; clk ; -; mbus_addr3_i[16] ; clk ; 0.013 ; -0.500 ; Rise ; clk ; -; mbus_addr3_i[17] ; clk ; 0.028 ; -0.508 ; Rise ; clk ; -; mbus_addr3_i[18] ; clk ; 0.010 ; -0.535 ; Rise ; clk ; -; mbus_addr3_i[19] ; clk ; 0.100 ; -0.424 ; Rise ; clk ; -; mbus_addr3_i[20] ; clk ; 0.087 ; -0.459 ; Rise ; clk ; -; mbus_addr3_i[21] ; clk ; 0.088 ; -0.445 ; Rise ; clk ; -; mbus_addr3_i[22] ; clk ; 0.050 ; -0.481 ; Rise ; clk ; -; mbus_addr3_i[23] ; clk ; 0.079 ; -0.470 ; Rise ; clk ; -; mbus_addr3_i[24] ; clk ; -0.003 ; -0.569 ; Rise ; clk ; -; mbus_addr3_i[25] ; clk ; 0.052 ; -0.473 ; Rise ; clk ; -; mbus_addr3_i[26] ; clk ; 0.048 ; -0.523 ; Rise ; clk ; -; mbus_addr3_i[27] ; clk ; 0.103 ; -0.405 ; Rise ; clk ; -; mbus_addr3_i[28] ; clk ; 0.017 ; -0.516 ; Rise ; clk ; -; mbus_addr3_i[29] ; clk ; 0.099 ; -0.417 ; Rise ; clk ; -; mbus_addr3_i[30] ; clk ; 0.047 ; -0.500 ; Rise ; clk ; -; mbus_addr3_i[31] ; clk ; 0.060 ; -0.511 ; Rise ; clk ; -; mbus_cmd0_i[*] ; clk ; 0.186 ; -0.172 ; Rise ; clk ; -; mbus_cmd0_i[0] ; clk ; 0.163 ; -0.187 ; Rise ; clk ; -; mbus_cmd0_i[1] ; clk ; 0.106 ; -0.304 ; Rise ; clk ; -; mbus_cmd0_i[2] ; clk ; 0.186 ; -0.172 ; Rise ; clk ; -; mbus_cmd1_i[*] ; clk ; 0.257 ; -0.211 ; Rise ; clk ; -; mbus_cmd1_i[0] ; clk ; 0.157 ; -0.374 ; Rise ; clk ; -; mbus_cmd1_i[1] ; clk ; 0.257 ; -0.211 ; Rise ; clk ; -; mbus_cmd1_i[2] ; clk ; 0.195 ; -0.329 ; Rise ; clk ; -; mbus_cmd2_i[*] ; clk ; 0.195 ; -0.254 ; Rise ; clk ; -; mbus_cmd2_i[0] ; clk ; 0.157 ; -0.277 ; Rise ; clk ; -; mbus_cmd2_i[1] ; clk ; 0.195 ; -0.266 ; Rise ; clk ; -; mbus_cmd2_i[2] ; clk ; 0.154 ; -0.254 ; Rise ; clk ; -; mbus_cmd3_i[*] ; clk ; 0.219 ; -0.213 ; Rise ; clk ; -; mbus_cmd3_i[0] ; clk ; 0.219 ; -0.213 ; Rise ; clk ; -; mbus_cmd3_i[1] ; clk ; 0.164 ; -0.308 ; Rise ; clk ; -; mbus_cmd3_i[2] ; clk ; 0.103 ; -0.361 ; Rise ; clk ; -+-------------------+------------+--------+--------+------------+-----------------+ - - -+------------------------------------------------------------------------------+ -; Clock to Output Times ; -+------------------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+------------------+------------+-------+-------+------------+-----------------+ -; cbus_addr_o[*] ; clk ; 3.729 ; 3.742 ; Rise ; clk ; -; cbus_addr_o[0] ; clk ; 3.672 ; 3.667 ; Rise ; clk ; -; cbus_addr_o[1] ; clk ; 3.674 ; 3.687 ; Rise ; clk ; -; cbus_addr_o[2] ; clk ; 3.649 ; 3.644 ; Rise ; clk ; -; cbus_addr_o[3] ; clk ; 3.640 ; 3.635 ; Rise ; clk ; -; cbus_addr_o[4] ; clk ; 3.661 ; 3.656 ; Rise ; clk ; -; cbus_addr_o[5] ; clk ; 3.632 ; 3.627 ; Rise ; clk ; -; cbus_addr_o[6] ; clk ; 3.671 ; 3.666 ; Rise ; clk ; -; cbus_addr_o[7] ; clk ; 3.695 ; 3.708 ; Rise ; clk ; -; cbus_addr_o[8] ; clk ; 3.659 ; 3.672 ; Rise ; clk ; -; cbus_addr_o[9] ; clk ; 3.650 ; 3.645 ; Rise ; clk ; -; cbus_addr_o[10] ; clk ; 3.684 ; 3.697 ; Rise ; clk ; -; cbus_addr_o[11] ; clk ; 3.643 ; 3.638 ; Rise ; clk ; -; cbus_addr_o[12] ; clk ; 3.729 ; 3.742 ; Rise ; clk ; -; cbus_addr_o[13] ; clk ; 3.634 ; 3.629 ; Rise ; clk ; -; cbus_addr_o[14] ; clk ; 3.669 ; 3.682 ; Rise ; clk ; -; cbus_addr_o[15] ; clk ; 3.678 ; 3.691 ; Rise ; clk ; -; cbus_addr_o[16] ; clk ; 3.683 ; 3.696 ; Rise ; clk ; -; cbus_addr_o[17] ; clk ; 3.651 ; 3.646 ; Rise ; clk ; -; cbus_addr_o[18] ; clk ; 3.651 ; 3.646 ; Rise ; clk ; -; cbus_addr_o[19] ; clk ; 3.653 ; 3.648 ; Rise ; clk ; -; cbus_addr_o[20] ; clk ; 3.659 ; 3.654 ; Rise ; clk ; -; cbus_addr_o[21] ; clk ; 3.641 ; 3.636 ; Rise ; clk ; -; cbus_addr_o[22] ; clk ; 3.659 ; 3.654 ; Rise ; clk ; -; cbus_addr_o[23] ; clk ; 3.646 ; 3.641 ; Rise ; clk ; -; cbus_addr_o[24] ; clk ; 3.654 ; 3.649 ; Rise ; clk ; -; cbus_addr_o[25] ; clk ; 3.656 ; 3.649 ; Rise ; clk ; -; cbus_addr_o[26] ; clk ; 3.651 ; 3.646 ; Rise ; clk ; -; cbus_addr_o[27] ; clk ; 3.681 ; 3.676 ; Rise ; clk ; -; cbus_addr_o[28] ; clk ; 3.653 ; 3.648 ; Rise ; clk ; -; cbus_addr_o[29] ; clk ; 3.674 ; 3.669 ; Rise ; clk ; -; cbus_addr_o[30] ; clk ; 3.682 ; 3.695 ; Rise ; clk ; -; cbus_addr_o[31] ; clk ; 3.643 ; 3.638 ; Rise ; clk ; -; cbus_cmd0_o[*] ; clk ; 5.470 ; 5.504 ; Rise ; clk ; -; cbus_cmd0_o[0] ; clk ; 5.470 ; 5.266 ; Rise ; clk ; -; cbus_cmd0_o[1] ; clk ; 5.384 ; 5.504 ; Rise ; clk ; -; cbus_cmd0_o[2] ; clk ; 5.253 ; 5.437 ; Rise ; clk ; -; cbus_cmd1_o[*] ; clk ; 5.562 ; 5.474 ; Rise ; clk ; -; cbus_cmd1_o[0] ; clk ; 5.562 ; 5.359 ; Rise ; clk ; -; cbus_cmd1_o[1] ; clk ; 5.382 ; 5.474 ; Rise ; clk ; -; cbus_cmd1_o[2] ; clk ; 5.227 ; 5.272 ; Rise ; clk ; -; cbus_cmd2_o[*] ; clk ; 5.454 ; 5.506 ; Rise ; clk ; -; cbus_cmd2_o[0] ; clk ; 5.389 ; 5.178 ; Rise ; clk ; -; cbus_cmd2_o[1] ; clk ; 5.401 ; 5.494 ; Rise ; clk ; -; cbus_cmd2_o[2] ; clk ; 5.454 ; 5.506 ; Rise ; clk ; -; cbus_cmd3_o[*] ; clk ; 5.311 ; 5.414 ; Rise ; clk ; -; cbus_cmd3_o[0] ; clk ; 5.311 ; 5.118 ; Rise ; clk ; -; cbus_cmd3_o[1] ; clk ; 5.180 ; 5.254 ; Rise ; clk ; -; cbus_cmd3_o[2] ; clk ; 5.216 ; 5.414 ; Rise ; clk ; -; mbus_ack0_o ; clk ; 3.648 ; 3.643 ; Rise ; clk ; -; mbus_ack1_o ; clk ; 3.654 ; 3.649 ; Rise ; clk ; -; mbus_ack2_o ; clk ; 3.663 ; 3.676 ; Rise ; clk ; -; mbus_ack3_o ; clk ; 3.671 ; 3.684 ; Rise ; clk ; -+------------------+------------+-------+-------+------------+-----------------+ - - -+------------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+------------------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+------------------+------------+-------+-------+------------+-----------------+ -; cbus_addr_o[*] ; clk ; 3.558 ; 3.553 ; Rise ; clk ; -; cbus_addr_o[0] ; clk ; 3.597 ; 3.592 ; Rise ; clk ; -; cbus_addr_o[1] ; clk ; 3.599 ; 3.612 ; Rise ; clk ; -; cbus_addr_o[2] ; clk ; 3.575 ; 3.570 ; Rise ; clk ; -; cbus_addr_o[3] ; clk ; 3.565 ; 3.560 ; Rise ; clk ; -; cbus_addr_o[4] ; clk ; 3.587 ; 3.582 ; Rise ; clk ; -; cbus_addr_o[5] ; clk ; 3.558 ; 3.553 ; Rise ; clk ; -; cbus_addr_o[6] ; clk ; 3.597 ; 3.592 ; Rise ; clk ; -; cbus_addr_o[7] ; clk ; 3.621 ; 3.634 ; Rise ; clk ; -; cbus_addr_o[8] ; clk ; 3.586 ; 3.599 ; Rise ; clk ; -; cbus_addr_o[9] ; clk ; 3.575 ; 3.570 ; Rise ; clk ; -; cbus_addr_o[10] ; clk ; 3.609 ; 3.622 ; Rise ; clk ; -; cbus_addr_o[11] ; clk ; 3.568 ; 3.563 ; Rise ; clk ; -; cbus_addr_o[12] ; clk ; 3.655 ; 3.668 ; Rise ; clk ; -; cbus_addr_o[13] ; clk ; 3.559 ; 3.554 ; Rise ; clk ; -; cbus_addr_o[14] ; clk ; 3.595 ; 3.608 ; Rise ; clk ; -; cbus_addr_o[15] ; clk ; 3.605 ; 3.618 ; Rise ; clk ; -; cbus_addr_o[16] ; clk ; 3.609 ; 3.622 ; Rise ; clk ; -; cbus_addr_o[17] ; clk ; 3.576 ; 3.571 ; Rise ; clk ; -; cbus_addr_o[18] ; clk ; 3.577 ; 3.572 ; Rise ; clk ; -; cbus_addr_o[19] ; clk ; 3.578 ; 3.573 ; Rise ; clk ; -; cbus_addr_o[20] ; clk ; 3.585 ; 3.580 ; Rise ; clk ; -; cbus_addr_o[21] ; clk ; 3.568 ; 3.563 ; Rise ; clk ; -; cbus_addr_o[22] ; clk ; 3.584 ; 3.579 ; Rise ; clk ; -; cbus_addr_o[23] ; clk ; 3.572 ; 3.567 ; Rise ; clk ; -; cbus_addr_o[24] ; clk ; 3.580 ; 3.575 ; Rise ; clk ; -; cbus_addr_o[25] ; clk ; 3.581 ; 3.574 ; Rise ; clk ; -; cbus_addr_o[26] ; clk ; 3.578 ; 3.573 ; Rise ; clk ; -; cbus_addr_o[27] ; clk ; 3.606 ; 3.601 ; Rise ; clk ; -; cbus_addr_o[28] ; clk ; 3.578 ; 3.573 ; Rise ; clk ; -; cbus_addr_o[29] ; clk ; 3.599 ; 3.594 ; Rise ; clk ; -; cbus_addr_o[30] ; clk ; 3.608 ; 3.621 ; Rise ; clk ; -; cbus_addr_o[31] ; clk ; 3.568 ; 3.563 ; Rise ; clk ; -; cbus_cmd0_o[*] ; clk ; 4.669 ; 4.778 ; Rise ; clk ; -; cbus_cmd0_o[0] ; clk ; 4.838 ; 4.778 ; Rise ; clk ; -; cbus_cmd0_o[1] ; clk ; 4.779 ; 4.946 ; Rise ; clk ; -; cbus_cmd0_o[2] ; clk ; 4.669 ; 4.820 ; Rise ; clk ; -; cbus_cmd1_o[*] ; clk ; 4.602 ; 4.661 ; Rise ; clk ; -; cbus_cmd1_o[0] ; clk ; 5.035 ; 4.954 ; Rise ; clk ; -; cbus_cmd1_o[1] ; clk ; 4.821 ; 4.952 ; Rise ; clk ; -; cbus_cmd1_o[2] ; clk ; 4.602 ; 4.661 ; Rise ; clk ; -; cbus_cmd2_o[*] ; clk ; 4.875 ; 4.830 ; Rise ; clk ; -; cbus_cmd2_o[0] ; clk ; 4.886 ; 4.830 ; Rise ; clk ; -; cbus_cmd2_o[1] ; clk ; 4.889 ; 5.045 ; Rise ; clk ; -; cbus_cmd2_o[2] ; clk ; 4.875 ; 4.927 ; Rise ; clk ; -; cbus_cmd3_o[*] ; clk ; 4.709 ; 4.804 ; Rise ; clk ; -; cbus_cmd3_o[0] ; clk ; 4.899 ; 4.804 ; Rise ; clk ; -; cbus_cmd3_o[1] ; clk ; 4.709 ; 4.814 ; Rise ; clk ; -; cbus_cmd3_o[2] ; clk ; 4.727 ; 4.868 ; Rise ; clk ; -; mbus_ack0_o ; clk ; 3.573 ; 3.568 ; Rise ; clk ; -; mbus_ack1_o ; clk ; 3.579 ; 3.574 ; Rise ; clk ; -; mbus_ack2_o ; clk ; 3.589 ; 3.602 ; Rise ; clk ; -; mbus_ack3_o ; clk ; 3.597 ; 3.610 ; Rise ; clk ; -+------------------+------------+-------+-------+------------+-----------------+ - - ---------------------------------------------- -; Fast 1200mV 0C Model Metastability Report ; ---------------------------------------------- -No synchronizer chains to report. - - -+----------------------------------------------------------------------------------+ -; Multicorner Timing Analysis Summary ; -+------------------+-----------+--------+----------+---------+---------------------+ -; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; -+------------------+-----------+--------+----------+---------+---------------------+ -; Worst-case Slack ; -8.340 ; -0.278 ; N/A ; N/A ; -3.000 ; -; clk ; -8.340 ; -0.278 ; N/A ; N/A ; -3.000 ; -; Design-wide TNS ; -2724.862 ; -3.47 ; 0.0 ; 0.0 ; -651.247 ; -; clk ; -2724.862 ; -3.470 ; N/A ; N/A ; -651.247 ; -+------------------+-----------+--------+----------+---------+---------------------+ - - -+-------------------------------------------------------------------------------+ -; Setup Times ; -+-------------------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-------------------+------------+-------+-------+------------+-----------------+ -; cbus_ack0_i ; clk ; 0.517 ; 0.748 ; Rise ; clk ; -; cbus_ack1_i ; clk ; 0.631 ; 0.820 ; Rise ; clk ; -; cbus_ack2_i ; clk ; 0.850 ; 0.811 ; Rise ; clk ; -; cbus_ack3_i ; clk ; 0.769 ; 0.740 ; Rise ; clk ; -; mbus_addr0_i[*] ; clk ; 0.799 ; 0.938 ; Rise ; clk ; -; mbus_addr0_i[0] ; clk ; 0.644 ; 0.872 ; Rise ; clk ; -; mbus_addr0_i[1] ; clk ; 0.558 ; 0.779 ; Rise ; clk ; -; mbus_addr0_i[2] ; clk ; 0.651 ; 0.885 ; Rise ; clk ; -; mbus_addr0_i[3] ; clk ; 0.611 ; 0.829 ; Rise ; clk ; -; mbus_addr0_i[4] ; clk ; 0.662 ; 0.895 ; Rise ; clk ; -; mbus_addr0_i[5] ; clk ; 0.583 ; 0.800 ; Rise ; clk ; -; mbus_addr0_i[6] ; clk ; 0.630 ; 0.862 ; Rise ; clk ; -; mbus_addr0_i[7] ; clk ; 0.518 ; 0.868 ; Rise ; clk ; -; mbus_addr0_i[8] ; clk ; 0.528 ; 0.883 ; Rise ; clk ; -; mbus_addr0_i[9] ; clk ; 0.608 ; 0.833 ; Rise ; clk ; -; mbus_addr0_i[10] ; clk ; 0.626 ; 0.835 ; Rise ; clk ; -; mbus_addr0_i[11] ; clk ; 0.690 ; 0.871 ; Rise ; clk ; -; mbus_addr0_i[12] ; clk ; 0.456 ; 0.742 ; Rise ; clk ; -; mbus_addr0_i[13] ; clk ; 0.603 ; 0.781 ; Rise ; clk ; -; mbus_addr0_i[14] ; clk ; 0.618 ; 0.854 ; Rise ; clk ; -; mbus_addr0_i[15] ; clk ; 0.560 ; 0.938 ; Rise ; clk ; -; mbus_addr0_i[16] ; clk ; 0.569 ; 0.788 ; Rise ; clk ; -; mbus_addr0_i[17] ; clk ; 0.799 ; 0.824 ; Rise ; clk ; -; mbus_addr0_i[18] ; clk ; 0.631 ; 0.882 ; Rise ; clk ; -; mbus_addr0_i[19] ; clk ; 0.616 ; 0.845 ; Rise ; clk ; -; mbus_addr0_i[20] ; clk ; 0.579 ; 0.807 ; Rise ; clk ; -; mbus_addr0_i[21] ; clk ; 0.451 ; 0.745 ; Rise ; clk ; -; mbus_addr0_i[22] ; clk ; 0.428 ; 0.709 ; Rise ; clk ; -; mbus_addr0_i[23] ; clk ; 0.636 ; 0.846 ; Rise ; clk ; -; mbus_addr0_i[24] ; clk ; 0.637 ; 0.864 ; Rise ; clk ; -; mbus_addr0_i[25] ; clk ; 0.543 ; 0.802 ; Rise ; clk ; -; mbus_addr0_i[26] ; clk ; 0.521 ; 0.784 ; Rise ; clk ; -; mbus_addr0_i[27] ; clk ; 0.650 ; 0.888 ; Rise ; clk ; -; mbus_addr0_i[28] ; clk ; 0.565 ; 0.761 ; Rise ; clk ; -; mbus_addr0_i[29] ; clk ; 0.438 ; 0.740 ; Rise ; clk ; -; mbus_addr0_i[30] ; clk ; 0.511 ; 0.853 ; Rise ; clk ; -; mbus_addr0_i[31] ; clk ; 0.529 ; 0.756 ; Rise ; clk ; -; mbus_addr1_i[*] ; clk ; 0.890 ; 1.090 ; Rise ; clk ; -; mbus_addr1_i[0] ; clk ; 0.549 ; 0.741 ; Rise ; clk ; -; mbus_addr1_i[1] ; clk ; 0.638 ; 0.900 ; Rise ; clk ; -; mbus_addr1_i[2] ; clk ; 0.543 ; 0.800 ; Rise ; clk ; -; mbus_addr1_i[3] ; clk ; 0.644 ; 0.883 ; Rise ; clk ; -; mbus_addr1_i[4] ; clk ; 0.517 ; 0.839 ; Rise ; clk ; -; mbus_addr1_i[5] ; clk ; 0.475 ; 0.818 ; Rise ; clk ; -; mbus_addr1_i[6] ; clk ; 0.715 ; 0.940 ; Rise ; clk ; -; mbus_addr1_i[7] ; clk ; 0.603 ; 0.934 ; Rise ; clk ; -; mbus_addr1_i[8] ; clk ; 0.549 ; 0.787 ; Rise ; clk ; -; mbus_addr1_i[9] ; clk ; 0.451 ; 0.769 ; Rise ; clk ; -; mbus_addr1_i[10] ; clk ; 0.450 ; 0.760 ; Rise ; clk ; -; mbus_addr1_i[11] ; clk ; 0.589 ; 0.838 ; Rise ; clk ; -; mbus_addr1_i[12] ; clk ; 0.375 ; 0.670 ; Rise ; clk ; -; mbus_addr1_i[13] ; clk ; 0.547 ; 0.781 ; Rise ; clk ; -; mbus_addr1_i[14] ; clk ; 0.649 ; 0.823 ; Rise ; clk ; -; mbus_addr1_i[15] ; clk ; 0.832 ; 1.040 ; Rise ; clk ; -; mbus_addr1_i[16] ; clk ; 0.535 ; 0.778 ; Rise ; clk ; -; mbus_addr1_i[17] ; clk ; 0.634 ; 0.728 ; Rise ; clk ; -; mbus_addr1_i[18] ; clk ; 0.693 ; 0.783 ; Rise ; clk ; -; mbus_addr1_i[19] ; clk ; 0.617 ; 0.793 ; Rise ; clk ; -; mbus_addr1_i[20] ; clk ; 0.559 ; 0.810 ; Rise ; clk ; -; mbus_addr1_i[21] ; clk ; 0.639 ; 0.795 ; Rise ; clk ; -; mbus_addr1_i[22] ; clk ; 0.491 ; 0.696 ; Rise ; clk ; -; mbus_addr1_i[23] ; clk ; 0.444 ; 0.746 ; Rise ; clk ; -; mbus_addr1_i[24] ; clk ; 0.528 ; 0.763 ; Rise ; clk ; -; mbus_addr1_i[25] ; clk ; 0.890 ; 1.090 ; Rise ; clk ; -; mbus_addr1_i[26] ; clk ; 0.501 ; 0.818 ; Rise ; clk ; -; mbus_addr1_i[27] ; clk ; 0.451 ; 0.721 ; Rise ; clk ; -; mbus_addr1_i[28] ; clk ; 0.453 ; 0.655 ; Rise ; clk ; -; mbus_addr1_i[29] ; clk ; 0.641 ; 0.894 ; Rise ; clk ; -; mbus_addr1_i[30] ; clk ; 0.542 ; 0.828 ; Rise ; clk ; -; mbus_addr1_i[31] ; clk ; 0.628 ; 0.873 ; Rise ; clk ; -; mbus_addr2_i[*] ; clk ; 0.807 ; 1.054 ; Rise ; clk ; -; mbus_addr2_i[0] ; clk ; 0.560 ; 0.846 ; Rise ; clk ; -; mbus_addr2_i[1] ; clk ; 0.588 ; 0.802 ; Rise ; clk ; -; mbus_addr2_i[2] ; clk ; 0.568 ; 0.794 ; Rise ; clk ; -; mbus_addr2_i[3] ; clk ; 0.371 ; 0.687 ; Rise ; clk ; -; mbus_addr2_i[4] ; clk ; 0.409 ; 0.777 ; Rise ; clk ; -; mbus_addr2_i[5] ; clk ; 0.435 ; 0.748 ; Rise ; clk ; -; mbus_addr2_i[6] ; clk ; 0.476 ; 0.741 ; Rise ; clk ; -; mbus_addr2_i[7] ; clk ; 0.570 ; 0.694 ; Rise ; clk ; -; mbus_addr2_i[8] ; clk ; 0.459 ; 0.775 ; Rise ; clk ; -; mbus_addr2_i[9] ; clk ; 0.415 ; 0.702 ; Rise ; clk ; -; mbus_addr2_i[10] ; clk ; 0.685 ; 0.918 ; Rise ; clk ; -; mbus_addr2_i[11] ; clk ; 0.613 ; 0.857 ; Rise ; clk ; -; mbus_addr2_i[12] ; clk ; 0.497 ; 0.854 ; Rise ; clk ; -; mbus_addr2_i[13] ; clk ; 0.515 ; 0.852 ; Rise ; clk ; -; mbus_addr2_i[14] ; clk ; 0.533 ; 0.780 ; Rise ; clk ; -; mbus_addr2_i[15] ; clk ; 0.538 ; 0.787 ; Rise ; clk ; -; mbus_addr2_i[16] ; clk ; 0.661 ; 0.868 ; Rise ; clk ; -; mbus_addr2_i[17] ; clk ; 0.463 ; 0.790 ; Rise ; clk ; -; mbus_addr2_i[18] ; clk ; 0.496 ; 0.821 ; Rise ; clk ; -; mbus_addr2_i[19] ; clk ; 0.557 ; 0.732 ; Rise ; clk ; -; mbus_addr2_i[20] ; clk ; 0.559 ; 0.661 ; Rise ; clk ; -; mbus_addr2_i[21] ; clk ; 0.572 ; 0.802 ; Rise ; clk ; -; mbus_addr2_i[22] ; clk ; 0.460 ; 0.790 ; Rise ; clk ; -; mbus_addr2_i[23] ; clk ; 0.605 ; 0.863 ; Rise ; clk ; -; mbus_addr2_i[24] ; clk ; 0.509 ; 0.724 ; Rise ; clk ; -; mbus_addr2_i[25] ; clk ; 0.462 ; 0.818 ; Rise ; clk ; -; mbus_addr2_i[26] ; clk ; 0.545 ; 0.805 ; Rise ; clk ; -; mbus_addr2_i[27] ; clk ; 0.807 ; 1.054 ; Rise ; clk ; -; mbus_addr2_i[28] ; clk ; 0.483 ; 0.829 ; Rise ; clk ; -; mbus_addr2_i[29] ; clk ; 0.605 ; 0.872 ; Rise ; clk ; -; mbus_addr2_i[30] ; clk ; 0.564 ; 0.774 ; Rise ; clk ; -; mbus_addr2_i[31] ; clk ; 0.693 ; 0.961 ; Rise ; clk ; -; mbus_addr3_i[*] ; clk ; 0.786 ; 1.045 ; Rise ; clk ; -; mbus_addr3_i[0] ; clk ; 0.629 ; 0.860 ; Rise ; clk ; -; mbus_addr3_i[1] ; clk ; 0.581 ; 0.796 ; Rise ; clk ; -; mbus_addr3_i[2] ; clk ; 0.621 ; 0.884 ; Rise ; clk ; -; mbus_addr3_i[3] ; clk ; 0.672 ; 0.844 ; Rise ; clk ; -; mbus_addr3_i[4] ; clk ; 0.669 ; 0.899 ; Rise ; clk ; -; mbus_addr3_i[5] ; clk ; 0.512 ; 0.843 ; Rise ; clk ; -; mbus_addr3_i[6] ; clk ; 0.570 ; 0.812 ; Rise ; clk ; -; mbus_addr3_i[7] ; clk ; 0.786 ; 1.045 ; Rise ; clk ; -; mbus_addr3_i[8] ; clk ; 0.591 ; 0.834 ; Rise ; clk ; -; mbus_addr3_i[9] ; clk ; 0.619 ; 0.824 ; Rise ; clk ; -; mbus_addr3_i[10] ; clk ; 0.608 ; 0.858 ; Rise ; clk ; -; mbus_addr3_i[11] ; clk ; 0.662 ; 0.889 ; Rise ; clk ; -; mbus_addr3_i[12] ; clk ; 0.536 ; 0.869 ; Rise ; clk ; -; mbus_addr3_i[13] ; clk ; 0.614 ; 0.800 ; Rise ; clk ; -; mbus_addr3_i[14] ; clk ; 0.522 ; 0.814 ; Rise ; clk ; -; mbus_addr3_i[15] ; clk ; 0.562 ; 0.781 ; Rise ; clk ; -; mbus_addr3_i[16] ; clk ; 0.692 ; 0.856 ; Rise ; clk ; -; mbus_addr3_i[17] ; clk ; 0.577 ; 0.835 ; Rise ; clk ; -; mbus_addr3_i[18] ; clk ; 0.655 ; 0.886 ; Rise ; clk ; -; mbus_addr3_i[19] ; clk ; 0.679 ; 0.959 ; Rise ; clk ; -; mbus_addr3_i[20] ; clk ; 0.615 ; 0.859 ; Rise ; clk ; -; mbus_addr3_i[21] ; clk ; 0.555 ; 0.787 ; Rise ; clk ; -; mbus_addr3_i[22] ; clk ; 0.647 ; 0.794 ; Rise ; clk ; -; mbus_addr3_i[23] ; clk ; 0.526 ; 0.847 ; Rise ; clk ; -; mbus_addr3_i[24] ; clk ; 0.603 ; 0.872 ; Rise ; clk ; -; mbus_addr3_i[25] ; clk ; 0.515 ; 0.803 ; Rise ; clk ; -; mbus_addr3_i[26] ; clk ; 0.613 ; 0.973 ; Rise ; clk ; -; mbus_addr3_i[27] ; clk ; 0.716 ; 0.926 ; Rise ; clk ; -; mbus_addr3_i[28] ; clk ; 0.586 ; 0.804 ; Rise ; clk ; -; mbus_addr3_i[29] ; clk ; 0.730 ; 0.952 ; Rise ; clk ; -; mbus_addr3_i[30] ; clk ; 0.514 ; 0.807 ; Rise ; clk ; -; mbus_addr3_i[31] ; clk ; 0.535 ; 0.885 ; Rise ; clk ; -; mbus_cmd0_i[*] ; clk ; 0.746 ; 0.907 ; Rise ; clk ; -; mbus_cmd0_i[0] ; clk ; 0.654 ; 0.838 ; Rise ; clk ; -; mbus_cmd0_i[1] ; clk ; 0.746 ; 0.907 ; Rise ; clk ; -; mbus_cmd0_i[2] ; clk ; 0.602 ; 0.752 ; Rise ; clk ; -; mbus_cmd1_i[*] ; clk ; 0.803 ; 1.064 ; Rise ; clk ; -; mbus_cmd1_i[0] ; clk ; 0.731 ; 0.996 ; Rise ; clk ; -; mbus_cmd1_i[1] ; clk ; 0.621 ; 0.908 ; Rise ; clk ; -; mbus_cmd1_i[2] ; clk ; 0.803 ; 1.064 ; Rise ; clk ; -; mbus_cmd2_i[*] ; clk ; 0.643 ; 0.788 ; Rise ; clk ; -; mbus_cmd2_i[0] ; clk ; 0.594 ; 0.775 ; Rise ; clk ; -; mbus_cmd2_i[1] ; clk ; 0.633 ; 0.735 ; Rise ; clk ; -; mbus_cmd2_i[2] ; clk ; 0.643 ; 0.788 ; Rise ; clk ; -; mbus_cmd3_i[*] ; clk ; 0.687 ; 0.970 ; Rise ; clk ; -; mbus_cmd3_i[0] ; clk ; 0.630 ; 0.950 ; Rise ; clk ; -; mbus_cmd3_i[1] ; clk ; 0.642 ; 0.863 ; Rise ; clk ; -; mbus_cmd3_i[2] ; clk ; 0.687 ; 0.970 ; Rise ; clk ; -+-------------------+------------+-------+-------+------------+-----------------+ - - -+---------------------------------------------------------------------------------+ -; Hold Times ; -+-------------------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-------------------+------------+--------+--------+------------+-----------------+ -; cbus_ack0_i ; clk ; 0.154 ; -0.198 ; Rise ; clk ; -; cbus_ack1_i ; clk ; 0.123 ; -0.265 ; Rise ; clk ; -; cbus_ack2_i ; clk ; -0.133 ; -0.341 ; Rise ; clk ; -; cbus_ack3_i ; clk ; -0.062 ; -0.135 ; Rise ; clk ; -; mbus_addr0_i[*] ; clk ; 0.193 ; -0.103 ; Rise ; clk ; -; mbus_addr0_i[0] ; clk ; 0.011 ; -0.372 ; Rise ; clk ; -; mbus_addr0_i[1] ; clk ; 0.063 ; -0.265 ; Rise ; clk ; -; mbus_addr0_i[2] ; clk ; 0.074 ; -0.265 ; Rise ; clk ; -; mbus_addr0_i[3] ; clk ; 0.055 ; -0.267 ; Rise ; clk ; -; mbus_addr0_i[4] ; clk ; 0.037 ; -0.296 ; Rise ; clk ; -; mbus_addr0_i[5] ; clk ; 0.017 ; -0.338 ; Rise ; clk ; -; mbus_addr0_i[6] ; clk ; 0.006 ; -0.358 ; Rise ; clk ; -; mbus_addr0_i[7] ; clk ; 0.184 ; -0.200 ; Rise ; clk ; -; mbus_addr0_i[8] ; clk ; 0.158 ; -0.171 ; Rise ; clk ; -; mbus_addr0_i[9] ; clk ; 0.063 ; -0.241 ; Rise ; clk ; -; mbus_addr0_i[10] ; clk ; 0.019 ; -0.330 ; Rise ; clk ; -; mbus_addr0_i[11] ; clk ; 0.055 ; -0.325 ; Rise ; clk ; -; mbus_addr0_i[12] ; clk ; 0.105 ; -0.251 ; Rise ; clk ; -; mbus_addr0_i[13] ; clk ; 0.094 ; -0.250 ; Rise ; clk ; -; mbus_addr0_i[14] ; clk ; 0.029 ; -0.319 ; Rise ; clk ; -; mbus_addr0_i[15] ; clk ; 0.148 ; -0.201 ; Rise ; clk ; -; mbus_addr0_i[16] ; clk ; 0.061 ; -0.268 ; Rise ; clk ; -; mbus_addr0_i[17] ; clk ; -0.185 ; -0.322 ; Rise ; clk ; -; mbus_addr0_i[18] ; clk ; 0.085 ; -0.219 ; Rise ; clk ; -; mbus_addr0_i[19] ; clk ; 0.083 ; -0.222 ; Rise ; clk ; -; mbus_addr0_i[20] ; clk ; 0.078 ; -0.215 ; Rise ; clk ; -; mbus_addr0_i[21] ; clk ; 0.138 ; -0.181 ; Rise ; clk ; -; mbus_addr0_i[22] ; clk ; 0.122 ; -0.231 ; Rise ; clk ; -; mbus_addr0_i[23] ; clk ; 0.028 ; -0.291 ; Rise ; clk ; -; mbus_addr0_i[24] ; clk ; -0.002 ; -0.372 ; Rise ; clk ; -; mbus_addr0_i[25] ; clk ; 0.056 ; -0.237 ; Rise ; clk ; -; mbus_addr0_i[26] ; clk ; 0.063 ; -0.256 ; Rise ; clk ; -; mbus_addr0_i[27] ; clk ; 0.053 ; -0.266 ; Rise ; clk ; -; mbus_addr0_i[28] ; clk ; 0.070 ; -0.251 ; Rise ; clk ; -; mbus_addr0_i[29] ; clk ; 0.091 ; -0.257 ; Rise ; clk ; -; mbus_addr0_i[30] ; clk ; 0.193 ; -0.103 ; Rise ; clk ; -; mbus_addr0_i[31] ; clk ; 0.052 ; -0.301 ; Rise ; clk ; -; mbus_addr1_i[*] ; clk ; 0.378 ; 0.156 ; Rise ; clk ; -; mbus_addr1_i[0] ; clk ; 0.131 ; -0.242 ; Rise ; clk ; -; mbus_addr1_i[1] ; clk ; 0.070 ; -0.320 ; Rise ; clk ; -; mbus_addr1_i[2] ; clk ; 0.075 ; -0.323 ; Rise ; clk ; -; mbus_addr1_i[3] ; clk ; 0.046 ; -0.331 ; Rise ; clk ; -; mbus_addr1_i[4] ; clk ; 0.207 ; -0.126 ; Rise ; clk ; -; mbus_addr1_i[5] ; clk ; 0.194 ; -0.146 ; Rise ; clk ; -; mbus_addr1_i[6] ; clk ; 0.058 ; -0.324 ; Rise ; clk ; -; mbus_addr1_i[7] ; clk ; 0.378 ; 0.156 ; Rise ; clk ; -; mbus_addr1_i[8] ; clk ; 0.073 ; -0.286 ; Rise ; clk ; -; mbus_addr1_i[9] ; clk ; 0.149 ; -0.191 ; Rise ; clk ; -; mbus_addr1_i[10] ; clk ; 0.147 ; -0.183 ; Rise ; clk ; -; mbus_addr1_i[11] ; clk ; 0.080 ; -0.245 ; Rise ; clk ; -; mbus_addr1_i[12] ; clk ; 0.161 ; -0.160 ; Rise ; clk ; -; mbus_addr1_i[13] ; clk ; 0.066 ; -0.287 ; Rise ; clk ; -; mbus_addr1_i[14] ; clk ; 0.078 ; -0.266 ; Rise ; clk ; -; mbus_addr1_i[15] ; clk ; 0.066 ; -0.264 ; Rise ; clk ; -; mbus_addr1_i[16] ; clk ; 0.079 ; -0.279 ; Rise ; clk ; -; mbus_addr1_i[17] ; clk ; -0.129 ; -0.318 ; Rise ; clk ; -; mbus_addr1_i[18] ; clk ; -0.097 ; -0.292 ; Rise ; clk ; -; mbus_addr1_i[19] ; clk ; 0.051 ; -0.308 ; Rise ; clk ; -; mbus_addr1_i[20] ; clk ; 0.090 ; -0.251 ; Rise ; clk ; -; mbus_addr1_i[21] ; clk ; 0.010 ; -0.350 ; Rise ; clk ; -; mbus_addr1_i[22] ; clk ; 0.127 ; -0.173 ; Rise ; clk ; -; mbus_addr1_i[23] ; clk ; 0.123 ; -0.260 ; Rise ; clk ; -; mbus_addr1_i[24] ; clk ; 0.102 ; -0.268 ; Rise ; clk ; -; mbus_addr1_i[25] ; clk ; 0.113 ; -0.196 ; Rise ; clk ; -; mbus_addr1_i[26] ; clk ; 0.095 ; -0.291 ; Rise ; clk ; -; mbus_addr1_i[27] ; clk ; 0.221 ; -0.100 ; Rise ; clk ; -; mbus_addr1_i[28] ; clk ; 0.096 ; -0.203 ; Rise ; clk ; -; mbus_addr1_i[29] ; clk ; 0.086 ; -0.252 ; Rise ; clk ; -; mbus_addr1_i[30] ; clk ; 0.142 ; -0.170 ; Rise ; clk ; -; mbus_addr1_i[31] ; clk ; 0.128 ; -0.188 ; Rise ; clk ; -; mbus_addr2_i[*] ; clk ; 0.183 ; -0.157 ; Rise ; clk ; -; mbus_addr2_i[0] ; clk ; 0.071 ; -0.233 ; Rise ; clk ; -; mbus_addr2_i[1] ; clk ; 0.002 ; -0.324 ; Rise ; clk ; -; mbus_addr2_i[2] ; clk ; 0.097 ; -0.249 ; Rise ; clk ; -; mbus_addr2_i[3] ; clk ; 0.142 ; -0.211 ; Rise ; clk ; -; mbus_addr2_i[4] ; clk ; 0.145 ; -0.234 ; Rise ; clk ; -; mbus_addr2_i[5] ; clk ; 0.131 ; -0.269 ; Rise ; clk ; -; mbus_addr2_i[6] ; clk ; 0.133 ; -0.226 ; Rise ; clk ; -; mbus_addr2_i[7] ; clk ; 0.081 ; -0.167 ; Rise ; clk ; -; mbus_addr2_i[8] ; clk ; 0.055 ; -0.274 ; Rise ; clk ; -; mbus_addr2_i[9] ; clk ; 0.088 ; -0.250 ; Rise ; clk ; -; mbus_addr2_i[10] ; clk ; 0.020 ; -0.337 ; Rise ; clk ; -; mbus_addr2_i[11] ; clk ; 0.045 ; -0.347 ; Rise ; clk ; -; mbus_addr2_i[12] ; clk ; 0.127 ; -0.253 ; Rise ; clk ; -; mbus_addr2_i[13] ; clk ; 0.071 ; -0.336 ; Rise ; clk ; -; mbus_addr2_i[14] ; clk ; 0.099 ; -0.253 ; Rise ; clk ; -; mbus_addr2_i[15] ; clk ; 0.021 ; -0.334 ; Rise ; clk ; -; mbus_addr2_i[16] ; clk ; 0.071 ; -0.271 ; Rise ; clk ; -; mbus_addr2_i[17] ; clk ; 0.132 ; -0.274 ; Rise ; clk ; -; mbus_addr2_i[18] ; clk ; 0.118 ; -0.254 ; Rise ; clk ; -; mbus_addr2_i[19] ; clk ; -0.073 ; -0.245 ; Rise ; clk ; -; mbus_addr2_i[20] ; clk ; 0.085 ; -0.209 ; Rise ; clk ; -; mbus_addr2_i[21] ; clk ; 0.055 ; -0.331 ; Rise ; clk ; -; mbus_addr2_i[22] ; clk ; 0.183 ; -0.161 ; Rise ; clk ; -; mbus_addr2_i[23] ; clk ; 0.023 ; -0.387 ; Rise ; clk ; -; mbus_addr2_i[24] ; clk ; 0.107 ; -0.271 ; Rise ; clk ; -; mbus_addr2_i[25] ; clk ; 0.173 ; -0.157 ; Rise ; clk ; -; mbus_addr2_i[26] ; clk ; 0.072 ; -0.338 ; Rise ; clk ; -; mbus_addr2_i[27] ; clk ; 0.009 ; -0.388 ; Rise ; clk ; -; mbus_addr2_i[28] ; clk ; 0.115 ; -0.266 ; Rise ; clk ; -; mbus_addr2_i[29] ; clk ; 0.067 ; -0.329 ; Rise ; clk ; -; mbus_addr2_i[30] ; clk ; 0.070 ; -0.247 ; Rise ; clk ; -; mbus_addr2_i[31] ; clk ; -0.042 ; -0.471 ; Rise ; clk ; -; mbus_addr3_i[*] ; clk ; 0.182 ; -0.116 ; Rise ; clk ; -; mbus_addr3_i[0] ; clk ; -0.004 ; -0.379 ; Rise ; clk ; -; mbus_addr3_i[1] ; clk ; 0.060 ; -0.254 ; Rise ; clk ; -; mbus_addr3_i[2] ; clk ; 0.035 ; -0.324 ; Rise ; clk ; -; mbus_addr3_i[3] ; clk ; 0.021 ; -0.366 ; Rise ; clk ; -; mbus_addr3_i[4] ; clk ; -0.007 ; -0.424 ; Rise ; clk ; -; mbus_addr3_i[5] ; clk ; 0.111 ; -0.210 ; Rise ; clk ; -; mbus_addr3_i[6] ; clk ; 0.015 ; -0.341 ; Rise ; clk ; -; mbus_addr3_i[7] ; clk ; 0.128 ; -0.200 ; Rise ; clk ; -; mbus_addr3_i[8] ; clk ; 0.042 ; -0.344 ; Rise ; clk ; -; mbus_addr3_i[9] ; clk ; 0.097 ; -0.261 ; Rise ; clk ; -; mbus_addr3_i[10] ; clk ; 0.087 ; -0.265 ; Rise ; clk ; -; mbus_addr3_i[11] ; clk ; 0.182 ; -0.116 ; Rise ; clk ; -; mbus_addr3_i[12] ; clk ; 0.111 ; -0.220 ; Rise ; clk ; -; mbus_addr3_i[13] ; clk ; 0.034 ; -0.304 ; Rise ; clk ; -; mbus_addr3_i[14] ; clk ; 0.127 ; -0.251 ; Rise ; clk ; -; mbus_addr3_i[15] ; clk ; 0.065 ; -0.274 ; Rise ; clk ; -; mbus_addr3_i[16] ; clk ; 0.013 ; -0.282 ; Rise ; clk ; -; mbus_addr3_i[17] ; clk ; 0.028 ; -0.336 ; Rise ; clk ; -; mbus_addr3_i[18] ; clk ; 0.010 ; -0.333 ; Rise ; clk ; -; mbus_addr3_i[19] ; clk ; 0.100 ; -0.265 ; Rise ; clk ; -; mbus_addr3_i[20] ; clk ; 0.087 ; -0.250 ; Rise ; clk ; -; mbus_addr3_i[21] ; clk ; 0.088 ; -0.267 ; Rise ; clk ; -; mbus_addr3_i[22] ; clk ; 0.050 ; -0.310 ; Rise ; clk ; -; mbus_addr3_i[23] ; clk ; 0.079 ; -0.260 ; Rise ; clk ; -; mbus_addr3_i[24] ; clk ; -0.003 ; -0.396 ; Rise ; clk ; -; mbus_addr3_i[25] ; clk ; 0.052 ; -0.317 ; Rise ; clk ; -; mbus_addr3_i[26] ; clk ; 0.048 ; -0.354 ; Rise ; clk ; -; mbus_addr3_i[27] ; clk ; 0.103 ; -0.232 ; Rise ; clk ; -; mbus_addr3_i[28] ; clk ; 0.017 ; -0.335 ; Rise ; clk ; -; mbus_addr3_i[29] ; clk ; 0.099 ; -0.226 ; Rise ; clk ; -; mbus_addr3_i[30] ; clk ; 0.047 ; -0.333 ; Rise ; clk ; -; mbus_addr3_i[31] ; clk ; 0.060 ; -0.373 ; Rise ; clk ; -; mbus_cmd0_i[*] ; clk ; 0.186 ; -0.071 ; Rise ; clk ; -; mbus_cmd0_i[0] ; clk ; 0.163 ; -0.096 ; Rise ; clk ; -; mbus_cmd0_i[1] ; clk ; 0.106 ; -0.258 ; Rise ; clk ; -; mbus_cmd0_i[2] ; clk ; 0.186 ; -0.071 ; Rise ; clk ; -; mbus_cmd1_i[*] ; clk ; 0.257 ; -0.047 ; Rise ; clk ; -; mbus_cmd1_i[0] ; clk ; 0.157 ; -0.238 ; Rise ; clk ; -; mbus_cmd1_i[1] ; clk ; 0.257 ; -0.047 ; Rise ; clk ; -; mbus_cmd1_i[2] ; clk ; 0.195 ; -0.181 ; Rise ; clk ; -; mbus_cmd2_i[*] ; clk ; 0.195 ; -0.103 ; Rise ; clk ; -; mbus_cmd2_i[0] ; clk ; 0.157 ; -0.159 ; Rise ; clk ; -; mbus_cmd2_i[1] ; clk ; 0.195 ; -0.103 ; Rise ; clk ; -; mbus_cmd2_i[2] ; clk ; 0.154 ; -0.196 ; Rise ; clk ; -; mbus_cmd3_i[*] ; clk ; 0.219 ; -0.121 ; Rise ; clk ; -; mbus_cmd3_i[0] ; clk ; 0.219 ; -0.121 ; Rise ; clk ; -; mbus_cmd3_i[1] ; clk ; 0.164 ; -0.208 ; Rise ; clk ; -; mbus_cmd3_i[2] ; clk ; 0.103 ; -0.352 ; Rise ; clk ; -+-------------------+------------+--------+--------+------------+-----------------+ - - -+------------------------------------------------------------------------------+ -; Clock to Output Times ; -+------------------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+------------------+------------+-------+-------+------------+-----------------+ -; cbus_addr_o[*] ; clk ; 6.105 ; 6.062 ; Rise ; clk ; -; cbus_addr_o[0] ; clk ; 6.025 ; 5.982 ; Rise ; clk ; -; cbus_addr_o[1] ; clk ; 6.050 ; 6.007 ; Rise ; clk ; -; cbus_addr_o[2] ; clk ; 6.002 ; 5.959 ; Rise ; clk ; -; cbus_addr_o[3] ; clk ; 5.992 ; 5.949 ; Rise ; clk ; -; cbus_addr_o[4] ; clk ; 6.014 ; 5.971 ; Rise ; clk ; -; cbus_addr_o[5] ; clk ; 5.986 ; 5.943 ; Rise ; clk ; -; cbus_addr_o[6] ; clk ; 6.024 ; 5.981 ; Rise ; clk ; -; cbus_addr_o[7] ; clk ; 6.071 ; 6.028 ; Rise ; clk ; -; cbus_addr_o[8] ; clk ; 6.037 ; 5.994 ; Rise ; clk ; -; cbus_addr_o[9] ; clk ; 6.002 ; 5.959 ; Rise ; clk ; -; cbus_addr_o[10] ; clk ; 6.060 ; 6.017 ; Rise ; clk ; -; cbus_addr_o[11] ; clk ; 5.995 ; 5.952 ; Rise ; clk ; -; cbus_addr_o[12] ; clk ; 6.105 ; 6.062 ; Rise ; clk ; -; cbus_addr_o[13] ; clk ; 5.987 ; 5.944 ; Rise ; clk ; -; cbus_addr_o[14] ; clk ; 6.046 ; 6.003 ; Rise ; clk ; -; cbus_addr_o[15] ; clk ; 6.055 ; 6.012 ; Rise ; clk ; -; cbus_addr_o[16] ; clk ; 6.058 ; 6.015 ; Rise ; clk ; -; cbus_addr_o[17] ; clk ; 6.003 ; 5.960 ; Rise ; clk ; -; cbus_addr_o[18] ; clk ; 6.004 ; 5.961 ; Rise ; clk ; -; cbus_addr_o[19] ; clk ; 6.005 ; 5.962 ; Rise ; clk ; -; cbus_addr_o[20] ; clk ; 6.012 ; 5.969 ; Rise ; clk ; -; cbus_addr_o[21] ; clk ; 5.994 ; 5.951 ; Rise ; clk ; -; cbus_addr_o[22] ; clk ; 6.012 ; 5.969 ; Rise ; clk ; -; cbus_addr_o[23] ; clk ; 5.999 ; 5.956 ; Rise ; clk ; -; cbus_addr_o[24] ; clk ; 6.006 ; 5.963 ; Rise ; clk ; -; cbus_addr_o[25] ; clk ; 5.993 ; 5.957 ; Rise ; clk ; -; cbus_addr_o[26] ; clk ; 6.004 ; 5.961 ; Rise ; clk ; -; cbus_addr_o[27] ; clk ; 6.033 ; 5.990 ; Rise ; clk ; -; cbus_addr_o[28] ; clk ; 6.005 ; 5.962 ; Rise ; clk ; -; cbus_addr_o[29] ; clk ; 6.027 ; 5.984 ; Rise ; clk ; -; cbus_addr_o[30] ; clk ; 6.059 ; 6.016 ; Rise ; clk ; -; cbus_addr_o[31] ; clk ; 5.995 ; 5.952 ; Rise ; clk ; -; cbus_cmd0_o[*] ; clk ; 9.110 ; 9.097 ; Rise ; clk ; -; cbus_cmd0_o[0] ; clk ; 9.110 ; 8.961 ; Rise ; clk ; -; cbus_cmd0_o[1] ; clk ; 9.095 ; 9.097 ; Rise ; clk ; -; cbus_cmd0_o[2] ; clk ; 8.955 ; 9.012 ; Rise ; clk ; -; cbus_cmd1_o[*] ; clk ; 9.220 ; 9.075 ; Rise ; clk ; -; cbus_cmd1_o[0] ; clk ; 9.220 ; 9.075 ; Rise ; clk ; -; cbus_cmd1_o[1] ; clk ; 9.105 ; 9.047 ; Rise ; clk ; -; cbus_cmd1_o[2] ; clk ; 8.844 ; 8.748 ; Rise ; clk ; -; cbus_cmd2_o[*] ; clk ; 9.214 ; 9.167 ; Rise ; clk ; -; cbus_cmd2_o[0] ; clk ; 8.900 ; 8.767 ; Rise ; clk ; -; cbus_cmd2_o[1] ; clk ; 9.119 ; 9.092 ; Rise ; clk ; -; cbus_cmd2_o[2] ; clk ; 9.214 ; 9.167 ; Rise ; clk ; -; cbus_cmd3_o[*] ; clk ; 8.881 ; 8.977 ; Rise ; clk ; -; cbus_cmd3_o[0] ; clk ; 8.823 ; 8.697 ; Rise ; clk ; -; cbus_cmd3_o[1] ; clk ; 8.786 ; 8.716 ; Rise ; clk ; -; cbus_cmd3_o[2] ; clk ; 8.881 ; 8.977 ; Rise ; clk ; -; mbus_ack0_o ; clk ; 6.000 ; 5.957 ; Rise ; clk ; -; mbus_ack1_o ; clk ; 6.008 ; 5.965 ; Rise ; clk ; -; mbus_ack2_o ; clk ; 6.040 ; 5.997 ; Rise ; clk ; -; mbus_ack3_o ; clk ; 6.047 ; 6.004 ; Rise ; clk ; -+------------------+------------+-------+-------+------------+-----------------+ - - -+------------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+------------------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+------------------+------------+-------+-------+------------+-----------------+ -; cbus_addr_o[*] ; clk ; 3.558 ; 3.553 ; Rise ; clk ; -; cbus_addr_o[0] ; clk ; 3.597 ; 3.592 ; Rise ; clk ; -; cbus_addr_o[1] ; clk ; 3.599 ; 3.612 ; Rise ; clk ; -; cbus_addr_o[2] ; clk ; 3.575 ; 3.570 ; Rise ; clk ; -; cbus_addr_o[3] ; clk ; 3.565 ; 3.560 ; Rise ; clk ; -; cbus_addr_o[4] ; clk ; 3.587 ; 3.582 ; Rise ; clk ; -; cbus_addr_o[5] ; clk ; 3.558 ; 3.553 ; Rise ; clk ; -; cbus_addr_o[6] ; clk ; 3.597 ; 3.592 ; Rise ; clk ; -; cbus_addr_o[7] ; clk ; 3.621 ; 3.634 ; Rise ; clk ; -; cbus_addr_o[8] ; clk ; 3.586 ; 3.599 ; Rise ; clk ; -; cbus_addr_o[9] ; clk ; 3.575 ; 3.570 ; Rise ; clk ; -; cbus_addr_o[10] ; clk ; 3.609 ; 3.622 ; Rise ; clk ; -; cbus_addr_o[11] ; clk ; 3.568 ; 3.563 ; Rise ; clk ; -; cbus_addr_o[12] ; clk ; 3.655 ; 3.668 ; Rise ; clk ; -; cbus_addr_o[13] ; clk ; 3.559 ; 3.554 ; Rise ; clk ; -; cbus_addr_o[14] ; clk ; 3.595 ; 3.608 ; Rise ; clk ; -; cbus_addr_o[15] ; clk ; 3.605 ; 3.618 ; Rise ; clk ; -; cbus_addr_o[16] ; clk ; 3.609 ; 3.622 ; Rise ; clk ; -; cbus_addr_o[17] ; clk ; 3.576 ; 3.571 ; Rise ; clk ; -; cbus_addr_o[18] ; clk ; 3.577 ; 3.572 ; Rise ; clk ; -; cbus_addr_o[19] ; clk ; 3.578 ; 3.573 ; Rise ; clk ; -; cbus_addr_o[20] ; clk ; 3.585 ; 3.580 ; Rise ; clk ; -; cbus_addr_o[21] ; clk ; 3.568 ; 3.563 ; Rise ; clk ; -; cbus_addr_o[22] ; clk ; 3.584 ; 3.579 ; Rise ; clk ; -; cbus_addr_o[23] ; clk ; 3.572 ; 3.567 ; Rise ; clk ; -; cbus_addr_o[24] ; clk ; 3.580 ; 3.575 ; Rise ; clk ; -; cbus_addr_o[25] ; clk ; 3.581 ; 3.574 ; Rise ; clk ; -; cbus_addr_o[26] ; clk ; 3.578 ; 3.573 ; Rise ; clk ; -; cbus_addr_o[27] ; clk ; 3.606 ; 3.601 ; Rise ; clk ; -; cbus_addr_o[28] ; clk ; 3.578 ; 3.573 ; Rise ; clk ; -; cbus_addr_o[29] ; clk ; 3.599 ; 3.594 ; Rise ; clk ; -; cbus_addr_o[30] ; clk ; 3.608 ; 3.621 ; Rise ; clk ; -; cbus_addr_o[31] ; clk ; 3.568 ; 3.563 ; Rise ; clk ; -; cbus_cmd0_o[*] ; clk ; 4.669 ; 4.778 ; Rise ; clk ; -; cbus_cmd0_o[0] ; clk ; 4.838 ; 4.778 ; Rise ; clk ; -; cbus_cmd0_o[1] ; clk ; 4.779 ; 4.946 ; Rise ; clk ; -; cbus_cmd0_o[2] ; clk ; 4.669 ; 4.820 ; Rise ; clk ; -; cbus_cmd1_o[*] ; clk ; 4.602 ; 4.661 ; Rise ; clk ; -; cbus_cmd1_o[0] ; clk ; 5.035 ; 4.954 ; Rise ; clk ; -; cbus_cmd1_o[1] ; clk ; 4.821 ; 4.952 ; Rise ; clk ; -; cbus_cmd1_o[2] ; clk ; 4.602 ; 4.661 ; Rise ; clk ; -; cbus_cmd2_o[*] ; clk ; 4.875 ; 4.830 ; Rise ; clk ; -; cbus_cmd2_o[0] ; clk ; 4.886 ; 4.830 ; Rise ; clk ; -; cbus_cmd2_o[1] ; clk ; 4.889 ; 5.045 ; Rise ; clk ; -; cbus_cmd2_o[2] ; clk ; 4.875 ; 4.927 ; Rise ; clk ; -; cbus_cmd3_o[*] ; clk ; 4.709 ; 4.804 ; Rise ; clk ; -; cbus_cmd3_o[0] ; clk ; 4.899 ; 4.804 ; Rise ; clk ; -; cbus_cmd3_o[1] ; clk ; 4.709 ; 4.814 ; Rise ; clk ; -; cbus_cmd3_o[2] ; clk ; 4.727 ; 4.868 ; Rise ; clk ; -; mbus_ack0_o ; clk ; 3.573 ; 3.568 ; Rise ; clk ; -; mbus_ack1_o ; clk ; 3.579 ; 3.574 ; Rise ; clk ; -; mbus_ack2_o ; clk ; 3.589 ; 3.602 ; Rise ; clk ; -; mbus_ack3_o ; clk ; 3.597 ; 3.610 ; Rise ; clk ; -+------------------+------------+-------+-------+------------+-----------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Board Trace Model Assignments ; -+-----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ -; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; -+-----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ -; cbus_addr_o[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[13] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[14] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[15] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[16] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[17] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[18] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[19] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[20] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[21] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[22] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[23] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[24] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[25] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[26] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[27] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[28] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[29] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[30] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_addr_o[31] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_cmd3_o[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_cmd3_o[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_cmd3_o[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_cmd2_o[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_cmd2_o[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_cmd2_o[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_cmd1_o[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_cmd1_o[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_cmd1_o[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_cmd0_o[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_cmd0_o[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; cbus_cmd0_o[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; mbus_ack3_o ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; mbus_ack2_o ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; mbus_ack1_o ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; mbus_ack0_o ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; ~ALTERA_NCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -+-----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ - - -+------------------------------------------------------------------------+ -; Input Transition Times ; -+---------------------+--------------+-----------------+-----------------+ -; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; -+---------------------+--------------+-----------------+-----------------+ -; clk ; 2.5 V ; 2000 ps ; 2000 ps ; -; rst ; 2.5 V ; 2000 ps ; 2000 ps ; -; cbus_ack3_i ; 2.5 V ; 2000 ps ; 2000 ps ; -; cbus_ack2_i ; 2.5 V ; 2000 ps ; 2000 ps ; -; cbus_ack1_i ; 2.5 V ; 2000 ps ; 2000 ps ; -; cbus_ack0_i ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_cmd3_i[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_cmd3_i[2] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_cmd3_i[1] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_cmd2_i[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_cmd2_i[1] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_cmd2_i[2] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_cmd1_i[2] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_cmd1_i[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_cmd1_i[1] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_cmd0_i[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_cmd0_i[1] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_cmd0_i[2] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[1] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[1] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[1] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[1] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[2] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[2] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[2] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[2] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[3] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[3] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[3] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[3] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[4] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[4] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[4] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[4] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[5] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[5] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[5] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[5] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[6] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[6] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[6] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[6] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[7] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[7] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[7] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[7] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[8] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[8] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[8] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[8] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[9] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[9] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[9] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[9] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[10] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[10] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[10] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[10] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[11] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[11] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[11] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[11] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[12] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[12] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[12] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[12] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[13] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[13] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[13] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[13] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[14] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[14] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[14] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[14] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[15] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[15] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[15] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[15] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[16] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[16] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[16] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[16] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[17] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[17] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[17] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[17] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[18] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[18] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[18] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[18] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[19] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[19] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[19] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[19] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[20] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[20] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[20] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[20] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[21] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[21] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[21] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[21] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[22] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[22] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[22] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[22] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[23] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[23] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[23] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[23] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[24] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[24] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[24] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[24] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[25] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[25] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[25] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[25] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[26] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[26] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[26] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[26] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[27] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[27] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[27] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[27] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[28] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[28] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[28] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[28] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[29] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[29] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[29] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[29] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[30] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[30] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[30] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[30] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr2_i[31] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr3_i[31] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr0_i[31] ; 2.5 V ; 2000 ps ; 2000 ps ; -; mbus_addr1_i[31] ; 2.5 V ; 2000 ps ; 2000 ps ; -; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ; -; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ; -; ~ALTERA_NCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ; -+---------------------+--------------+-----------------+-----------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Signal Integrity Metrics (Slow 1200mv 0c Model) ; -+-----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+-----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; cbus_addr_o[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; -; cbus_addr_o[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; -; cbus_addr_o[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; -; cbus_addr_o[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; -; cbus_addr_o[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; -; cbus_addr_o[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; -; cbus_addr_o[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; -; cbus_addr_o[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; -; cbus_addr_o[17] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[18] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[19] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[20] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[21] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[22] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[23] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[24] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[25] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; -; cbus_addr_o[26] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[27] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[28] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[29] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_addr_o[30] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; -; cbus_addr_o[31] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_cmd3_o[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_cmd3_o[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; -; cbus_cmd3_o[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; -; cbus_cmd2_o[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; -; cbus_cmd2_o[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_cmd2_o[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_cmd1_o[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_cmd1_o[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; -; cbus_cmd1_o[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; -; cbus_cmd0_o[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; cbus_cmd0_o[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; -; cbus_cmd0_o[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; -; mbus_ack3_o ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; -; mbus_ack2_o ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; -; mbus_ack1_o ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; mbus_ack0_o ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; -; ~ALTERA_NCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.99e-09 V ; 2.53 V ; -0.0412 V ; 0.279 V ; 0.088 V ; 1.14e-10 s ; 2.15e-10 s ; No ; Yes ; 2.32 V ; 3.99e-09 V ; 2.53 V ; -0.0412 V ; 0.279 V ; 0.088 V ; 1.14e-10 s ; 2.15e-10 s ; No ; Yes ; -; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.21e-09 V ; 2.38 V ; -0.0508 V ; 0.161 V ; 0.093 V ; 2.91e-10 s ; 2.66e-10 s ; Yes ; Yes ; 2.32 V ; 5.21e-09 V ; 2.38 V ; -0.0508 V ; 0.161 V ; 0.093 V ; 2.91e-10 s ; 2.66e-10 s ; Yes ; Yes ; -+-----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Signal Integrity Metrics (Slow 1200mv 85c Model) ; -+-----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+-----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; cbus_addr_o[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; -; cbus_addr_o[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; -; cbus_addr_o[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; -; cbus_addr_o[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; -; cbus_addr_o[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; -; cbus_addr_o[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; -; cbus_addr_o[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; -; cbus_addr_o[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; -; cbus_addr_o[17] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[18] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[19] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[20] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[21] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[22] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[23] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[24] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[25] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; -; cbus_addr_o[26] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[27] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[28] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[29] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_addr_o[30] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; -; cbus_addr_o[31] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_cmd3_o[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_cmd3_o[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; -; cbus_cmd3_o[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; -; cbus_cmd2_o[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; -; cbus_cmd2_o[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_cmd2_o[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_cmd1_o[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_cmd1_o[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; -; cbus_cmd1_o[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; -; cbus_cmd0_o[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; cbus_cmd0_o[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; -; cbus_cmd0_o[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; -; mbus_ack3_o ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; -; mbus_ack2_o ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; -; mbus_ack1_o ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; mbus_ack0_o ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; -; ~ALTERA_NCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.99e-07 V ; 2.39 V ; -0.0291 V ; 0.081 V ; 0.039 V ; 1.9e-10 s ; 2.97e-10 s ; Yes ; Yes ; 2.32 V ; 6.99e-07 V ; 2.39 V ; -0.0291 V ; 0.081 V ; 0.039 V ; 1.9e-10 s ; 2.97e-10 s ; Yes ; Yes ; -; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.5e-07 V ; 2.35 V ; -0.0159 V ; 0.081 V ; 0.032 V ; 4.24e-10 s ; 3.5e-10 s ; Yes ; Yes ; 2.32 V ; 8.5e-07 V ; 2.35 V ; -0.0159 V ; 0.081 V ; 0.032 V ; 4.24e-10 s ; 3.5e-10 s ; Yes ; Yes ; -+-----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Signal Integrity Metrics (Fast 1200mv 0c Model) ; -+-----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+-----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; cbus_addr_o[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; cbus_addr_o[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; cbus_addr_o[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; cbus_addr_o[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[10] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; cbus_addr_o[11] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[12] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; cbus_addr_o[13] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[14] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; cbus_addr_o[15] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; cbus_addr_o[16] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; cbus_addr_o[17] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[18] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[19] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[20] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[21] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[22] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[23] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[24] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[25] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; -; cbus_addr_o[26] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[27] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[28] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[29] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_addr_o[30] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; cbus_addr_o[31] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_cmd3_o[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_cmd3_o[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; cbus_cmd3_o[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; cbus_cmd2_o[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; cbus_cmd2_o[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_cmd2_o[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_cmd1_o[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_cmd1_o[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; cbus_cmd1_o[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; cbus_cmd0_o[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; cbus_cmd0_o[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; cbus_cmd0_o[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; mbus_ack3_o ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; mbus_ack2_o ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; mbus_ack1_o ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; mbus_ack0_o ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; ~ALTERA_NCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.65e-08 V ; 3.12 V ; -0.147 V ; 0.571 V ; 0.186 V ; 8.91e-11 s ; 1.76e-10 s ; No ; Yes ; 2.62 V ; 2.65e-08 V ; 3.12 V ; -0.147 V ; 0.571 V ; 0.186 V ; 8.91e-11 s ; 1.76e-10 s ; No ; Yes ; -; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.26e-08 V ; 2.73 V ; -0.0622 V ; 0.148 V ; 0.088 V ; 2.68e-10 s ; 2.25e-10 s ; Yes ; Yes ; 2.62 V ; 3.26e-08 V ; 2.73 V ; -0.0622 V ; 0.148 V ; 0.088 V ; 2.68e-10 s ; 2.25e-10 s ; Yes ; Yes ; -+-----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ - - -+-------------------------------------------------------------------+ -; Setup Transfers ; -+------------+----------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+------------+----------+----------+----------+----------+----------+ -; clk ; clk ; 126010 ; 0 ; 0 ; 0 ; -+------------+----------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - -+-------------------------------------------------------------------+ -; Hold Transfers ; -+------------+----------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+------------+----------+----------+----------+----------+----------+ -; clk ; clk ; 126010 ; 0 ; 0 ; 0 ; -+------------+----------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - ---------------- -; Report TCCS ; ---------------- -No dedicated SERDES Transmitter circuitry present in device or used in design - - ---------------- -; Report RSKM ; ---------------- -No dedicated SERDES Receiver circuitry present in device or used in design - - -+------------------------------------------------+ -; Unconstrained Paths ; -+---------------------------------+-------+------+ -; Property ; Setup ; Hold ; -+---------------------------------+-------+------+ -; Illegal Clocks ; 0 ; 0 ; -; Unconstrained Clocks ; 0 ; 0 ; -; Unconstrained Input Ports ; 1 ; 1 ; -; Unconstrained Input Port Paths ; 640 ; 640 ; -; Unconstrained Output Ports ; 0 ; 0 ; -; Unconstrained Output Port Paths ; 0 ; 0 ; -+---------------------------------+-------+------+ - - -+------------------------------------+ -; TimeQuest Timing Analyzer Messages ; -+------------------------------------+ -Info: ******************************************************************* -Info: Running Quartus II 32-bit TimeQuest Timing Analyzer - Info: Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition - Info: Processing started: Tue Dec 25 14:04:04 2012 -Info: Command: quartus_sta mesi_isc -c mesi_isc -Info: qsta_default_script.tcl version: #2 -Warning (20028): Parallel compilation is not licensed and has been disabled -Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'. -Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'. -Info (332104): Reading SDC File: 'mesi_isc.sdc' -Info (332152): The following assignments are ignored by the derive_clock_uncertainty command -Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON -Info: Analyzing Slow 1200mV 85C Model -Critical Warning (332148): Timing requirements not met -Info (332146): Worst-case setup slack is -8.340 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): -8.340 -2724.862 clk -Info (332146): Worst-case hold slack is -0.278 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): -0.278 -0.443 clk -Info (332140): No Recovery paths to report -Info (332140): No Removal paths to report -Info (332146): Worst-case minimum pulse width slack is -3.000 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): -3.000 -643.000 clk -Info: Analyzing Slow 1200mV 0C Model -Info (332152): The following assignments are ignored by the derive_clock_uncertainty command -Critical Warning (332148): Timing requirements not met -Info (332146): Worst-case setup slack is -7.387 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): -7.387 -2375.975 clk -Info (332146): Worst-case hold slack is -0.237 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): -0.237 -0.279 clk -Info (332140): No Recovery paths to report -Info (332140): No Removal paths to report -Info (332146): Worst-case minimum pulse width slack is -3.000 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): -3.000 -643.000 clk -Info: Analyzing Fast 1200mV 0C Model -Info (332152): The following assignments are ignored by the derive_clock_uncertainty command -Critical Warning (332148): Timing requirements not met -Info (332146): Worst-case setup slack is -4.682 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): -4.682 -1313.549 clk -Info (332146): Worst-case hold slack is -0.271 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): -0.271 -3.470 clk -Info (332140): No Recovery paths to report -Info (332140): No Removal paths to report -Info (332146): Worst-case minimum pulse width slack is -3.000 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): -3.000 -651.247 clk -Info (332102): Design is not fully constrained for setup requirements -Info (332102): Design is not fully constrained for hold requirements -Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings - Info: Peak virtual memory: 371 megabytes - Info: Processing ended: Tue Dec 25 14:04:07 2012 - Info: Elapsed time: 00:00:03 - Info: Total CPU time (on all processors): 00:00:03 - - Index: syn/mesi_isc.eda.rpt =================================================================== --- syn/mesi_isc.eda.rpt (revision 4) +++ syn/mesi_isc.eda.rpt (nonexistent) @@ -1,59 +0,0 @@ -EDA Netlist Writer report for mesi_isc -Tue Dec 25 14:02:45 2012 -Quartus II 32-bit Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. EDA Netlist Writer Summary - 3. EDA Netlist Writer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2012 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+----------------------------------------------------------------------------------+ -; EDA Netlist Writer Summary ; -+---------------------------+------------------------------------------------------+ -; EDA Netlist Writer Status ; No Output Files Generated - Tue Dec 25 14:02:45 2012 ; -; Revision Name ; mesi_isc ; -; Top-level Entity Name ; mesi_isc ; -; Family ; Cyclone IV GX ; -+---------------------------+------------------------------------------------------+ - - -+-----------------------------+ -; EDA Netlist Writer Messages ; -+-----------------------------+ -Info: ******************************************************************* -Info: Running Quartus II 32-bit EDA Netlist Writer - Info: Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition - Info: Processing started: Tue Dec 25 14:02:45 2012 -Info: Command: quartus_eda --read_settings_files=on --write_settings_files=off mesi_isc -c mesi_isc -Warning (199027): Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script. -Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 344 megabytes - Info: Processing ended: Tue Dec 25 14:02:45 2012 - Info: Elapsed time: 00:00:00 - Info: Total CPU time (on all processors): 00:00:01 - - Index: syn/mesi_isc.pow.summary =================================================================== --- syn/mesi_isc.pow.summary (revision 4) +++ syn/mesi_isc.pow.summary (nonexistent) @@ -1,12 +0,0 @@ -PowerPlay Power Analyzer Status : Successful - Sun Dec 23 11:48:56 2012 -Quartus II 32-bit Version : 12.0 Build 263 08/02/2012 SP 2 SJ Web Edition -Revision Name : mesi_isc -Top-level Entity Name : mesi_isc -Family : Cyclone IV GX -Device : EP4CGX30CF23C6 -Power Models : Final -Total Thermal Power Dissipation : 178.89 mW -Core Dynamic Thermal Power Dissipation : 0.00 mW -Core Static Thermal Power Dissipation : 118.11 mW -I/O Thermal Power Dissipation : 60.78 mW -Power Estimation Confidence : Low: user provided insufficient toggle rate data Index: syn/run_syn =================================================================== --- syn/run_syn (revision 4) +++ syn/run_syn (nonexistent) @@ -1,38 +0,0 @@ -#////////////////////////////////////////////////////////////////// -#//// //// -#//// Copyright (C) 2009 Authors and OPENCORES.ORG //// -#//// //// -#//// This source file may be used and distributed without //// -#//// restriction provided that this copyright statement is not //// -#//// removed from the file and that any derivative work contains //// -#//// the original copyright notice and the associated disclaimer. //// -#//// //// -#//// This source file is free software; you can redistribute it //// -#//// and/or modify it under the terms of the GNU Lesser General //// -#//// Public License as published by the Free Software Foundation; //// -#//// either version 2.1 of the License, or (at your option) any //// -#//// later version. //// -#//// //// -#//// This source is distributed in the hope that it will be //// -#//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -#//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -#//// PURPOSE. See the GNU Lesser General Public License for more //// -#//// details. //// -#//// //// -#//// You should have received a copy of the GNU Lesser General //// -#//// Public License along with this source; if not, download it //// -#//// from http://www.opencores.org/lgpl.shtml //// -#//// //// -#////////////////////////////////////////////////////////////////////// - -#////////////////////////////////////////////////////////////////////// -#//// //// -#//// MESI_ISC Project //// -#//// //// -#//// Author(s): //// -#//// - Yair Amitay yair.amitay@yahoo.com //// -#//// www.linkedin.com/in/yairamitay //// -#//// //// -#////////////////////////////////////////////////////////////////////// - -/opt/12.0sp2/quartus/bin/quartus &
syn/run_syn Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: syn/mesi_isc.jdi =================================================================== --- syn/mesi_isc.jdi (revision 4) +++ syn/mesi_isc.jdi (nonexistent) @@ -1,7 +0,0 @@ - - - - - - - Index: syn/mesi_isc.pow.rpt =================================================================== --- syn/mesi_isc.pow.rpt (revision 4) +++ syn/mesi_isc.pow.rpt (nonexistent) @@ -1,436 +0,0 @@ -PowerPlay Power Analyzer report for mesi_isc -Sun Dec 23 11:48:56 2012 -Quartus II 32-bit Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. PowerPlay Power Analyzer Summary - 3. PowerPlay Power Analyzer Settings - 4. Indeterminate Toggle Rates - 5. Operating Conditions Used - 6. Thermal Power Dissipation by Block - 7. Thermal Power Dissipation by Block Type - 8. Thermal Power Dissipation by Hierarchy - 9. Core Dynamic Thermal Power Dissipation by Clock Domain - 10. Current Drawn from Voltage Supplies Summary - 11. VCCIO Supply Current Drawn by I/O Bank - 12. VCCIO Supply Current Drawn by Voltage - 13. Confidence Metric Details - 14. Signal Activities - 15. PowerPlay Power Analyzer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2012 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-------------------------------------------------------------------------------------------+ -; PowerPlay Power Analyzer Summary ; -+----------------------------------------+--------------------------------------------------+ -; PowerPlay Power Analyzer Status ; Successful - Sun Dec 23 11:48:56 2012 ; -; Quartus II 32-bit Version ; 12.0 Build 263 08/02/2012 SP 2 SJ Web Edition ; -; Revision Name ; mesi_isc ; -; Top-level Entity Name ; mesi_isc ; -; Family ; Cyclone IV GX ; -; Device ; EP4CGX30CF23C6 ; -; Power Models ; Final ; -; Total Thermal Power Dissipation ; 178.89 mW ; -; Core Dynamic Thermal Power Dissipation ; 0.00 mW ; -; Core Static Thermal Power Dissipation ; 118.11 mW ; -; I/O Thermal Power Dissipation ; 60.78 mW ; -; Power Estimation Confidence ; Low: user provided insufficient toggle rate data ; -+----------------------------------------+--------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------+ -; PowerPlay Power Analyzer Settings ; -+----------------------------------------------------------------------------+---------+---------------+ -; Option ; Setting ; Default Value ; -+----------------------------------------------------------------------------+---------+---------------+ -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Default Power Toggle Rate ; 12.5% ; 12.5% ; -; Default Power Input I/O Toggle Rate ; 12.5% ; 12.5% ; -; Use vectorless estimation ; On ; On ; -; Use Input Files ; Off ; Off ; -; Filter Glitches in VCD File Reader ; On ; On ; -; Power Analyzer Report Signal Activity ; Off ; Off ; -; Power Analyzer Report Power Dissipation ; Off ; Off ; -; Device Power Characteristics ; TYPICAL ; TYPICAL ; -; Automatically Compute Junction Temperature ; On ; On ; -; Specified Junction Temperature ; 25 ; 25 ; -; Ambient Temperature ; 25 ; 25 ; -; Use Custom Cooling Solution ; Off ; Off ; -; Board Temperature ; 25 ; 25 ; -; Enable HPS ; Off ; Off ; -; Processor Frequency ; 0.0 ; 0.0 ; -+----------------------------------------------------------------------------+---------+---------------+ - - -+------------------------------------------------+ -; Indeterminate Toggle Rates ; -+------------------+-----------------------------+ -; Node ; Reason ; -+------------------+-----------------------------+ -; clk ; No valid clock domain found ; -; rst ; No valid clock domain found ; -; cbus_ack3_i ; No valid clock domain found ; -; cbus_ack2_i ; No valid clock domain found ; -; cbus_ack1_i ; No valid clock domain found ; -; cbus_ack0_i ; No valid clock domain found ; -; mbus_cmd3_i[0] ; No valid clock domain found ; -; mbus_cmd3_i[1] ; No valid clock domain found ; -; mbus_cmd3_i[2] ; No valid clock domain found ; -; mbus_cmd2_i[0] ; No valid clock domain found ; -; mbus_cmd2_i[1] ; No valid clock domain found ; -; mbus_cmd2_i[2] ; No valid clock domain found ; -; mbus_cmd1_i[0] ; No valid clock domain found ; -; mbus_cmd1_i[1] ; No valid clock domain found ; -; mbus_cmd1_i[2] ; No valid clock domain found ; -; mbus_cmd0_i[0] ; No valid clock domain found ; -; mbus_cmd0_i[1] ; No valid clock domain found ; -; mbus_cmd0_i[2] ; No valid clock domain found ; -; mbus_addr2_i[0] ; No valid clock domain found ; -; mbus_addr3_i[0] ; No valid clock domain found ; -; mbus_addr0_i[0] ; No valid clock domain found ; -; mbus_addr1_i[0] ; No valid clock domain found ; -; mbus_addr2_i[1] ; No valid clock domain found ; -; mbus_addr3_i[1] ; No valid clock domain found ; -; mbus_addr0_i[1] ; No valid clock domain found ; -; mbus_addr1_i[1] ; No valid clock domain found ; -; mbus_addr2_i[2] ; No valid clock domain found ; -; mbus_addr3_i[2] ; No valid clock domain found ; -; mbus_addr0_i[2] ; No valid clock domain found ; -; mbus_addr1_i[2] ; No valid clock domain found ; -; mbus_addr2_i[3] ; No valid clock domain found ; -; mbus_addr3_i[3] ; No valid clock domain found ; -; mbus_addr0_i[3] ; No valid clock domain found ; -; mbus_addr1_i[3] ; No valid clock domain found ; -; mbus_addr2_i[4] ; No valid clock domain found ; -; mbus_addr3_i[4] ; No valid clock domain found ; -; mbus_addr0_i[4] ; No valid clock domain found ; -; mbus_addr1_i[4] ; No valid clock domain found ; -; mbus_addr2_i[5] ; No valid clock domain found ; -; mbus_addr3_i[5] ; No valid clock domain found ; -; mbus_addr0_i[5] ; No valid clock domain found ; -; mbus_addr1_i[5] ; No valid clock domain found ; -; mbus_addr2_i[6] ; No valid clock domain found ; -; mbus_addr3_i[6] ; No valid clock domain found ; -; mbus_addr0_i[6] ; No valid clock domain found ; -; mbus_addr1_i[6] ; No valid clock domain found ; -; mbus_addr2_i[7] ; No valid clock domain found ; -; mbus_addr3_i[7] ; No valid clock domain found ; -; mbus_addr0_i[7] ; No valid clock domain found ; -; mbus_addr1_i[7] ; No valid clock domain found ; -; mbus_addr2_i[8] ; No valid clock domain found ; -; mbus_addr3_i[8] ; No valid clock domain found ; -; mbus_addr0_i[8] ; No valid clock domain found ; -; mbus_addr1_i[8] ; No valid clock domain found ; -; mbus_addr2_i[9] ; No valid clock domain found ; -; mbus_addr3_i[9] ; No valid clock domain found ; -; mbus_addr0_i[9] ; No valid clock domain found ; -; mbus_addr1_i[9] ; No valid clock domain found ; -; mbus_addr2_i[10] ; No valid clock domain found ; -; mbus_addr3_i[10] ; No valid clock domain found ; -; mbus_addr0_i[10] ; No valid clock domain found ; -; mbus_addr1_i[10] ; No valid clock domain found ; -; mbus_addr2_i[11] ; No valid clock domain found ; -; mbus_addr3_i[11] ; No valid clock domain found ; -; mbus_addr0_i[11] ; No valid clock domain found ; -; mbus_addr1_i[11] ; No valid clock domain found ; -; mbus_addr2_i[12] ; No valid clock domain found ; -; mbus_addr3_i[12] ; No valid clock domain found ; -; mbus_addr0_i[12] ; No valid clock domain found ; -; mbus_addr1_i[12] ; No valid clock domain found ; -; mbus_addr2_i[13] ; No valid clock domain found ; -; mbus_addr3_i[13] ; No valid clock domain found ; -; mbus_addr0_i[13] ; No valid clock domain found ; -; mbus_addr1_i[13] ; No valid clock domain found ; -; mbus_addr2_i[14] ; No valid clock domain found ; -; mbus_addr3_i[14] ; No valid clock domain found ; -; mbus_addr0_i[14] ; No valid clock domain found ; -; mbus_addr1_i[14] ; No valid clock domain found ; -; mbus_addr2_i[15] ; No valid clock domain found ; -; mbus_addr3_i[15] ; No valid clock domain found ; -; mbus_addr0_i[15] ; No valid clock domain found ; -; mbus_addr1_i[15] ; No valid clock domain found ; -; mbus_addr2_i[16] ; No valid clock domain found ; -; mbus_addr3_i[16] ; No valid clock domain found ; -; mbus_addr0_i[16] ; No valid clock domain found ; -; mbus_addr1_i[16] ; No valid clock domain found ; -; mbus_addr2_i[17] ; No valid clock domain found ; -; mbus_addr3_i[17] ; No valid clock domain found ; -; mbus_addr0_i[17] ; No valid clock domain found ; -; mbus_addr1_i[17] ; No valid clock domain found ; -; mbus_addr2_i[18] ; No valid clock domain found ; -; mbus_addr3_i[18] ; No valid clock domain found ; -; mbus_addr0_i[18] ; No valid clock domain found ; -; mbus_addr1_i[18] ; No valid clock domain found ; -; mbus_addr2_i[19] ; No valid clock domain found ; -; mbus_addr3_i[19] ; No valid clock domain found ; -; mbus_addr0_i[19] ; No valid clock domain found ; -; mbus_addr1_i[19] ; No valid clock domain found ; -; mbus_addr2_i[20] ; No valid clock domain found ; -; mbus_addr3_i[20] ; No valid clock domain found ; -; mbus_addr0_i[20] ; No valid clock domain found ; -; mbus_addr1_i[20] ; No valid clock domain found ; -; mbus_addr2_i[21] ; No valid clock domain found ; -; mbus_addr3_i[21] ; No valid clock domain found ; -; mbus_addr0_i[21] ; No valid clock domain found ; -; mbus_addr1_i[21] ; No valid clock domain found ; -; mbus_addr2_i[22] ; No valid clock domain found ; -; mbus_addr3_i[22] ; No valid clock domain found ; -; mbus_addr0_i[22] ; No valid clock domain found ; -; mbus_addr1_i[22] ; No valid clock domain found ; -; mbus_addr2_i[23] ; No valid clock domain found ; -; mbus_addr3_i[23] ; No valid clock domain found ; -; mbus_addr0_i[23] ; No valid clock domain found ; -; mbus_addr1_i[23] ; No valid clock domain found ; -; mbus_addr2_i[24] ; No valid clock domain found ; -; mbus_addr3_i[24] ; No valid clock domain found ; -; mbus_addr0_i[24] ; No valid clock domain found ; -; mbus_addr1_i[24] ; No valid clock domain found ; -; mbus_addr2_i[25] ; No valid clock domain found ; -; mbus_addr3_i[25] ; No valid clock domain found ; -; mbus_addr0_i[25] ; No valid clock domain found ; -; mbus_addr1_i[25] ; No valid clock domain found ; -; mbus_addr2_i[26] ; No valid clock domain found ; -; mbus_addr3_i[26] ; No valid clock domain found ; -; mbus_addr0_i[26] ; No valid clock domain found ; -; mbus_addr1_i[26] ; No valid clock domain found ; -; mbus_addr2_i[27] ; No valid clock domain found ; -; mbus_addr3_i[27] ; No valid clock domain found ; -; mbus_addr0_i[27] ; No valid clock domain found ; -; mbus_addr1_i[27] ; No valid clock domain found ; -; mbus_addr2_i[28] ; No valid clock domain found ; -; mbus_addr3_i[28] ; No valid clock domain found ; -; mbus_addr0_i[28] ; No valid clock domain found ; -; mbus_addr1_i[28] ; No valid clock domain found ; -; mbus_addr2_i[29] ; No valid clock domain found ; -; mbus_addr3_i[29] ; No valid clock domain found ; -; mbus_addr0_i[29] ; No valid clock domain found ; -; mbus_addr1_i[29] ; No valid clock domain found ; -; mbus_addr2_i[30] ; No valid clock domain found ; -; mbus_addr3_i[30] ; No valid clock domain found ; -; mbus_addr0_i[30] ; No valid clock domain found ; -; mbus_addr1_i[30] ; No valid clock domain found ; -; mbus_addr2_i[31] ; No valid clock domain found ; -; mbus_addr3_i[31] ; No valid clock domain found ; -; mbus_addr0_i[31] ; No valid clock domain found ; -; mbus_addr1_i[31] ; No valid clock domain found ; -+------------------+-----------------------------+ - - -+-------------------------------------------------------------------------+ -; Operating Conditions Used ; -+---------------------------------------------+---------------------------+ -; Setting ; Value ; -+---------------------------------------------+---------------------------+ -; Device power characteristics ; Typical ; -; ; ; -; Voltages ; ; -; VCCINT ; 1.20 V ; -; VCCA ; 2.50 V ; -; VCCD_PLL ; 1.20 V ; -; VCC_CLKIN ; 2.50 V ; -; VCCA_GXB ; 0.00 V ; -; VCCH_GXB ; 2.50 V ; -; VCCL_GXB ; 0.00 V ; -; 2.5 V I/O Standard ; 2.5 V ; -; ; ; -; Auto computed junction temperature ; 26.4 degrees Celsius ; -; Ambient temperature ; 25.0 degrees Celsius ; -; Junction-to-Case thermal resistance ; 4.40 degrees Celsius/Watt ; -; Case-to-Heat Sink thermal resistance ; 0.10 degrees Celsius/Watt ; -; Heat Sink-to-Ambient thermal resistance ; 3.40 degrees Celsius/Watt ; -; ; ; -; Board model used ; None ; -+---------------------------------------------+---------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Thermal Power Dissipation by Block ; -+------------+------------+---------------------+-----------------------------+--------------------------------+-------------------------------+ -; Block Name ; Block Type ; Total Thermal Power ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ; -+------------+------------+---------------------+-----------------------------+--------------------------------+-------------------------------+ -(1) The "Thermal Power Dissipation by Block" Table has been hidden. To show this table, please select the "Write power dissipation by block to report file" option under "PowerPlay Power Analyzer Settings". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Thermal Power Dissipation by Block Type ; -+---------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+ -; Block Type ; Total Thermal Power by Block Type ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ; Block Average Toggle Rate (millions of transitions / sec) ; -+---------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+ -; Combinational cell ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ; -; Clock control block ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ; -; Register cell ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ; -; I/O ; 54.26 mW ; 0.00 mW ; 54.26 mW ; 0.00 mW ; 0.000 ; -+---------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+ -(1) The "Block Thermal Static Power" for all block types except Pins and the Voltage Regulator, if one exists, is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing. - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Thermal Power Dissipation by Hierarchy ; -+------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+-----------------------------------------------------------------------------------------------------+ -; Compilation Hierarchy Node ; Total Thermal Power by Hierarchy (1) ; Block Thermal Dynamic Power (1) ; Block Thermal Static Power (1)(2) ; Routing Thermal Dynamic Power (1) ; Full Hierarchy Name ; -+------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+-----------------------------------------------------------------------------------------------------+ -; |mesi_isc ; 54.26 mW (54.26 mW) ; 0.00 mW (0.00 mW) ; 54.26 mW (54.26 mW) ; 0.00 mW (0.00 mW) ; |mesi_isc ; -; |hard_block:auto_generated_inst ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |mesi_isc|hard_block:auto_generated_inst ; -; |mesi_isc_breq_fifos:mesi_isc_breq_fifos ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos ; -; |mesi_isc_basic_fifo:fifo_0 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0 ; -; |mesi_isc_basic_fifo:fifo_1 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1 ; -; |mesi_isc_basic_fifo:fifo_2 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2 ; -; |mesi_isc_basic_fifo:fifo_3 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3 ; -; |mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl ; -; |mesi_isc_broad:mesi_isc_broad ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |mesi_isc|mesi_isc_broad:mesi_isc_broad ; -; |mesi_isc_basic_fifo:broad_fifo ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo ; -; |mesi_isc_broad_cntl:mesi_isc_broad_cntl ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl ; -+------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+-----------------------------------------------------------------------------------------------------+ -(1) Value in parentheses is the power consumed at that level of hierarchy. Value not in parentheses is the power consumed at that level of hierarchy plus the power consumed by all levels of hierarchy below it. - -(2) The "Block Thermal Static Power" for all levels of hierarchy except the top-level hierarchy is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing. - - -+--------------------------------------------------------------------+ -; Core Dynamic Thermal Power Dissipation by Clock Domain ; -+-----------------+-----------------------+--------------------------+ -; Clock Domain ; Clock Frequency (MHz) ; Total Core Dynamic Power ; -+-----------------+-----------------------+--------------------------+ -; No clock domain ; 0.00 ; 0.00 ; -+-----------------+-----------------------+--------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------+ -; Current Drawn from Voltage Supplies Summary ; -+----------------+-------------------------+---------------------------+--------------------------+----------------------------------+ -; Voltage Supply ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ; -+----------------+-------------------------+---------------------------+--------------------------+----------------------------------+ -; VCCINT ; 63.36 mA ; 0.00 mA ; 63.36 mA ; 63.36 mA ; -; VCCIO ; 3.38 mA ; 0.00 mA ; 3.38 mA ; 3.38 mA ; -; VCCA ; 35.06 mA ; 0.00 mA ; 35.06 mA ; 35.06 mA ; -; VCCD_PLL ; 5.62 mA ; 0.00 mA ; 5.62 mA ; 5.62 mA ; -; VCC_CLKIN ; 0.00 mA ; 0.00 mA ; 0.00 mA ; 0.00 mA ; -; VCCA_GXB ; 0.00 mA ; 0.00 mA ; 0.00 mA ; 0.00 mA ; -; VCCH_GXB ; 0.00 mA ; 0.00 mA ; 0.00 mA ; 0.00 mA ; -; VCCL_GXB ; 0.00 mA ; 0.00 mA ; 0.00 mA ; 0.00 mA ; -+----------------+-------------------------+---------------------------+--------------------------+----------------------------------+ -(1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device. -(2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device. - - -+-----------------------------------------------------------------------------------------------+ -; VCCIO Supply Current Drawn by I/O Bank ; -+----------+---------------+---------------------+-----------------------+----------------------+ -; I/O Bank ; VCCIO Voltage ; Total Current Drawn ; Dynamic Current Drawn ; Static Current Drawn ; -+----------+---------------+---------------------+-----------------------+----------------------+ -; QL1 ; -- ; -- ; -- ; -- ; -; QL0 ; -- ; -- ; -- ; -- ; -; 3 ; 2.5V ; 0.45 mA ; 0.00 mA ; 0.45 mA ; -; 3B ; -- ; -- ; -- ; -- ; -; 3A ; -- ; -- ; -- ; -- ; -; 4 ; 2.5V ; 0.52 mA ; 0.00 mA ; 0.52 mA ; -; 5 ; 2.5V ; 0.48 mA ; 0.00 mA ; 0.48 mA ; -; 6 ; 2.5V ; 0.52 mA ; 0.00 mA ; 0.52 mA ; -; 7 ; 2.5V ; 0.53 mA ; 0.00 mA ; 0.53 mA ; -; 8A ; -- ; -- ; -- ; -- ; -; 8 ; 2.5V ; 0.48 mA ; 0.00 mA ; 0.48 mA ; -; 8B ; -- ; -- ; -- ; -- ; -; 9 ; 2.5V ; 0.39 mA ; 0.00 mA ; 0.39 mA ; -+----------+---------------+---------------------+-----------------------+----------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------+ -; VCCIO Supply Current Drawn by Voltage ; -+---------------+-------------------------+---------------------------+--------------------------+----------------------------------+ -; VCCIO Voltage ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ; -+---------------+-------------------------+---------------------------+--------------------------+----------------------------------+ -; 2.5V ; 3.38 mA ; 0.00 mA ; 3.38 mA ; 3.38 mA ; -+---------------+-------------------------+---------------------------+--------------------------+----------------------------------+ -(1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device. -(2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device. - - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Confidence Metric Details ; -+----------------------------------------------------------------------------------------+--------------+-------------+--------------+---------------+ -; Data Source ; Total ; Pin ; Registered ; Combinational ; -+----------------------------------------------------------------------------------------+--------------+-------------+--------------+---------------+ -; Simulation (from file) ; ; ; ; ; -; -- Number of signals with Toggle Rate from Simulation ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; -; -- Number of signals with Static Probability from Simulation ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; -; ; ; ; ; ; -; Node, entity or clock assignment ; ; ; ; ; -; -- Number of signals with Toggle Rate from Node, entity or clock assignment ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; -; -- Number of signals with Static Probability from Node, entity or clock assignment ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; -; ; ; ; ; ; -; Vectorless estimation ; ; ; ; ; -; -- Number of signals with Toggle Rate from Vectorless estimation ; 1633 (91.7%) ; 51 (25.6%) ; 636 (100.0%) ; 946 (100.0%) ; -; -- Number of signals with Zero toggle rate, from Vectorless estimation ; 404 (22.7%) ; 2 (1.0%) ; 8 (1.3%) ; 394 (41.6%) ; -; -- Number of signals with Static Probability from Vectorless estimation ; 1633 (91.7%) ; 51 (25.6%) ; 636 (100.0%) ; 946 (100.0%) ; -; ; ; ; ; ; -; Default assignment ; ; ; ; ; -; -- Number of signals with Toggle Rate from Default assignment ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; -; -- Number of signals with Static Probability from Default assignment ; 148 (8.3%) ; 148 (74.4%) ; 0 (0.0%) ; 0 (0.0%) ; -; ; ; ; ; ; -; Assumed 0 ; ; ; ; ; -; -- Number of signals with Toggle Rate assumed 0 ; 148 (8.3%) ; 148 (74.4%) ; 0 (0.0%) ; 0 (0.0%) ; -+----------------------------------------------------------------------------------------+--------------+-------------+--------------+---------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Signal Activities ; -+--------+------+---------------------------------------------+-------------------------+--------------------+--------------------------------+ -; Signal ; Type ; Toggle Rate (millions of transitions / sec) ; Toggle Rate Data Source ; Static Probability ; Static Probability Data Source ; -+--------+------+---------------------------------------------+-------------------------+--------------------+--------------------------------+ -(1) The "Signal Activity" Table has been hidden. To show this table, please select the "Write signal activities to report file" option under "PowerPlay Power Analyzer Settings". - - -+-----------------------------------+ -; PowerPlay Power Analyzer Messages ; -+-----------------------------------+ -Info: ******************************************************************* -Info: Running Quartus II 32-bit PowerPlay Power Analyzer - Info: Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition - Info: Processing started: Sun Dec 23 11:48:46 2012 -Info: Command: quartus_pow --read_settings_files=on --write_settings_files=off mesi_isc -c mesi_isc -Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'. -Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'. -Critical Warning (332012): Synopsys Design Constraints File file not found: 'mesi_isc.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. -Warning (332060): Node: clk was determined to be a clock but was found without an associated clock assignment. -Warning (332068): No clocks defined in design. -Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" -Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. -Info (223000): Starting Vectorless Power Activity Estimation -Warning (222013): Relative toggle rates could not be calculated because no clock domain could be identified for some nodes -Info (223001): Completed Vectorless Power Activity Estimation -Info (218000): Using Advanced I/O Power to simulate I/O buffers with the specified board trace model -Warning (215044): No board thermal model was selected. Analyzing without board thermal modeling. -Info (215049): Average toggle rate for this design is 0.000 millions of transitions / sec -Info (215031): Total thermal power estimate for the design is 178.89 mW -Info: Quartus II 32-bit PowerPlay Power Analyzer was successful. 0 errors, 5 warnings - Info: Peak virtual memory: 428 megabytes - Info: Processing ended: Sun Dec 23 11:48:56 2012 - Info: Elapsed time: 00:00:10 - Info: Total CPU time (on all processors): 00:00:10 - - Index: syn/mesi_isc.map.summary =================================================================== --- syn/mesi_isc.map.summary (revision 4) +++ syn/mesi_isc.map.summary (nonexistent) @@ -1,18 +0,0 @@ -Analysis & Synthesis Status : Successful - Tue Dec 25 13:54:13 2012 -Quartus II 32-bit Version : 12.0 Build 263 08/02/2012 SP 2 SJ Web Edition -Revision Name : mesi_isc -Top-level Entity Name : mesi_isc -Family : Cyclone IV GX -Total logic elements : 863 - Total combinational functions : 481 - Dedicated logic registers : 636 -Total registers : 636 -Total pins : 194 -Total virtual pins : 0 -Total memory bits : 0 -Embedded Multiplier 9-bit elements : 0 -Total GXB Receiver Channel PCS : 0 -Total GXB Receiver Channel PMA : 0 -Total GXB Transmitter Channel PCS : 0 -Total GXB Transmitter Channel PMA : 0 -Total PLLs : 0 Index: syn/mesi_isc.sdc =================================================================== --- syn/mesi_isc.sdc (revision 4) +++ syn/mesi_isc.sdc (nonexistent) @@ -1,103 +0,0 @@ -## Generated SDC file "mesi_isc.out.sdc" - -## Copyright (C) 1991-2012 Altera Corporation -## Your use of Altera Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Altera Program License -## Subscription Agreement, Altera MegaCore Function License -## Agreement, or other applicable license agreement, including, -## without limitation, that your use is for the sole purpose of -## programming logic devices manufactured by Altera and sold by -## Altera or its authorized distributors. Please refer to the -## applicable agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus II" -## VERSION "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition" - -## DATE "Tue Nov 6 14:51:56 2012" - -## -## DEVICE "EP4CGX30CF23C6" -## - - -#************************************************************** -# Time Information -#************************************************************** - -set_time_format -unit ns -decimal_places 3 - - - -#************************************************************** -# Create Clock -#************************************************************** -create_clock -name {clk} -period 1.000 -waveform { 0.000 0.500 } [get_ports {clk}] - - -#************************************************************** -# Create Generated Clock -#************************************************************** - -#************************************************************** -# Set Clock Latency -#************************************************************** - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** -set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {clk}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {clk}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {clk}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {clk}] 0.020 - -#************************************************************** -# Set Input Delay -#************************************************************** -set_input_delay -add_delay -clock [get_clocks {clk}] 0.100 [get_ports {cbus_ack*}] -set_input_delay -add_delay -clock [get_clocks {clk}] 0.100 [get_ports {mbus_addr*}] -set_input_delay -add_delay -clock [get_clocks {clk}] 0.100 [get_ports {mbus_cmd*}] - - -#************************************************************** -# Set Output Delay -#************************************************************** -set_output_delay -add_delay -clock [get_clocks {clk}] 0.100 [get_ports {cbus_addr_o*}] -set_output_delay -add_delay -clock [get_clocks {clk}] 0.100 [get_ports {cbus_cmd*}] -set_output_delay -add_delay -clock [get_clocks {clk}] 0.100 [get_ports {mbus_ack*}] - - -#************************************************************** -# Set Clock Groups -#************************************************************** - - -#************************************************************** -# Set False Path -#************************************************************** - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - -#************************************************************** -# Set Input Transition -#************************************************************** - Index: syn/mesi_isc.qws =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: syn/mesi_isc.qws =================================================================== --- syn/mesi_isc.qws (revision 4) +++ syn/mesi_isc.qws (nonexistent)
syn/mesi_isc.qws Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property

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