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/trunk/src/rtl/mesi_isc.v
0,0 → 1,203
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
//// ////
//// MESI_ISC Project ////
//// ////
//// Author(s): ////
//// - Yair Amitay yair.amitay@yahoo.com ////
//// www.linkedin.com/in/yairamitay ////
//// ////
//// Description ////
//// mesi_isc ////
//// ------------------- ////
//// ////
//// ////
//// To Do: ////
//// - ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`include "mesi_isc_define.v"
 
module mesi_isc
(
// Inputs
clk,
rst,
mbus_cmd3_i,
mbus_cmd2_i,
mbus_cmd1_i,
mbus_cmd0_i,
mbus_addr3_i,
mbus_addr2_i,
mbus_addr1_i,
mbus_addr0_i,
cbus_ack3_i,
cbus_ack2_i,
cbus_ack1_i,
cbus_ack0_i,
// Outputs
cbus_addr_o,
cbus_cmd3_o,
cbus_cmd2_o,
cbus_cmd1_o,
cbus_cmd0_o,
mbus_ack3_o,
mbus_ack2_o,
mbus_ack1_o,
mbus_ack0_o
);
parameter
CBUS_CMD_WIDTH = 3,
ADDR_WIDTH = 32,
BROAD_TYPE_WIDTH = 2,
BROAD_ID_WIDTH = 5,
BROAD_REQ_FIFO_SIZE = 4,
BROAD_REQ_FIFO_SIZE_LOG2 = 2,
MBUS_CMD_WIDTH = 3,
BREQ_FIFO_SIZE = 2,
BREQ_FIFO_SIZE_LOG2 = 1;
// Inputs
//================================
// System
input clk; // System clock
input rst; // Active high system reset
// Main buses
input [MBUS_CMD_WIDTH-1:0] mbus_cmd3_i; // Main bus3 command
input [MBUS_CMD_WIDTH-1:0] mbus_cmd2_i; // Main bus2 command
input [MBUS_CMD_WIDTH-1:0] mbus_cmd1_i; // Main bus1 command
input [MBUS_CMD_WIDTH-1:0] mbus_cmd0_i; // Main bus0 command
// Coherence buses
input [ADDR_WIDTH-1:0] mbus_addr3_i; // Coherence bus3 address
input [ADDR_WIDTH-1:0] mbus_addr2_i; // Coherence bus2 address
input [ADDR_WIDTH-1:0] mbus_addr1_i; // Coherence bus1 address
input [ADDR_WIDTH-1:0] mbus_addr0_i; // Coherence bus0 address
input cbus_ack3_i; // Coherence bus3 acknowledge
input cbus_ack2_i; // Coherence bus2 acknowledge
input cbus_ack1_i; // Coherence bus1 acknowledge
input cbus_ack0_i; // Coherence bus0 acknowledge
// Outputs
//================================
 
output [ADDR_WIDTH-1:0] cbus_addr_o; // Coherence bus address. All busses have
// the same address
output [CBUS_CMD_WIDTH-1:0] cbus_cmd3_o; // Coherence bus3 command
output [CBUS_CMD_WIDTH-1:0] cbus_cmd2_o; // Coherence bus2 command
output [CBUS_CMD_WIDTH-1:0] cbus_cmd1_o; // Coherence bus1 command
output [CBUS_CMD_WIDTH-1:0] cbus_cmd0_o; // Coherence bus0 command
 
 
output mbus_ack3_o; // Main bus3 acknowledge
output mbus_ack2_o; // Main bus2 acknowledge
output mbus_ack1_o; // Main bus1 acknowledge
output mbus_ack0_o; // Main bus0 acknowledge
// Regs & wires
//================================
wire broad_fifo_wr;
wire [ADDR_WIDTH-1:0] broad_addr;
wire [BROAD_ID_WIDTH-1:0] broad_id;
wire [BROAD_TYPE_WIDTH-1:0] broad_type;
wire [1:0] broad_cpu_id;
wire broad_fifo_status_full;
// mesi_isc_broad
//================================
mesi_isc_broad #(CBUS_CMD_WIDTH,
ADDR_WIDTH,
BROAD_TYPE_WIDTH,
BROAD_ID_WIDTH,
BROAD_REQ_FIFO_SIZE,
BROAD_REQ_FIFO_SIZE_LOG2)
mesi_isc_broad
(
// Inputs
.clk (clk),
.rst (rst),
.cbus_ack_array_i ({cbus_ack3_i,
cbus_ack2_i,
cbus_ack1_i,
cbus_ack0_i}
),
.broad_fifo_wr_i (broad_fifo_wr ),
.broad_addr_i (broad_addr[ADDR_WIDTH-1:0]),
.broad_type_i (broad_type[BROAD_TYPE_WIDTH-1:0]),
.broad_cpu_id_i (broad_cpu_id[1:0]),
.broad_id_i (broad_id[BROAD_ID_WIDTH-1:0]),
// Outputs
.cbus_addr_o (cbus_addr_o[ADDR_WIDTH-1:0]),
.cbus_cmd_array_o ({cbus_cmd3_o[CBUS_CMD_WIDTH-1:0],
cbus_cmd2_o[CBUS_CMD_WIDTH-1:0],
cbus_cmd1_o[CBUS_CMD_WIDTH-1:0],
cbus_cmd0_o[CBUS_CMD_WIDTH-1:0]}
),
.fifo_status_full_o (broad_fifo_status_full)
);
 
// mesi_isc_breq_fifos
//================================
mesi_isc_breq_fifos #(MBUS_CMD_WIDTH,
ADDR_WIDTH,
BROAD_TYPE_WIDTH,
BROAD_ID_WIDTH,
BREQ_FIFO_SIZE,
BREQ_FIFO_SIZE_LOG2)
mesi_isc_breq_fifos
(
// Inputs
.clk (clk),
.rst (rst),
.mbus_cmd_array_i ({mbus_cmd3_i[MBUS_CMD_WIDTH-1:0],
mbus_cmd2_i[MBUS_CMD_WIDTH-1:0],
mbus_cmd1_i[MBUS_CMD_WIDTH-1:0],
mbus_cmd0_i[MBUS_CMD_WIDTH-1:0]}
),
.mbus_addr_array_i ({mbus_addr3_i[ADDR_WIDTH-1:0],
mbus_addr2_i[ADDR_WIDTH-1:0],
mbus_addr1_i[ADDR_WIDTH-1:0],
mbus_addr0_i[ADDR_WIDTH-1:0]}
),
.broad_fifo_status_full_i (broad_fifo_status_full),
// Outputs
.mbus_ack_array_o ({mbus_ack3_o,
mbus_ack2_o,
mbus_ack1_o,
mbus_ack0_o}
),
.broad_fifo_wr_o (broad_fifo_wr ),
.broad_addr_o (broad_addr[ADDR_WIDTH-1:0]),
.broad_type_o (broad_type[BROAD_TYPE_WIDTH-1:0]),
.broad_cpu_id_o (broad_cpu_id[1:0]),
.broad_id_o (broad_id[BROAD_ID_WIDTH-1:0])
);
 
endmodule
/trunk/src/rtl/mesi_isc_basic_fifo.v
0,0 → 1,233
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
//// ////
//// MESI_ISC Project ////
//// ////
//// Author(s): ////
//// - Yair Amitay yair.amitay@yahoo.com ////
//// www.linkedin.com/in/yairamitay ////
//// ////
//// Description ////
//// mesi_isc_basic_fifo ////
//// ------------------- ////
//// The basic fifo is a fifo for instantiation in the different ////
//// parts of the block ////
//// ////
//// To Do: ////
//// - ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`include "mesi_isc_define.v"
 
module mesi_isc_basic_fifo
(
// Inputs
clk,
rst,
wr_i,
rd_i,
data_i,
// Outputs
data_o,
status_empty_o,
status_full_o
);
parameter
DATA_WIDTH = 32,
FIFO_SIZE = 4,
FIFO_SIZE_LOG2 = 2;
 
// Inputs
//================================
// System
input clk; // System clock
input rst; // Active high system reset
 
input wr_i; // Write data to the fifo (store the data)
input rd_i; // Read data from the fifo. Data is erased
// afterward.
input [DATA_WIDTH-1:0] data_i; // Data data in to be stored
// Outputs
//================================
output [DATA_WIDTH-1:0] data_o; // Data out to be rad
// Status outputs
output status_empty_o; // There are no valid entries in the
// fifo
output status_full_o; // There are no free entries in the fifo
// all the entries are valid
 
// Regs
//================================
reg [DATA_WIDTH-1:0] data_o; // Data out to be rad
reg [DATA_WIDTH-1:0] entry [FIFO_SIZE-1:0]; // The fifo entries
reg [FIFO_SIZE_LOG2-1:0] ptr_wr; // Fifo write pointer
reg [FIFO_SIZE_LOG2-1:0] ptr_rd; // Fifo read pointer
wire [FIFO_SIZE_LOG2-1:0] ptr_rd_plus_1;
reg status_empty;
reg status_full;
wire [FIFO_SIZE_LOG2-1:0] fifo_depth; // Number of used entries
wire fifo_depth_increase;
wire fifo_depth_decrease;
integer i; // For loop
`ifdef mesi_isc_debug
reg dbg_fifo_overflow; // Sticky bit for fifo overflow
reg dbg_fifo_underflow; // Sticky bit for fifo underflow
`endif
 
// Write to the fifo
//================================
// ptr_wr
// entry array
always @(posedge clk or posedge rst)
if (rst)
begin
for(i=0; i < FIFO_SIZE; i = i + 1 )
entry[i] <= 0;
ptr_wr <= 0;
end
else if (wr_i)
begin
entry[ptr_wr] <= data_i; // Store the data_i to entry ptr_wr
ptr_wr[FIFO_SIZE_LOG2-1:0] <= ptr_wr[FIFO_SIZE_LOG2-1:0] + 1; // Increase
// the write pointer
end
 
 
// Read from the fifo
//================================
// data_o
// The fifo output data_o is sampled. It always contains the data of
// the entry[ptr_rd];
always @(posedge clk or posedge rst)
if (rst)
data_o[DATA_WIDTH-1:0] <= 0;
else if (status_empty)
data_o[DATA_WIDTH-1:0] <= data_i[DATA_WIDTH-1:0]; // When the fifo is empty
// the write data
// (if exists) is sampled to the fifo and
// to the fifo output. In a case that in
// the current cycle there is a write and
// in the next cycle there is a read, the
// data is ready in the output
else if (rd_i)
data_o[DATA_WIDTH-1:0] <= entry[ptr_rd_plus_1]; // Output the next data if this
// is a read cycle.
else
data_o[DATA_WIDTH-1:0] <= entry[ptr_rd]; // The first data is sampled and
// ready for a read
// ptr_rd
always @(posedge clk or posedge rst)
if (rst)
ptr_rd[FIFO_SIZE_LOG2-1:0] <= 0;
else if (rd_i)
ptr_rd[FIFO_SIZE_LOG2-1:0] <= ptr_rd[FIFO_SIZE_LOG2-1:0] + 1; // Increase the
// read pointer
assign ptr_rd_plus_1 = ptr_rd + 1;
 
// Status
//================================
assign status_empty_o = status_empty;
assign status_full_o = status_full;
 
// status_empty
// status_empty is set when there are no any valid entries
always @(posedge clk or posedge rst)
// On reset the fifo is empty
if (rst)
status_empty <= 1;
// There is one valid entry which is read (without write another entry)
else if (fifo_depth == 1 & fifo_depth_decrease)
status_empty <= 1;
// The fifo is empty and it is in a write cycle (without read)
// The fifo_depth == 0 when the fifo is empty and when it is full
else if (fifo_depth == 0 &
status_empty &
fifo_depth_increase)
status_empty <= 0;
always @(posedge clk or posedge rst)
// On reset the fifo not full
if (rst)
status_full <= 0;
// There is free entry which is written (without read other entry)
else if (fifo_depth == FIFO_SIZE-1 & fifo_depth_increase)
status_full <= 1;
// The fifo is full and it is in a read cycle (without write)
// The fifo_depth == 0 when the fifo is empty and when it is full
else if (fifo_depth == 0 &
status_full &
fifo_depth_decrease)
status_full <= 0;
 
// The depth of the used fifo's entries is increased when there is a write
// and there is no a read
assign fifo_depth_increase = wr_i & !rd_i;
 
// The depth of the used fifo's entries is decreased when there is a write
// and there is no a read
assign fifo_depth_decrease = !wr_i & rd_i;
// In other cases (ptr_wr & ptr_rd) or (!ptr_wr & !ptr_rd) the number of the
// valid entries remains the same
 
// Because the buffer is cyclic the depth is always correct
assign fifo_depth[FIFO_SIZE_LOG2-1:0] = ptr_wr[FIFO_SIZE_LOG2-1:0] -
ptr_rd[FIFO_SIZE_LOG2-1:0];
`ifdef mesi_isc_debug
// Debug
//================================
// dbg_fifo_overflow is a sticky bit which is set when writing (without reading)
// to a full fifo
// dbg_fifo_underflow is a sticky bit which is set when reading from an empty
// fifo
always @(posedge clk or posedge rst)
if (rst)
begin
dbg_fifo_overflow <= 0;
dbg_fifo_underflow <= 0;
end
else
begin
dbg_fifo_overflow <= dbg_fifo_overflow |
(status_full & fifo_depth_increase);
dbg_fifo_underflow <= dbg_fifo_underflow |
(status_empty & fifo_depth_decrease);
end
`endif
endmodule
/trunk/src/rtl/mesi_isc_broad.v
0,0 → 1,170
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
//// ////
//// MESI_ISC Project ////
//// ////
//// Author(s): ////
//// - Yair Amitay yair.amitay@yahoo.com ////
//// www.linkedin.com/in/yairamitay ////
//// ////
//// Description ////
//// mesi_isc_broad ////
//// ------------------- ////
//// ////
//// ////
//// To Do: ////
//// - ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`include "mesi_isc_define.v"
 
module mesi_isc_broad
(
// Inputs
clk,
rst,
cbus_ack_array_i,
broad_fifo_wr_i,
broad_addr_i,
broad_type_i,
broad_cpu_id_i,
broad_id_i,
// Outputs
cbus_addr_o,
cbus_cmd_array_o,
fifo_status_full_o
);
parameter
CBUS_CMD_WIDTH = 3,
ADDR_WIDTH = 32,
BROAD_TYPE_WIDTH = 2,
BROAD_ID_WIDTH = 5,
BROAD_REQ_FIFO_SIZE = 4,
BROAD_REQ_FIFO_SIZE_LOG2 = 2;
// Inputs
//================================
// System
input clk; // System clock
input rst; // Active high system reset
// Coherence bus
input [3:0] cbus_ack_array_i;
input broad_fifo_wr_i; // Write the broadcast request
input [ADDR_WIDTH-1:0] broad_addr_i; // Broad addresses
input [BROAD_TYPE_WIDTH-1:0] broad_type_i; // Broad type
input [1:0] broad_cpu_id_i; // Initiators
// CPU id array
input [BROAD_ID_WIDTH-1:0] broad_id_i; // Broadcast request ID array
 
// Outputs
//================================
 
output [ADDR_WIDTH-1:0] cbus_addr_o; // Coherence bus address. All busses have
// the same address
output [4*CBUS_CMD_WIDTH-1:0] cbus_cmd_array_o; // See broad_addr_i
 
output fifo_status_full_o; // The broad fifo is full
// Regs & wires
//================================
wire broad_fifo_rd; // Read broadcast
wire fifo_status_empty; // Status empty
wire fifo_status_full; // The broad fifo is full
wire [ADDR_WIDTH-1:0] broad_snoop_addr; // Address of broadcast snooping
wire [BROAD_TYPE_WIDTH-1:0] broad_snoop_type; // Type of broadcast snooping
wire [1:0] broad_snoop_cpu_id; // ID of initiator of broadcast
// snooping
wire [BROAD_ID_WIDTH-1:0] broad_snoop_id; // Broadcast snooping ID
\
// assign
//================================
assign cbus_addr_o[ADDR_WIDTH-1:0] = broad_snoop_addr[ADDR_WIDTH-1:0];
assign fifo_status_full_o = fifo_status_full;
// Breq fifo control
//================================
mesi_isc_broad_cntl #(CBUS_CMD_WIDTH,
BROAD_TYPE_WIDTH,
BROAD_ID_WIDTH)
mesi_isc_broad_cntl
(
// Inputs
.clk (clk),
.rst (rst),
// Coherence buses
.cbus_ack_array_i (cbus_ack_array_i[3:0]),
// broad_fifo
.fifo_status_empty_i (fifo_status_empty),
.fifo_status_full_i (fifo_status_full),
// broad_fifo
.broad_snoop_type_i (broad_snoop_type[BROAD_TYPE_WIDTH-1:0]),
.broad_snoop_cpu_id_i (broad_snoop_cpu_id[1:0]),
.broad_snoop_id_i (broad_snoop_id[BROAD_ID_WIDTH-1:0]),
// Outputs
// Coherence buses
.cbus_cmd_array_o (cbus_cmd_array_o[4*CBUS_CMD_WIDTH-1:0]),
// fifo
.broad_fifo_rd_o (broad_fifo_rd)
);
 
// broad fifo
//================================
mesi_isc_basic_fifo #(ADDR_WIDTH + // DATA_WIDTH
BROAD_TYPE_WIDTH +
2 + // BROAD_CPU_ID_WIDTH
BROAD_ID_WIDTH,
BROAD_REQ_FIFO_SIZE, // FIFO_SIZE
BROAD_REQ_FIFO_SIZE_LOG2) // FIFO_SIZE_LOG2
// \ / (\ / marks the fifo ID)
broad_fifo
(
// Inputs
.clk (clk),
.rst (rst),
.wr_i (broad_fifo_wr_i),
.rd_i (broad_fifo_rd),
.data_i ({broad_addr_i[ADDR_WIDTH-1:0],
broad_type_i[BROAD_TYPE_WIDTH-1:0],
broad_cpu_id_i[1:0],
broad_id_i[BROAD_ID_WIDTH-1:0]
}),
// Outputs
.data_o ({broad_snoop_addr[ADDR_WIDTH-1:0],
broad_snoop_type[BROAD_TYPE_WIDTH-1:0],
broad_snoop_cpu_id[1:0],
broad_snoop_id[BROAD_ID_WIDTH-1:0]
}),
.status_empty_o (fifo_status_empty),
.status_full_o (fifo_status_full)
);
 
endmodule
/trunk/src/rtl/mesi_isc_broad_cntl.v
0,0 → 1,314
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
//// ////
//// MESI_ISC Project ////
//// ////
//// Author(s): ////
//// - Yair Amitay yair.amitay@yahoo.com ////
//// www.linkedin.com/in/yairamitay ////
//// ////
//// Description ////
//// mesi_isc_broad_cntl ////
//// ------------------- ////
//// ////
//// ////
//// To Do: ////
//// - ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`include "mesi_isc_define.v"
 
module mesi_isc_broad_cntl
(
// Inputs
clk,
rst,
cbus_ack_array_i,
fifo_status_empty_i,
fifo_status_full_i,
broad_snoop_type_i,
broad_snoop_cpu_id_i,
broad_snoop_id_i,
// Outputs
cbus_cmd_array_o,
broad_fifo_rd_o
);
parameter
CBUS_CMD_WIDTH = 3,
BROAD_TYPE_WIDTH = 2,
BROAD_ID_WIDTH = 5;
// Inputs
//================================
// System
input clk; // System clock
input rst; // Active high system reset
// Coherence buses
input [3:0] cbus_ack_array_i;
// broad_fifo
input fifo_status_empty_i;
input fifo_status_full_i;
// broad_fifo
input [BROAD_TYPE_WIDTH-1:0] broad_snoop_type_i; // The type of the broad
input [1:0] broad_snoop_cpu_id_i; // The ID of the initiator CPU
input [BROAD_ID_WIDTH-1:0] broad_snoop_id_i; // The ID of the broad
// Outputs
//================================
output [4*CBUS_CMD_WIDTH-1:0] cbus_cmd_array_o; // Command for coherence bus.
// write broadcast, read broadcast, write
// enable or read enable
// fifo
output broad_fifo_rd_o;
 
// Regs & wires
//================================
wire [CBUS_CMD_WIDTH-1:0] cbus_cmd3; // Command for coherence bus.
wire [CBUS_CMD_WIDTH-1:0] cbus_cmd2; // Command for coherence bus.
wire [CBUS_CMD_WIDTH-1:0] cbus_cmd1; // Command for coherence bus.
wire [CBUS_CMD_WIDTH-1:0] cbus_cmd0; // Command for coherence bus.
reg broadcast_in_progress; // A broadcast process
// contains 2 stages. The first stage is
// to send read or write broadcast to
// all CPUs and to receive an
// acknowledge for each one. The second
// stage is to send an
// enable-access to the initiator CPU.
reg [3:0] cbus_active_broad_array; // For each bit, when high a
// broad access is sent to the CPU
reg [3:0] cbus_active_en_access_array; // For each bit, when
// hing a enable-access is sent to the
// CPU
reg broad_fifo_rd_o; // output
wire [3:0] cbus_active_en_access_and_not_cbus_ack_array;
//cbus_cmd
assign cbus_cmd_array_o[(3+1)*CBUS_CMD_WIDTH-1 : 3*CBUS_CMD_WIDTH] = cbus_cmd3;
assign cbus_cmd_array_o[(2+1)*CBUS_CMD_WIDTH-1 : 2*CBUS_CMD_WIDTH] = cbus_cmd2;
assign cbus_cmd_array_o[(1+1)*CBUS_CMD_WIDTH-1 : 1*CBUS_CMD_WIDTH] = cbus_cmd1;
assign cbus_cmd_array_o[(0+1)*CBUS_CMD_WIDTH-1 : 0*CBUS_CMD_WIDTH] = cbus_cmd0;
 
// The command of the coherence bus is define according to the state of
// cbus_active_broad_array and cbus_active_en_access_array
// \ /
assign cbus_cmd3 =
// The broadcast proccess is active. Send the broadcast request
// \ /
cbus_active_broad_array[3] ?
broad_snoop_type_i == `MESI_ISC_BREQ_TYPE_WR ?
`MESI_ISC_CBUS_CMD_WR_SNOOP:
`MESI_ISC_CBUS_CMD_RD_SNOOP :
// All the broadcast proccesses were done. This CPU is the initiator
// of the request. Enable it to continue by send en_wr/en_rd
!(|cbus_active_broad_array) &
// \ /
cbus_active_en_access_array[3] &
~broad_fifo_rd_o ?
broad_snoop_type_i == `MESI_ISC_BREQ_TYPE_WR ?
`MESI_ISC_CBUS_CMD_EN_WR:
`MESI_ISC_CBUS_CMD_EN_RD :
`MESI_ISC_CBUS_CMD_NOP;
// \ /
assign cbus_cmd2 =
// \ /
cbus_active_broad_array[2] ?
broad_snoop_type_i == `MESI_ISC_BREQ_TYPE_WR ?
`MESI_ISC_CBUS_CMD_WR_SNOOP:
`MESI_ISC_CBUS_CMD_RD_SNOOP :
!(|cbus_active_broad_array) &
// \ /
cbus_active_en_access_array[2] &
~broad_fifo_rd_o ?
broad_snoop_type_i == `MESI_ISC_BREQ_TYPE_WR ?
`MESI_ISC_CBUS_CMD_EN_WR:
`MESI_ISC_CBUS_CMD_EN_RD :
`MESI_ISC_CBUS_CMD_NOP;
// \ /
assign cbus_cmd1 =
// \ /
cbus_active_broad_array[1] ?
broad_snoop_type_i == `MESI_ISC_BREQ_TYPE_WR ?
`MESI_ISC_CBUS_CMD_WR_SNOOP:
`MESI_ISC_CBUS_CMD_RD_SNOOP :
!(|cbus_active_broad_array) &
// \ /
cbus_active_en_access_array[1] &
~broad_fifo_rd_o ?
broad_snoop_type_i == `MESI_ISC_BREQ_TYPE_WR ?
`MESI_ISC_CBUS_CMD_EN_WR:
`MESI_ISC_CBUS_CMD_EN_RD :
`MESI_ISC_CBUS_CMD_NOP;
// \ /
assign cbus_cmd0 =
// Send read or write broad according to the type of the broad.
// \ /
cbus_active_broad_array[0] ?
broad_snoop_type_i == `MESI_ISC_BREQ_TYPE_WR ?
`MESI_ISC_CBUS_CMD_WR_SNOOP:
`MESI_ISC_CBUS_CMD_RD_SNOOP :
!(|cbus_active_broad_array) &
// \ /
cbus_active_en_access_array[0] &
~broad_fifo_rd_o ?
broad_snoop_type_i == `MESI_ISC_BREQ_TYPE_WR ?
`MESI_ISC_CBUS_CMD_EN_WR:
`MESI_ISC_CBUS_CMD_EN_RD :
 
`MESI_ISC_CBUS_CMD_NOP;
 
 
// A broadcast process contains 5 sub-processes: Each one of the 4 CPU receives
// a snoop request and answers with an acknowledge. Then the initiator CPU
// receives an access enable and answer answers with an acknowledge.
//
// The broadcast process *stages* are:
// 1. Curently there is no an active process. If there is a valid broadcast to
// send then:
// 1.1 broadcast_in_progress <= 1 : It represents an active process of
// broadcast. It contains 4 snoop sub-processes and 1 enable sub-process.
// 1.2 cbus_active_broad_array <= 4'b1111 : Each bit represents an active
// sub-process, for each CPU - sending a snoop request and get an answer
// with an acknowledge.
// 1.3 cbus_active_en_access_array[ID of initiator CPU] <= 1
// The corresponding bit of the initiator CPU in the
// cbus_active_en_access_array is set to enable in stage 4 to send an
// enable-access to the initiator CPU.
// 2. cbus_active_broad_array[ID of CPU] <= 0
// A snoop request is send for all the CPUs. For each CPU that answers with
// acknowledge the corresponding bit is clear:
// cbus_active_broad_array == 0
// After all CPUs answer with acknowledge all the bits of
// cbus_active_broad_array are clear.
// 3. cbus_active_en_access_array[ID of initiator CPU] <= 0
// broadcast_in_progress <= 0
// The enable access is sent to the initiator CPU. When it answers with an
// acknowledge then the broadcast process is finished: the corresponding
// bit in the cbus_active_en_access_array is clear and
// the broadcast_in_progress is clear
//
//
// broadcast_in_progress
// There is an active action of the broadcast. Either not all CPU received the
// broadcast and return acknowledge. or the initiator CPU received the access
// enable and return acknowledge.
//
// cbus_active_broad_array
// For each bit, when set - there is an active process of sending a snoop
// request and answering with an acknowledge.
//
// cbus_active_en_access_array
// For each bit, when set - there is an active process of sending
// enable-access request to the initiator CPU and receive an acknowledge answer.
// The enable-access request is send only after all CPUs receive and approve
// the snoop requests.
//
// broad_fifo_rd_o
// When broadcast process in finish clear the corresponding entry from the fifo
always @(posedge clk or posedge rst)
if (rst)
begin
broadcast_in_progress <= 0;
cbus_active_broad_array <= 4'b0000;
cbus_active_en_access_array <= 4'b0000;
broad_fifo_rd_o <= 0;
end
else if (~broadcast_in_progress & ~broad_fifo_rd_o)
if (~fifo_status_empty_i)
// Stage 1
begin
broadcast_in_progress <= 1;
case (broad_snoop_cpu_id_i) // The initiator does not received a
// broadcast for the same line it asks the
// broadcast
0:
begin
cbus_active_broad_array <= 4'b1110;
cbus_active_en_access_array <= 4'b0001;
end
1:
begin
cbus_active_broad_array <= 4'b1101;
cbus_active_en_access_array <= 4'b0010;
end
2:
begin
cbus_active_broad_array <= 4'b1011;
cbus_active_en_access_array <= 4'b0100;
end
3:
begin
cbus_active_broad_array <= 4'b0111;
cbus_active_en_access_array <= 4'b1000;
end
default
begin
cbus_active_broad_array <= 4'b0000;
cbus_active_en_access_array <= 4'b0000;
end
endcase
broad_fifo_rd_o <= 0;
end
else // if (~fifo_status_empty_i)
begin
broadcast_in_progress <= 0;
cbus_active_broad_array <= 4'b0000;
cbus_active_en_access_array <= 4'b0000;
broad_fifo_rd_o <= 0;
end
else // if (~broadcast_in_progress)
// Stage 2
if (|cbus_active_broad_array) // There is at least on active snoop
// sub-process
begin
broadcast_in_progress <= 1;
// Clear related sub-process of a CPU then returns ack for the snoop
// request.
cbus_active_broad_array <= cbus_active_broad_array &
~cbus_ack_array_i;
cbus_active_en_access_array <= cbus_active_en_access_array;
broad_fifo_rd_o <= 0;
end
// Stage 3
else if (broad_fifo_rd_o) // All snoop sub-process were done
begin
broadcast_in_progress <= 0;
cbus_active_broad_array <= 0;
cbus_active_en_access_array <= 0;
broad_fifo_rd_o <= 0;
end
else
broad_fifo_rd_o <= !(|(cbus_active_en_access_and_not_cbus_ack_array));
 
assign cbus_active_en_access_and_not_cbus_ack_array =
cbus_active_en_access_array & ~cbus_ack_array_i;
 
endmodule
/trunk/src/rtl/mesi_isc_define.v
0,0 → 1,63
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
//// ////
//// MESI_ISC Project ////
//// ////
//// Author(s): ////
//// - Yair Amitay yair.amitay@yahoo.com ////
//// www.linkedin.com/in/yairamitay ////
//// ////
//// Description ////
//// mesi_isc_define ////
//// ------------------- ////
//// Contains the timescale and the define declaration of the ////
//// block ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ns / 1ps
 
// Main Bus commands
`define MESI_ISC_MBUS_CMD_NOP 3'd0
`define MESI_ISC_MBUS_CMD_WR 3'd1
`define MESI_ISC_MBUS_CMD_RD 3'd2
`define MESI_ISC_MBUS_CMD_WR_BROAD 3'd3
`define MESI_ISC_MBUS_CMD_RD_BROAD 3'd4
 
// Coherence Bus commands
`define MESI_ISC_CBUS_CMD_NOP 3'd0
`define MESI_ISC_CBUS_CMD_WR_SNOOP 3'd1
`define MESI_ISC_CBUS_CMD_RD_SNOOP 3'd2
`define MESI_ISC_CBUS_CMD_EN_WR 3'd3
`define MESI_ISC_CBUS_CMD_EN_RD 3'd4
// BREQ_TYPE
`define MESI_ISC_BREQ_TYPE_NOP 2'd0
`define MESI_ISC_BREQ_TYPE_WR 2'd1
`define MESI_ISC_BREQ_TYPE_RD 2'd2
/trunk/src/rtl/README.txt
0,0 → 1,7
MESI_ISC Project
=================
 
Directoy: rtl
=================
 
Contains all the project`s RTL files.
/trunk/src/rtl/mesi_isc_breq_fifos.v
0,0 → 1,396
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
//// ////
//// MESI_ISC Project ////
//// ////
//// Author(s): ////
//// - Yair Amitay yair.amitay@yahoo.com ////
//// www.linkedin.com/in/yairamitay ////
//// ////
//// Description ////
//// mesi_isc_breq_fifos ////
//// ------------------- ////
//// Stores all the snoop transactions. Keeps the transactions ////
//// until the cpu receives the transactions ////
//// ////
//// The functional ports of the block are arranged in arrays. ////
//// Each functional port is an array which contains one signal ////
//// for each snoop fifo. ////
//// The order of the signals, of width X (each signal has ////
//// X-1:0 bits), in the port is described below. ////
//// All the bits of the first signal are located in the port ////
//// least significant bits. Then, the second signal is located ////
//// in the next X bits, etc. ////
//// ////
//// For a port that contains M (M>1) signals of width X (X>0) ////
//// signal_N[X-1:0] = port[(N+1)*X-1:N*X]. ////
//// ////
//// For example for a port with 4 signals of 8 bits ////
//// signal_0[7:0] = port[(N+1)*X-1:N*X] = port[(N+1)*8-1:N*8] = ////
//// = port[(0+1)*8-1:0*8] = port[7:0] ////
//// signal_1[7:0] = port[(1+1)*8-1:1*8] = port[15:8] ////
//// signal_2[7:0] = port[(2+1)*8-1:2*8] = port[23:16] ////
//// signal_3[7:0] = port[(3+1)*8-1:3*8] = port[31:24] ////
//// ////
//// To Do: ////
//// - ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`include "mesi_isc_define.v"
 
module mesi_isc_breq_fifos
(
// Inputs
clk,
rst,
mbus_cmd_array_i,
mbus_addr_array_i,
broad_fifo_status_full_i,
// Outputs
mbus_ack_array_o,
broad_fifo_wr_o,
broad_addr_o,
broad_type_o,
broad_cpu_id_o,
broad_id_o
);
parameter
MBUS_CMD_WIDTH = 3,
ADDR_WIDTH = 32,
BROAD_TYPE_WIDTH = 2,
BROAD_ID_WIDTH = 7,
BREQ_FIFO_SIZE = 2,
BREQ_FIFO_SIZE_LOG2 = 1;
// Inputs
//================================
// System
input clk; // System clock
input rst; // Active high system reset
 
// Main buses
input [4*MBUS_CMD_WIDTH-1:0] mbus_cmd_array_i; // Main bus command (array)
input [4*ADDR_WIDTH-1:0] mbus_addr_array_i; // Main bus address (array)
 
// From mesi_isc_broad_fifo
input broad_fifo_status_full_i; // The broad fifo is full
// and can't receive another broadcast
// request
// Outputs
//================================
// Main buses
output [3:0] mbus_ack_array_o; // Bus acknowledge for receiving the
// broadcast request
// To mesi_isc_broad_fifo
output broad_fifo_wr_o; // Write the broadcast request
output [ADDR_WIDTH-1:0] broad_addr_o; // Address of the broadcast request
output [BROAD_TYPE_WIDTH-1:0] broad_type_o; // Type of the broadcast request
output [1:0] broad_cpu_id_o; // ID of the initiator CPU
// broad in the broad fifo
output [BROAD_ID_WIDTH-1:0] broad_id_o; // The ID of the broadcast request
 
 
// Regs & wires
//================================
wire [3:0] fifo_status_empty_array;
wire [3:0] fifo_status_full_array;
wire [4*ADDR_WIDTH-1:0] broad_addr_array;
wire [4*BROAD_TYPE_WIDTH-1:0] broad_type_array;
wire [4*BROAD_ID_WIDTH-1:0] broad_id_array;
wire [3:0] fifo_wr_array;
wire [3:0] fifo_rd_array;
wire [4*BROAD_TYPE_WIDTH-1:0] breq_type_array;
wire [4*2-1:0] breq_cpu_id_array;
wire [4*BROAD_ID_WIDTH-1:0] breq_id_array;
wire [4*2-1:0] broad_cpu_id_array;
// Breq fifo control
//================================
mesi_isc_breq_fifos_cntl #(MBUS_CMD_WIDTH,
ADDR_WIDTH,
BROAD_TYPE_WIDTH,
BROAD_ID_WIDTH)
mesi_isc_breq_fifos_cntl
(
// Inputs
.clk (clk),
.rst (rst),
.mbus_cmd_array_i (mbus_cmd_array_i [4*MBUS_CMD_WIDTH-1 :0]),
.fifo_status_empty_array_i (fifo_status_empty_array [3:0]),
.fifo_status_full_array_i (fifo_status_full_array [3:0]),
.broad_fifo_status_full_i (broad_fifo_status_full_i),
.broad_addr_array_i (broad_addr_array [4*ADDR_WIDTH-1 :0]),
.broad_type_array_i (broad_type_array [4*BROAD_TYPE_WIDTH-1 :0]),
.broad_id_array_i (broad_id_array [4*BROAD_ID_WIDTH-1 :0]),
// Outputs
.mbus_ack_array_o (mbus_ack_array_o [3:0]),
.fifo_wr_array_o (fifo_wr_array [3:0]),
.fifo_rd_array_o (fifo_rd_array [3:0]),
.broad_fifo_wr_o (broad_fifo_wr_o),
.broad_addr_o (broad_addr_o [ADDR_WIDTH-1 :0]),
.broad_type_o (broad_type_o [BROAD_TYPE_WIDTH-1 :0]),
.broad_cpu_id_o (broad_cpu_id_o [1:0]),
.broad_id_o (broad_id_o [BROAD_ID_WIDTH-1 :0]),
.breq_type_array_o (breq_type_array [4*BROAD_TYPE_WIDTH-1 :0]),
.breq_cpu_id_array_o (breq_cpu_id_array [4*2-1 :0]),
.breq_id_array_o (breq_id_array [4*BROAD_ID_WIDTH-1 :0])
);
 
// Breq fifo 3
//================================
mesi_isc_basic_fifo #(ADDR_WIDTH + // DATA_WIDTH
BROAD_TYPE_WIDTH +
2 + // BROAD_CPU_ID_WIDTH
BROAD_ID_WIDTH,
BREQ_FIFO_SIZE, // FIFO_SIZE
BREQ_FIFO_SIZE_LOG2) // FIFO_SIZE_LOG2
// \ / (\ / marks the fifo ID)
fifo_3
(
// Inputs
.clk (clk),
.rst (rst),
// \ /
.wr_i (fifo_wr_array[3]),
// \ /
.rd_i (fifo_rd_array[3]),
// \ /
.data_i ({mbus_addr_array_i[(3+1)*ADDR_WIDTH-1:
// \ /
3*ADDR_WIDTH],
// \ /
breq_type_array [(3+1)*BROAD_TYPE_WIDTH-1:
// \ /
3*BROAD_TYPE_WIDTH],
// \ /
breq_cpu_id_array[(3+1)*2-1:
// \ /
3*2],
// \ /
breq_id_array [(3+1)*BROAD_ID_WIDTH-1:
// \ /
3*BROAD_ID_WIDTH]}),
// Outputs
// // \ /
.data_o ({broad_addr_array [(3+1)*ADDR_WIDTH-1:
// \ /
3*ADDR_WIDTH],
// \ /
broad_type_array [(3+1)*BROAD_TYPE_WIDTH-1:
// \ /
3*BROAD_TYPE_WIDTH],
// \ /
broad_cpu_id_array[(3+1)*2-1:
// \ /
3*2],
// \ /
broad_id_array [(3+1)*BROAD_ID_WIDTH-1:
// \ /
3*BROAD_ID_WIDTH]}),
// \ /
.status_empty_o (fifo_status_empty_array [3]),
// \ /
.status_full_o (fifo_status_full_array [3])
);
 
// Breq fifo 2
//================================
mesi_isc_basic_fifo #(ADDR_WIDTH + // DATA_WIDTH
BROAD_TYPE_WIDTH +
2 + // BROAD_CPU_ID_WIDTH
BROAD_ID_WIDTH,
BREQ_FIFO_SIZE, // FIFO_SIZE
BREQ_FIFO_SIZE_LOG2) // FIFO_SIZE_LOG2
// \ / (\ / marks the fifo ID)
fifo_2
(
// Inputs
.clk (clk),
.rst (rst),
// \ /
.wr_i (fifo_wr_array[2]),
// \ /
.rd_i (fifo_rd_array[2]),
// \ /
.data_i ({mbus_addr_array_i[(2+1)*ADDR_WIDTH-1:
// \ /
2*ADDR_WIDTH],
// \ /
breq_type_array [(2+1)*BROAD_TYPE_WIDTH-1:
// \ /
2*BROAD_TYPE_WIDTH],
// \ /
breq_cpu_id_array[(2+1)*2-1:
// \ /
2*2],
// \ /
breq_id_array [(2+1)*BROAD_ID_WIDTH-1:
// \ /
2*BROAD_ID_WIDTH]}),
// Outputs
// // \ /
.data_o ({broad_addr_array [(2+1)*ADDR_WIDTH-1:
// \ /
2*ADDR_WIDTH],
// \ /
broad_type_array [(2+1)*BROAD_TYPE_WIDTH-1:
// \ /
2*BROAD_TYPE_WIDTH],
// \ /
broad_cpu_id_array[(2+1)*2-1:
// \ /
2*2],
// \ /
broad_id_array [(2+1)*BROAD_ID_WIDTH-1:
// \ /
2*BROAD_ID_WIDTH]}),
// \ /
.status_empty_o (fifo_status_empty_array [2]),
// \ /
.status_full_o (fifo_status_full_array [2])
);
 
// Breq fifo 1
//================================
mesi_isc_basic_fifo #(ADDR_WIDTH + // DATA_WIDTH
BROAD_TYPE_WIDTH +
2 + // BROAD_CPU_ID_WIDTH
BROAD_ID_WIDTH,
BREQ_FIFO_SIZE, // FIFO_SIZE
BREQ_FIFO_SIZE_LOG2) // FIFO_SIZE_LOG2
// \ / (\ / marks the fifo ID)
fifo_1
(
// Inputs
.clk (clk),
.rst (rst),
// \ /
.wr_i (fifo_wr_array[1]),
// \ /
.rd_i (fifo_rd_array[1]),
// \ /
.data_i ({mbus_addr_array_i[(1+1)*ADDR_WIDTH-1:
// \ /
1*ADDR_WIDTH],
// \ /
breq_type_array [(1+1)*BROAD_TYPE_WIDTH-1:
// \ /
1*BROAD_TYPE_WIDTH],
// \ /
breq_cpu_id_array[(1+1)*2-1:
// \ /
1*2],
// \ /
breq_id_array [(1+1)*BROAD_ID_WIDTH-1:
// \ /
1*BROAD_ID_WIDTH]}),
// Outputs
// // \ /
.data_o ({broad_addr_array [(1+1)*ADDR_WIDTH-1:
// \ /
1*ADDR_WIDTH],
// \ /
broad_type_array [(1+1)*BROAD_TYPE_WIDTH-1:
// \ /
1*BROAD_TYPE_WIDTH],
// \ /
broad_cpu_id_array[(1+1)*2-1:
// \ /
1*2],
// \ /
broad_id_array [(1+1)*BROAD_ID_WIDTH-1:
// \ /
1*BROAD_ID_WIDTH]}),
// \ /
.status_empty_o (fifo_status_empty_array [1]),
// \ /
.status_full_o (fifo_status_full_array [1])
);
 
// Breq fifo 0
//================================
mesi_isc_basic_fifo #(ADDR_WIDTH + // DATA_WIDTH
BROAD_TYPE_WIDTH +
2 + // BROAD_CPU_ID_WIDTH
BROAD_ID_WIDTH,
BREQ_FIFO_SIZE, // FIFO_SIZE
BREQ_FIFO_SIZE_LOG2) // FIFO_SIZE_LOG2
// \ / (\ / marks the fifo ID)
fifo_0
(
// Inputs
.clk (clk),
.rst (rst),
// \ /
.wr_i (fifo_wr_array[0]),
// \ /
.rd_i (fifo_rd_array[0]),
// \ /
.data_i ({mbus_addr_array_i[(0+1)*ADDR_WIDTH-1:
// \ /
0*ADDR_WIDTH],
// \ /
breq_type_array [(0+1)*BROAD_TYPE_WIDTH-1:
// \ /
0*BROAD_TYPE_WIDTH],
// \ /
breq_cpu_id_array[(0+1)*2-1:
// \ /
0*2],
// \ /
breq_id_array [(0+1)*BROAD_ID_WIDTH-1:
// \ /
0*BROAD_ID_WIDTH]}),
// Outputs
// // \ /
.data_o ({broad_addr_array [(0+1)*ADDR_WIDTH-1:
// \ /
0*ADDR_WIDTH],
// \ /
broad_type_array [(0+1)*BROAD_TYPE_WIDTH-1:
// \ /
0*BROAD_TYPE_WIDTH],
// \ /
broad_cpu_id_array[(0+1)*2-1:
// \ /
0*2],
// \ /
broad_id_array [(0+1)*BROAD_ID_WIDTH-1:
// \ /
0*BROAD_ID_WIDTH]}),
// \ /
.status_empty_o (fifo_status_empty_array [0]),
// \ /
.status_full_o (fifo_status_full_array [0])
);
 
endmodule
/trunk/src/rtl/mesi_isc_breq_fifos_cntl.v
0,0 → 1,376
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
//// ////
//// MESI_ISC Project ////
//// ////
//// Author(s): ////
//// - Yair Amitay yair.amitay@yahoo.com ////
//// www.linkedin.com/in/yairamitay ////
//// ////
//// Description ////
//// mesi_isc_breq_fifos_cntl ////
//// ------------------- ////
//// Controls and muxes of the mesi_isc_breq_fifos. This module ////
//// contains all the controls and logic of the ////
//// mesi_isc_breq_fifos_cntl ////
//// ////
//// To Do: ////
//// - ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`include "mesi_isc_define.v"
 
module mesi_isc_breq_fifos_cntl
(
// Inputs
clk,
rst,
mbus_cmd_array_i,
fifo_status_empty_array_i,
fifo_status_full_array_i,
broad_fifo_status_full_i,
broad_addr_array_i,
broad_type_array_i,
broad_id_array_i,
// Outputs
mbus_ack_array_o,
fifo_wr_array_o,
fifo_rd_array_o,
broad_fifo_wr_o,
broad_addr_o,
broad_type_o,
broad_cpu_id_o,
broad_id_o,
breq_type_array_o,
breq_cpu_id_array_o,
breq_id_array_o
);
parameter
MBUS_CMD_WIDTH = 3,
ADDR_WIDTH = 32,
BROAD_TYPE_WIDTH = 2,
BROAD_ID_WIDTH = 7;
// Inputs
//================================
// System
input clk; // System clock
input rst; // Active high system reset
 
// Main buses
// The mbus commands, according to the commend the breq are written to
// the fifos
input [4*MBUS_CMD_WIDTH-1:0] mbus_cmd_array_i;
// cntl
// breq fifo status
input [3:0] fifo_status_empty_array_i;
input [3:0] fifo_status_full_array_i;
// broad_fifo
// breqs can be written to the broad fifo when it is not full
input broad_fifo_status_full_i;
// mux
// The mux sends to the broad fifo one of the broad from the 4 breq fifos.
// It sends: address. type, cpu_id, broad_id
input [4*ADDR_WIDTH-1 :0] broad_addr_array_i;
input [4*BROAD_TYPE_WIDTH-1:0] broad_type_array_i;
input [4*BROAD_ID_WIDTH-1 :0] broad_id_array_i;
// Outputs
// Main busses
// When a breq is stored to a fifo an acknowledge is send to the initiator
output [3:0] mbus_ack_array_o;
// cntl
// Write the breq to one of the fifos
output [3:0] fifo_wr_array_o;
// Read a breq toward the broad fifo
output [3:0] fifo_rd_array_o;
// broad_fifo
// Command to fifo for a broad in the broad fifo
output broad_fifo_wr_o;
// The broad information that is send to the broad fifo: address. type, cpu_id
// and broad_id
output [ADDR_WIDTH-1 :0] broad_addr_o;
output [BROAD_TYPE_WIDTH-1:0] broad_type_o;
output [1:0] broad_cpu_id_o;
output [BROAD_ID_WIDTH-1: 0] broad_id_o;
// fifo inputs
// Some of the breq fifo input are manipulate before storing
// The type in manipulation of the mbus command
output [4*BROAD_TYPE_WIDTH-1:0] breq_type_array_o;
// Each CPU has a fixed ID
output [4*2-1:0] breq_cpu_id_array_o;
// Each breq has a unique ID.
output [4*BROAD_ID_WIDTH-1:0] breq_id_array_o;
 
// Regs & wires
//================================
reg [3:0] mbus_ack_array;
reg [3:0] fifos_priority; // A one hot priority between the
// breq fifos toward the broad fifo
wire [3:0] fifos_priority_barrel_shiftl_1,
fifos_priority_barrel_shiftl_2,
fifos_priority_barrel_shiftl_3;
wire [3:0] fifo_select_oh; // A one hot control of the mux between
// breq fifos toward the broad fifo
reg [BROAD_ID_WIDTH-3:0] breq_id_base; // breq_id_base is the base value of
// the IDs. breq_id_base = breq_id/4
wire [MBUS_CMD_WIDTH-1:0] mbus_cmd_array_i_3,
mbus_cmd_array_i_2,
mbus_cmd_array_i_1,
mbus_cmd_array_i_0;
reg [4*BROAD_TYPE_WIDTH-1:0] breq_type_array_o;
// Assigns for outputs
//================================
assign mbus_ack_array_o = mbus_ack_array;
 
 
// fifo_rd_array_o, broad_fifo_wr_o
// Read the breq from one of the breq fifos and write it to the broad fifo.
assign fifo_rd_array_o = {4{~broad_fifo_status_full_i}} & // There is space in
// the broad fifo
fifo_select_oh[3:0]; // The highest priority
// fifo that has a valid breq.
assign broad_fifo_wr_o = |fifo_rd_array_o[3:0]; // Write to the broad fifo is
// done in parallel to Read from one of
// the breq fifo The values set
// fifos_priority, fifos_priority_barrel_shift_1/2/3 (one hot)
// The priority between the CPU is done in round robin order.
// The breq which is sent to the broad fifo is selected according to
// the value of the fifos_priority register, from the low value to the high
// value.
// For example when fifos_priority == 2 then the priority order is:
// 2 -> 3 -> 0 -> 1. The breq is sent from the first breq fifo, in that order,
// that has a valid breq.
// The priority is change whenever a breq is sent to the broad fifo
always @(posedge clk or posedge rst)
if (rst)
fifos_priority <= 1;
else if (broad_fifo_wr_o)
fifos_priority[3:0] <= fifos_priority_barrel_shiftl_1[3:0];
 
assign fifos_priority_barrel_shiftl_3[3:0] =
{fifos_priority[0] , fifos_priority[3:1]};
assign fifos_priority_barrel_shiftl_2[3:0] =
{fifos_priority[1:0], fifos_priority[3:2]};
assign fifos_priority_barrel_shiftl_1[3:0] =
{fifos_priority[2:0], fifos_priority[3]};
// fifo_select_oh (one hot)
// Points to the highest priority fifo (see fifos_priority) that
// has a valid breq.
// The control of the mux from the breq fifos to the broad fifo.
assign fifo_select_oh[3:0] =
// If the 1st highest priority fifo is not empty then select it
// Or the bit-wise results of the following formula to one result
// Bit-wise set for fifos that are not empty
|(~fifo_status_empty_array_i[3:0] &
// Bit-wise one hot priority for the 1st highest priority
fifos_priority[3:0] ) ?
fifos_priority[3:0] :
|(~fifo_status_empty_array_i[3:0] &
fifos_priority_barrel_shiftl_1[3:0] ) ?
fifos_priority_barrel_shiftl_1[3:0] :
|(~fifo_status_empty_array_i[3:0] &
fifos_priority_barrel_shiftl_2[3:0] ) ?
fifos_priority_barrel_shiftl_2[3:0] :
|(~fifo_status_empty_array_i[3:0] &
fifos_priority_barrel_shiftl_3[3:0] ) ?
fifos_priority_barrel_shiftl_3[3:0] :
4'd0;
// broad_addr_o, broad_type_o, broad_cpu_id_o, broad_id_o
// One hot mux
assign broad_addr_o[ADDR_WIDTH-1:0] =
broad_addr_array_i[(3+1)*ADDR_WIDTH-1 : 3*ADDR_WIDTH] &
{ADDR_WIDTH{fifo_select_oh[3]}} |
broad_addr_array_i[(2+1)*ADDR_WIDTH-1 : 2*ADDR_WIDTH] &
{ADDR_WIDTH{fifo_select_oh[2]}} |
broad_addr_array_i[(1+1)*ADDR_WIDTH-1 : 1*ADDR_WIDTH] &
{ADDR_WIDTH{fifo_select_oh[1]}} |
broad_addr_array_i[(0+1)*ADDR_WIDTH-1 : 0*ADDR_WIDTH] &
{ADDR_WIDTH{fifo_select_oh[0]}};
assign broad_type_o[BROAD_TYPE_WIDTH-1:0] =
broad_type_array_i[(3+1)*BROAD_TYPE_WIDTH-1 : 3*BROAD_TYPE_WIDTH] &
{BROAD_TYPE_WIDTH{fifo_select_oh[3]}} |
broad_type_array_i[(2+1)*BROAD_TYPE_WIDTH-1 : 2*BROAD_TYPE_WIDTH] &
{BROAD_TYPE_WIDTH{fifo_select_oh[2]}} |
broad_type_array_i[(1+1)*BROAD_TYPE_WIDTH-1 : 1*BROAD_TYPE_WIDTH] &
{BROAD_TYPE_WIDTH{fifo_select_oh[1]}} |
broad_type_array_i[(0+1)*BROAD_TYPE_WIDTH-1 : 0*BROAD_TYPE_WIDTH] &
{BROAD_TYPE_WIDTH{fifo_select_oh[0]}};
// Each CPU has a fixed ID
assign broad_cpu_id_o[1:0] = 2'd3 & {2{fifo_select_oh[3]}} |
2'd2 & {2{fifo_select_oh[2]}} |
2'd1 & {2{fifo_select_oh[1]}} |
2'd0 & {2{fifo_select_oh[0]}};
assign broad_id_o[BROAD_ID_WIDTH-1:0] =
broad_id_array_i[(3+1)*BROAD_ID_WIDTH-1 : 3*BROAD_ID_WIDTH] &
{BROAD_ID_WIDTH{fifo_select_oh[3]}} |
broad_id_array_i[(2+1)*BROAD_ID_WIDTH-1 : 2*BROAD_ID_WIDTH] &
{BROAD_ID_WIDTH{fifo_select_oh[2]}} |
broad_id_array_i[(1+1)*BROAD_ID_WIDTH-1 : 1*BROAD_ID_WIDTH] &
{BROAD_ID_WIDTH{fifo_select_oh[1]}} |
broad_id_array_i[(0+1)*BROAD_ID_WIDTH-1 : 0*BROAD_ID_WIDTH] &
{BROAD_ID_WIDTH{fifo_select_oh[0]}};
//fifo_wr_array
// Write the breq into the fifo.
// When an acknowledge is sent to the mbus the breq is written to the fifo.
assign fifo_wr_array_o[3:0] = mbus_ack_array[3:0];
// mbus_ack_array
// The mbus ack is an indication for the mbus that the (broadcast) transaction
// was received and it can proceed to the next transaction (or to nop).
// The acknowledge is sent to the mbus when the breq can be stored in the fifo.
// The acknowledge can't be asserted for more then one cycle for simplification
// of the protocol and timing paths.
always @(posedge clk or posedge rst)
if (rst)
mbus_ack_array[3:0] <= 0;
else
begin
mbus_ack_array[3] <= ~mbus_ack_array[3] &
(mbus_cmd_array_i_3 == `MESI_ISC_MBUS_CMD_WR_BROAD |
mbus_cmd_array_i_3 == `MESI_ISC_MBUS_CMD_RD_BROAD )&
fifo_status_full_array_i[3] == 0;
mbus_ack_array[2] <= ~mbus_ack_array[2] &
(mbus_cmd_array_i_2 == `MESI_ISC_MBUS_CMD_WR_BROAD |
mbus_cmd_array_i_2 == `MESI_ISC_MBUS_CMD_RD_BROAD )&
fifo_status_full_array_i[2] == 0;
mbus_ack_array[1] <= ~mbus_ack_array[1] &
(mbus_cmd_array_i_1 == `MESI_ISC_MBUS_CMD_WR_BROAD |
mbus_cmd_array_i_1 == `MESI_ISC_MBUS_CMD_RD_BROAD )&
fifo_status_full_array_i[1] == 0;
mbus_ack_array[0] <= ~mbus_ack_array[0] &
(mbus_cmd_array_i_0 == `MESI_ISC_MBUS_CMD_WR_BROAD |
mbus_cmd_array_i_0 == `MESI_ISC_MBUS_CMD_RD_BROAD )&
fifo_status_full_array_i[0] == 0;
end
 
assign mbus_cmd_array_i_3[MBUS_CMD_WIDTH-1:0] =
mbus_cmd_array_i[(3+1)*MBUS_CMD_WIDTH-1 : 3*MBUS_CMD_WIDTH];
assign mbus_cmd_array_i_2[MBUS_CMD_WIDTH-1:0] =
mbus_cmd_array_i[(2+1)*MBUS_CMD_WIDTH-1 : 2*MBUS_CMD_WIDTH];
assign mbus_cmd_array_i_1[MBUS_CMD_WIDTH-1:0] =
mbus_cmd_array_i[(1+1)*MBUS_CMD_WIDTH-1 : 1*MBUS_CMD_WIDTH];
assign mbus_cmd_array_i_0[MBUS_CMD_WIDTH-1:0] =
mbus_cmd_array_i[(0+1)*MBUS_CMD_WIDTH-1 : 0*MBUS_CMD_WIDTH];
// The breq type depends on the mbus command.
// Mbus: Write broadcast - breq type: wr
// Mbus: Read broadcast - breq type: rd
// Mbus: else - breq type: nop
always @(posedge clk or posedge rst)
if (rst)
breq_type_array_o[4*BROAD_TYPE_WIDTH-1:0] <= 0;
else begin
// \ / \ /
breq_type_array_o[(3+1)*BROAD_TYPE_WIDTH-1: 3*BROAD_TYPE_WIDTH] =
// \ /
mbus_cmd_array_i_3[MBUS_CMD_WIDTH-1:0] == `MESI_ISC_MBUS_CMD_WR_BROAD ?
`MESI_ISC_BREQ_TYPE_WR:
// \ /
mbus_cmd_array_i_3[MBUS_CMD_WIDTH-1:0] == `MESI_ISC_MBUS_CMD_RD_BROAD ?
`MESI_ISC_BREQ_TYPE_RD:
`MESI_ISC_BREQ_TYPE_NOP;
// \ / \ /
breq_type_array_o[(2+1)*BROAD_TYPE_WIDTH-1: 2*BROAD_TYPE_WIDTH] =
// \ /
mbus_cmd_array_i_2[MBUS_CMD_WIDTH-1:0] == `MESI_ISC_MBUS_CMD_WR_BROAD ?
`MESI_ISC_BREQ_TYPE_WR:
// \ /
mbus_cmd_array_i_2[MBUS_CMD_WIDTH-1:0] == `MESI_ISC_MBUS_CMD_RD_BROAD ?
`MESI_ISC_BREQ_TYPE_RD:
`MESI_ISC_BREQ_TYPE_NOP;
// \ / \ /
breq_type_array_o[(1+1)*BROAD_TYPE_WIDTH-1: 1*BROAD_TYPE_WIDTH] =
// \ /
mbus_cmd_array_i_1[MBUS_CMD_WIDTH-1:0] == `MESI_ISC_MBUS_CMD_WR_BROAD ?
`MESI_ISC_BREQ_TYPE_WR:
// \ /
mbus_cmd_array_i_1[MBUS_CMD_WIDTH-1:0] == `MESI_ISC_MBUS_CMD_RD_BROAD ?
`MESI_ISC_BREQ_TYPE_RD:
`MESI_ISC_BREQ_TYPE_NOP;
// \ / \ /
breq_type_array_o[(0+1)*BROAD_TYPE_WIDTH-1: 0*BROAD_TYPE_WIDTH] =
// \ /
mbus_cmd_array_i_0[MBUS_CMD_WIDTH-1:0] == `MESI_ISC_MBUS_CMD_WR_BROAD ?
`MESI_ISC_BREQ_TYPE_WR:
// \ /
mbus_cmd_array_i_0[MBUS_CMD_WIDTH-1:0] == `MESI_ISC_MBUS_CMD_RD_BROAD ?
`MESI_ISC_BREQ_TYPE_RD:
`MESI_ISC_BREQ_TYPE_NOP;
 
end
// The CPU IDs have fixed values
assign breq_cpu_id_array_o[(3+1)*2-1 : 3*2] = 3;
assign breq_cpu_id_array_o[(2+1)*2-1 : 2*2] = 2;
assign breq_cpu_id_array_o[(1+1)*2-1 : 1*2] = 1;
assign breq_cpu_id_array_o[(0+1)*2-1 : 0*2] = 0;
 
// breq_id_array_o
// In a cycle that at least on breq is received there are 4 unique numbers -
// one for each fifo. These numbers are the breq ID. In a cycle that a certain
// fifo does not receive a breq (but there is at least one more fifos that
// receives) then its unique number in that cycle is not used.
// The values of breq_id are cyclic and every specific amount of breqs its
// value go back to 0. The possible different values of breq_id are much bigger
// then 4*(the latency of mesi_isc). In that way it is not possible that the
// same ID is used for more then one request in the same time.
//
// fifo 0 ID (for each cycle) is breq_id_base*4
// fifo 1 ID is breq_id_base*4 + 1
// fifo 1 ID is breq_id_base*4 + 2
// fifo 1 ID is breq_id_base*4 + 3
assign breq_id_array_o[(3+1)*BROAD_ID_WIDTH-1 : 3*BROAD_ID_WIDTH] =
{breq_id_base[BROAD_ID_WIDTH-3 : 0], 2'b00};
assign breq_id_array_o[(2+1)*BROAD_ID_WIDTH-1 : 2*BROAD_ID_WIDTH] =
{breq_id_base[BROAD_ID_WIDTH-3 : 0], 2'b01};
assign breq_id_array_o[(1+1)*BROAD_ID_WIDTH-1 : 1*BROAD_ID_WIDTH] =
{breq_id_base[BROAD_ID_WIDTH-3 : 0], 2'b10};
assign breq_id_array_o[(0+1)*BROAD_ID_WIDTH-1 : 0*BROAD_ID_WIDTH] =
{breq_id_base[BROAD_ID_WIDTH-3 : 0], 2'b11};
// The least significant bits of breq_id_base are always 0
always @(posedge clk or posedge rst)
if (rst)
breq_id_base[BROAD_ID_WIDTH-3 : 0] <= 0;
else if (|fifo_wr_array_o)
// breq_id_base+1 is analogous to breq_id+4
breq_id_base[BROAD_ID_WIDTH-3 : 0] <= breq_id_base[BROAD_ID_WIDTH-3 : 0] + 1;
endmodule
/trunk/src/tb/mesi_isc_tb.v
0,0 → 1,630
//////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
//// ////
//// MESI_ISC Project ////
//// ////
//// Author(s): ////
//// - Yair Amitay yair.amitay@yahoo.com ////
//// www.linkedin.com/in/yairamitay ////
//// ////
//// Description ////
//// mesi_isc_tb ////
//// ------------------- ////
//// Project test bench ////
//// - Instantiation of the top level module mesi_isc ////
//// - Generates the tests stimulus ////
//// - Simulate the CPU and caches ////
//// - Generates clock, reset and watchdog ////
//// - Generate statistic ////
//// - Generate dump file ////
//// - Check for behavior correctness ////
//// - Check for coherency correctness ////
//// ////
//// For more details see the project spec document. ////
//// To Do: ////
//// - ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`include "mesi_isc_define.v"
`include "mesi_isc_tb_define.v"
 
module mesi_isc_tb
(
// Inputs
// Outputs
);
parameter
CBUS_CMD_WIDTH = 3,
ADDR_WIDTH = 32,
DATA_WIDTH = 32,
BROAD_TYPE_WIDTH = 2,
BROAD_ID_WIDTH = 5,
BROAD_REQ_FIFO_SIZE = 4,
BROAD_REQ_FIFO_SIZE_LOG2 = 2,
MBUS_CMD_WIDTH = 3,
BREQ_FIFO_SIZE = 2,
BREQ_FIFO_SIZE_LOG2 = 1;
/// Regs and wires
//================================
// System
reg clk; // System clock
reg rst; // Active high system reset
 
// Main buses
wire [MBUS_CMD_WIDTH-1:0] mbus_cmd_array [3:0]; // Main bus3 command
wire [MBUS_CMD_WIDTH-1:0] mbus_cmd3; // Main bus2 command
wire [MBUS_CMD_WIDTH-1:0] mbus_cmd2; // Main bus2 command
wire [MBUS_CMD_WIDTH-1:0] mbus_cmd1; // Main bus1 command
wire [MBUS_CMD_WIDTH-1:0] mbus_cmd0; // Main bus0 command
// Coherence buses
wire [ADDR_WIDTH-1:0] mbus_addr_array [3:0]; // Main bus3 address
wire [ADDR_WIDTH-1:0] mbus_addr3; // Main bus3 address
wire [ADDR_WIDTH-1:0] mbus_addr2; // Main bus2 address
wire [ADDR_WIDTH-1:0] mbus_addr1; // Main bus1 address
wire [ADDR_WIDTH-1:0] mbus_addr0; // Main bus0 address
reg [DATA_WIDTH-1:0] mbus_data_rd; // Main bus data read
wire [DATA_WIDTH-1:0] mbus_data_wr_array [3:0]; // Main bus data read
wire [DATA_WIDTH-1:0] mbus_data_wr3; // Main bus data read
wire [DATA_WIDTH-1:0] mbus_data_wr2; // Main bus data read
wire [DATA_WIDTH-1:0] mbus_data_wr1; // Main bus data read
wire [DATA_WIDTH-1:0] mbus_data_wr0; // Main bus data read
 
wire [7:0] mbus_data_rd_word_array [3:0]; // Bus data read in words
// word
 
wire cbus_ack3; // Coherence bus3 acknowledge
wire cbus_ack2; // Coherence bus2 acknowledge
wire cbus_ack1; // Coherence bus1 acknowledge
wire cbus_ack0; // Coherence bus0 acknowledge
 
wire [ADDR_WIDTH-1:0] cbus_addr; // Coherence bus address. All busses have
// the same address
wire [CBUS_CMD_WIDTH-1:0] cbus_cmd3; // Coherence bus3 command
wire [CBUS_CMD_WIDTH-1:0] cbus_cmd2; // Coherence bus2 command
wire [CBUS_CMD_WIDTH-1:0] cbus_cmd1; // Coherence bus1 command
wire [CBUS_CMD_WIDTH-1:0] cbus_cmd0; // Coherence bus0 command
 
wire [3:0] mbus_ack; // Main bus3 acknowledge
reg [3:0] mbus_ack_memory;
wire [3:0] mbus_ack_mesi_isc;
reg [3:0] tb_ins_array [3:0];
wire [3:0] tb_ins3;
wire [3:0] tb_ins2;
wire [3:0] tb_ins1;
wire [3:0] tb_ins0;
reg [3:0] tb_ins_addr_array [3:0];
wire [3:0] tb_ins_addr3;
wire [3:0] tb_ins_addr2;
wire [3:0] tb_ins_addr1;
wire [3:0] tb_ins_addr0;
reg [7:0] tb_ins_nop_period [3:0];
wire [7:0] tb_ins_nop_period3;
wire [7:0] tb_ins_nop_period2;
wire [7:0] tb_ins_nop_period1;
wire [7:0] tb_ins_nop_period0;
wire [3:0] tb_ins_ack;
reg [31:0] mem [9:0]; // Main memory
wire [31:0] mem0;
wire [31:0] mem1;
wire [31:0] mem2;
wire [31:0] mem3;
wire [31:0] mem4;
wire [31:0] mem5;
wire [31:0] mem6;
wire [31:0] mem7;
wire [31:0] mem8;
wire [31:0] mem9;
reg [1:0] cpu_priority;
reg [3:0] cpu_selected;
reg mem_access;
integer stimulus_rand_numb [9:0];
integer seed;
reg [1:0] stimulus_rand_cpu_select;
reg [1:0] stimulus_op;
reg [7:0] stimulus_addr;
reg [7:0] stimulus_nop_period;
integer cur_stimulus_cpu;
// For debug in GTKwave
wire [ADDR_WIDTH+BROAD_TYPE_WIDTH+2+BROAD_ID_WIDTH:0] broad_fifo_entry0;
wire [ADDR_WIDTH+BROAD_TYPE_WIDTH+2+BROAD_ID_WIDTH:0] broad_fifo_entry1;
wire [ADDR_WIDTH+BROAD_TYPE_WIDTH+2+BROAD_ID_WIDTH:0] broad_fifo_entry2;
wire [ADDR_WIDTH+BROAD_TYPE_WIDTH+2+BROAD_ID_WIDTH:0] broad_fifo_entry3;
 
wire [5:0] cache_state_valid_array [3:0];
 
integer i, j, k, l, m, n, p;
 
reg [31:0] stat_cpu_access_nop [3:0];
reg [31:0] stat_cpu_access_rd [3:0];
reg [31:0] stat_cpu_access_wr [3:0];
 
`include "mesi_isc_tb_sanity_check.v"
// Stimulus
//================================
// The stimulus drives instruction to the CPU. There are three possible
// instructions:
// 1. NOP - Do nothing for a random cycles.
// 2. RD - Read a memory address line with a random address. If the line address
// is valid on the cache read it from there, if not bring the line according
// to the the MESI protocol.
// 3. WR - Write a memory address line with a random address. If the line address
// is valid on the cache write to it according to the MESI protocol. If it is
// not valid, bring it from the memory according to the the MESI protocol.
always @(posedge clk or posedge rst)
if (rst)
begin
tb_ins_array[3] = `MESI_ISC_TB_INS_NOP;
tb_ins_array[2] = `MESI_ISC_TB_INS_NOP;
tb_ins_array[1] = `MESI_ISC_TB_INS_NOP;
tb_ins_array[0] = `MESI_ISC_TB_INS_NOP;
tb_ins_addr_array[3] = 0;
tb_ins_addr_array[2] = 0;
tb_ins_addr_array[1] = 0;
tb_ins_addr_array[0] = 0;
tb_ins_nop_period[3] = 0;
tb_ins_nop_period[2] = 0;
tb_ins_nop_period[1] = 0;
tb_ins_nop_period[0] = 0;
end
else
begin
// Calculate the random numbers for this cycle. Use one $random command
// to perform one series of random number depends on the seed.
for (m = 0; m < 9; m = m + 1)
stimulus_rand_numb[m] = $random(seed);
 
// For the current cycle check all the CPU starting in a random CPU ID
stimulus_rand_cpu_select = $unsigned(stimulus_rand_numb[0]) % 4; // The
// random CPU ID
for (l = 0; l < 4; l = l + 1)
begin
// Start generate a request of CPU ID that equal to cur_stimulus_cpu
cur_stimulus_cpu = (stimulus_rand_cpu_select+l) % 4;
// This CPU is in NOP period
// ----------------------------
if(tb_ins_nop_period[cur_stimulus_cpu] > 0)
begin
tb_ins_array[cur_stimulus_cpu] = `MESI_ISC_TB_INS_NOP;
// Decrease the counter by 1. When the counter value is 0 the NOP period
// is finished
tb_ins_nop_period[cur_stimulus_cpu] =
tb_ins_nop_period[cur_stimulus_cpu] - 1;
end
// The CPU is return acknowledge for the last action. Change the
// instruction back to nop.
// ----------------------------
else if (tb_ins_ack[cur_stimulus_cpu])
tb_ins_array[cur_stimulus_cpu] = `MESI_ISC_TB_INS_NOP;
// Generate the next instruction for the CPU
// ----------------------------
else if(tb_ins_array[cur_stimulus_cpu] == `MESI_ISC_TB_INS_NOP)
begin
// Decide the next operation - nop (0), wr (1), or rd (2)
stimulus_op = $unsigned(stimulus_rand_numb[1+l]) % 20 ;
// Ratio: 1 - nop 1 - wr 5 - rd
if (stimulus_op > 1) stimulus_op = 2;
// Decide the next address operation 1 to 5
stimulus_addr = ($unsigned(stimulus_rand_numb[5+l]) % 5) + 1 ;
// Decide the next operation 1 to 10
stimulus_nop_period = ($unsigned(stimulus_rand_numb[9]) % 10) + 1 ;
// Next op is nop. Set the value of the counter
if (stimulus_op == 0)
tb_ins_nop_period[cur_stimulus_cpu] = stimulus_nop_period;
else
begin
tb_ins_array[cur_stimulus_cpu] = stimulus_op; // 1 for wr, 2 for rd
tb_ins_addr_array[cur_stimulus_cpu] = stimulus_addr;
end
end // if (tb_ins_array[cur_stimulus_cpu] == `MESI_ISC_TB_INS_NOP)
end // for (l = 0; l < 4; l = l + 1)
end // else: !if(rst)
 
// Statistic
//================================
always @(posedge clk or posedge rst)
if (rst)
for (n = 0; n < 4; n = n + 1)
begin
stat_cpu_access_nop[n] = 0;
stat_cpu_access_rd[n] = 0;
stat_cpu_access_wr[n] = 0;
end
else
for (p = 0; p < 4; p = p + 1)
if (tb_ins_ack[p])
begin
case (tb_ins_array[p])
`MESI_ISC_TB_INS_NOP: stat_cpu_access_nop[p] = stat_cpu_access_nop[p]+1;
`MESI_ISC_TB_INS_WR: stat_cpu_access_wr[p] = stat_cpu_access_wr[p] +1;
`MESI_ISC_TB_INS_RD: stat_cpu_access_rd[p] = stat_cpu_access_rd[p] +1;
endcase // case (tb_ins_array[p])
end
// clock and reset
//================================
always #50
clk = !clk;
 
// Reset and watchdog
//================================
initial
begin
// Reset the memory
for (j = 0; j < 10; j = j + 1)
mem[j] = 0;
clk = 1;
rst = 1;
repeat (10) @(negedge clk);
rst = 0;
repeat (20000) @(negedge clk); // Watchdog
$display ("Watchdog finish\n");
$display ("Statistic\n");
$display ("CPU 3. WR:%d RD:%d NOP:%d \n", stat_cpu_access_wr[3],
stat_cpu_access_rd[3],
stat_cpu_access_nop[3]);
$display ("CPU 2. WR:%d RD:%d NOP:%d\n", stat_cpu_access_wr[2],
stat_cpu_access_rd[2],
stat_cpu_access_nop[2]);
$display ("CPU 1. WR:%d RD:%d NOP:%d\n", stat_cpu_access_wr[1],
stat_cpu_access_rd[1],
stat_cpu_access_nop[1]);
$display ("CPU 0. WR: %d RD:%d NOP:%d\n", stat_cpu_access_wr[0],
stat_cpu_access_rd[0],
stat_cpu_access_nop[0]);
$display ("Total rd and wr accesses: %d\n", stat_cpu_access_wr[3] +
stat_cpu_access_rd[3] +
stat_cpu_access_wr[2] +
stat_cpu_access_rd[2] +
stat_cpu_access_wr[1] +
stat_cpu_access_rd[1] +
stat_cpu_access_wr[0] +
stat_cpu_access_rd[0]);
$finish;
end
 
// Dumpfile
//================================
initial
begin
$dumpfile("./dump.vcd");
$dumpvars(0,mesi_isc_tb);
end
// Memory and matrix
//================================
always @(posedge clk or posedge rst)
if (rst)
begin
cpu_priority = 0;
cpu_selected = 0;
end
else
begin
mbus_ack_memory = 0;
mem_access = 0;
for (i = 0; i < 4; i = i + 1)
if ((mbus_cmd_array[cpu_priority+i] == `MESI_ISC_MBUS_CMD_WR |
mbus_cmd_array[cpu_priority+i] == `MESI_ISC_MBUS_CMD_RD ) &
!mem_access)
begin
mem_access = 1;
cpu_selected = cpu_priority+i;
mbus_ack_memory[cpu_priority+i] = 1;
if (mbus_cmd_array[cpu_priority+i] == `MESI_ISC_MBUS_CMD_WR)
// WR
begin
sanity_check_rule1_rule2(cpu_selected,
mbus_addr_array[cpu_priority+i],
mbus_data_wr_array[cpu_priority+i]);
mem[mbus_addr_array[cpu_priority+i]] =
mbus_data_wr_array[cpu_priority+i];
end
// RD
else
mbus_data_rd = mem[mbus_addr_array[cpu_priority+i]];
end
end
assign mbus_ack[3:0] = mbus_ack_memory[3:0] | mbus_ack_mesi_isc[3:0];
 
// Assigns
//================================
// GTKwave can't see arrays. points to array so GTKwave can see these signals
assign broad_fifo_entry0 = mesi_isc.mesi_isc_broad.broad_fifo.entry[0];
assign broad_fifo_entry1 = mesi_isc.mesi_isc_broad.broad_fifo.entry[1];
assign brroad_fifo_entry2 = mesi_isc.mesi_isc_broad.broad_fifo.entry[2];
assign brroad_fifo_entry3 = mesi_isc.mesi_isc_broad.broad_fifo.entry[3];
assign mbus_cmd3 = mbus_cmd_array[3];
assign mbus_cmd2 = mbus_cmd_array[2];
assign mbus_cmd1 = mbus_cmd_array[1];
assign mbus_cmd0 = mbus_cmd_array[0];
assign mbus_addr3 = mbus_addr_array[3];
assign mbus_addr2 = mbus_addr_array[2];
assign mbus_addr1 = mbus_addr_array[1];
assign mbus_addr0 = mbus_addr_array[0];
assign mbus_data_wr3 = mbus_data_wr_array[3];
assign mbus_data_wr2 = mbus_data_wr_array[2];
assign mbus_data_wr1 = mbus_data_wr_array[1];
assign mbus_data_wr0 = mbus_data_wr_array[0];
assign tb_ins3 = tb_ins_array[3];
assign tb_ins2 = tb_ins_array[2];
assign tb_ins1 = tb_ins_array[1];
assign tb_ins0 = tb_ins_array[0];
assign tb_ins_addr3 = tb_ins_addr_array[3];
assign tb_ins_addr2 = tb_ins_addr_array[2];
assign tb_ins_addr1 = tb_ins_addr_array[1];
assign tb_ins_addr0 = tb_ins_addr_array[0];
assign tb_ins_nop_period3 = tb_ins_nop_period[3];
assign tb_ins_nop_period2 = tb_ins_nop_period[2];
assign tb_ins_nop_period1 = tb_ins_nop_period[1];
assign tb_ins_nop_period0 = tb_ins_nop_period[0];
assign mem0 = mem[0];
assign mem1 = mem[1];
assign mem2 = mem[2];
assign mem3 = mem[3];
assign mem4 = mem[4];
assign mem5 = mem[5];
assign mem6 = mem[6];
assign mem7 = mem[7];
assign mem8 = mem[8];
assign mem9 = mem[9];
assign mbus_data_rd_word_array[3] = mbus_data_rd[31:24];
assign mbus_data_rd_word_array[2] = mbus_data_rd[23:16];
assign mbus_data_rd_word_array[1] = mbus_data_rd[15:8];
assign mbus_data_rd_word_array[0] = mbus_data_rd[7:0];
// Instantiations
//================================
 
 
// mesi_isc
mesi_isc #(CBUS_CMD_WIDTH,
ADDR_WIDTH,
BROAD_TYPE_WIDTH,
BROAD_ID_WIDTH,
BROAD_REQ_FIFO_SIZE,
BROAD_REQ_FIFO_SIZE_LOG2,
MBUS_CMD_WIDTH,
BREQ_FIFO_SIZE,
BREQ_FIFO_SIZE_LOG2
)
mesi_isc
(
// Inputs
.clk (clk),
.rst (rst),
.mbus_cmd3_i (mbus_cmd_array[3]),
.mbus_cmd2_i (mbus_cmd_array[2]),
.mbus_cmd1_i (mbus_cmd_array[1]),
.mbus_cmd0_i (mbus_cmd_array[0]),
.mbus_addr3_i (mbus_addr_array[3]),
.mbus_addr2_i (mbus_addr_array[2]),
.mbus_addr1_i (mbus_addr_array[1]),
.mbus_addr0_i (mbus_addr_array[0]),
.cbus_ack3_i (cbus_ack3),
.cbus_ack2_i (cbus_ack2),
.cbus_ack1_i (cbus_ack1),
.cbus_ack0_i (cbus_ack0),
// Outputs
.cbus_addr_o (cbus_addr),
.cbus_cmd3_o (cbus_cmd3),
.cbus_cmd2_o (cbus_cmd2),
.cbus_cmd1_o (cbus_cmd1),
.cbus_cmd0_o (cbus_cmd0),
.mbus_ack3_o (mbus_ack_mesi_isc[3]),
.mbus_ack2_o (mbus_ack_mesi_isc[2]),
.mbus_ack1_o (mbus_ack_mesi_isc[1]),
.mbus_ack0_o (mbus_ack_mesi_isc[0])
);
 
// mesi_isc_tb_cpu3
mesi_isc_tb_cpu #(
CBUS_CMD_WIDTH,
ADDR_WIDTH,
DATA_WIDTH,
BROAD_TYPE_WIDTH,
BROAD_ID_WIDTH,
BROAD_REQ_FIFO_SIZE,
BROAD_REQ_FIFO_SIZE_LOG2,
MBUS_CMD_WIDTH,
BREQ_FIFO_SIZE,
BREQ_FIFO_SIZE_LOG2
)
// \ /
mesi_isc_tb_cpu3
(
// Inputs
.clk (clk),
.rst (rst),
.cbus_addr_i (cbus_addr),
// \ /
.cbus_cmd_i (cbus_cmd3),
// \ /
.mbus_data_i (mbus_data_rd),
// \ /
.mbus_ack_i (mbus_ack[3]),
// \ /
.cpu_id_i (2'd3),
// \ /
.tb_ins_i (tb_ins_array[3]),
// \ /
.tb_ins_addr_i (tb_ins_addr3),
// Outputs \ /
.mbus_cmd_o (mbus_cmd_array[3]),
// \ /
.mbus_addr_o (mbus_addr_array[3]),
// \ /
.mbus_data_o (mbus_data_wr_array[3]),
// \ /
.cbus_ack_o (cbus_ack3),
// \ /
.tb_ins_ack_o (tb_ins_ack[3])
);
 
// mesi_isc_tb_cpu2
mesi_isc_tb_cpu #(
CBUS_CMD_WIDTH,
ADDR_WIDTH,
DATA_WIDTH,
BROAD_TYPE_WIDTH,
BROAD_ID_WIDTH,
BROAD_REQ_FIFO_SIZE,
BROAD_REQ_FIFO_SIZE_LOG2,
MBUS_CMD_WIDTH,
BREQ_FIFO_SIZE,
BREQ_FIFO_SIZE_LOG2
)
// \ /
mesi_isc_tb_cpu2
(
// Inputs
.clk (clk),
.rst (rst),
.cbus_addr_i (cbus_addr),
// \ /
.cbus_cmd_i (cbus_cmd2),
// \ /
.mbus_data_i (mbus_data_rd),
// \ /
.mbus_ack_i (mbus_ack[2]),
// \ /
.cpu_id_i (2'd2),
// \ /
.tb_ins_i (tb_ins_array[2]),
// \ /
.tb_ins_addr_i (tb_ins_addr2),
// Outputs \ /
.mbus_cmd_o (mbus_cmd_array[2]),
// \ /
.mbus_addr_o (mbus_addr_array[2]),
// \ /
.mbus_data_o (mbus_data_wr_array[2]),
// \ /
.cbus_ack_o (cbus_ack2),
// \ /
.tb_ins_ack_o (tb_ins_ack[2])
);
 
// mesi_isc_tb_cpu1
mesi_isc_tb_cpu #(
CBUS_CMD_WIDTH,
ADDR_WIDTH,
DATA_WIDTH,
BROAD_TYPE_WIDTH,
BROAD_ID_WIDTH,
BROAD_REQ_FIFO_SIZE,
BROAD_REQ_FIFO_SIZE_LOG2,
MBUS_CMD_WIDTH,
BREQ_FIFO_SIZE,
BREQ_FIFO_SIZE_LOG2
)
// \ /
mesi_isc_tb_cpu1
(
// Inputs
.clk (clk),
.rst (rst),
.cbus_addr_i (cbus_addr),
// \ /
.cbus_cmd_i (cbus_cmd1),
// \ /
.mbus_data_i (mbus_data_rd),
// \ /
.mbus_ack_i (mbus_ack[1]),
// \ /
.cpu_id_i (2'd1),
// \ /
.tb_ins_i (tb_ins_array[1]),
// \ /
.tb_ins_addr_i (tb_ins_addr1),
// Outputs \ /
.mbus_cmd_o (mbus_cmd_array[1]),
// \ /
.mbus_addr_o (mbus_addr_array[1]),
// \ /
.mbus_data_o (mbus_data_wr_array[1]),
// \ /
.cbus_ack_o (cbus_ack1),
// \ /
.tb_ins_ack_o (tb_ins_ack[1])
);
 
// mesi_isc_tb_cpu0
mesi_isc_tb_cpu #(
CBUS_CMD_WIDTH,
ADDR_WIDTH,
DATA_WIDTH,
BROAD_TYPE_WIDTH,
BROAD_ID_WIDTH,
BROAD_REQ_FIFO_SIZE,
BROAD_REQ_FIFO_SIZE_LOG2,
MBUS_CMD_WIDTH,
BREQ_FIFO_SIZE,
BREQ_FIFO_SIZE_LOG2
)
// \ /
mesi_isc_tb_cpu0
(
// Inputs
.clk (clk),
.rst (rst),
.cbus_addr_i (cbus_addr),
// \ /
.cbus_cmd_i (cbus_cmd0),
// \ /
.mbus_data_i (mbus_data_rd),
// \ /
.mbus_ack_i (mbus_ack[0]),
// \ /
.cpu_id_i (2'd0),
// \ /
.tb_ins_i (tb_ins_array[0]),
// \ /
.tb_ins_addr_i (tb_ins_addr0),
// Outputs \ /
.mbus_cmd_o (mbus_cmd_array[0]),
// \ /
.mbus_addr_o (mbus_addr_array[0]),
// \ /
.mbus_data_o (mbus_data_wr_array[0]),
// \ /
.cbus_ack_o (cbus_ack0),
// \ /
.tb_ins_ack_o (tb_ins_ack[0])
);
 
endmodule
/trunk/src/tb/mesi_isc_tb_sanity_check.v
0,0 → 1,196
//////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
//// ////
//// MESI_ISC Project ////
//// ////
//// Author(s): ////
//// - Yair Amitay yair.amitay@yahoo.com ////
//// www.linkedin.com/in/yairamitay ////
//// ////
//// Description ////
//// mesi_isc_tb ////
//// ------------------- ////
//// Project test bench. ////
//// Check coherency rules 1,2, and 3. ////
//// Check fifos overflow and underflow. ////
//// ////
//// To Do: ////
//// - ////
//// ////
//////////////////////////////////////////////////////////////////////
 
// Sanity checks
//================================
 
// Sanity Check 1 - coherency rules
//================================
//
// Rule | time | CPU ID | Memory | Address | Data | Condition |
// | | | Event | | | |
// -----|-------|---------|--------|---------|------|-------------|
// | x | 1 | WR | A1 | D1 |
// 1 |-------|---------|--------|---------|------|
// | x+1 | 1 | RD | A1 | D1 |
// -----|-------|---------|--------|---------|------|
// | x | 1 | WR | A1 | D1 |
// 2 |-------|---------|--------|---------|------|
// | x+1 | 2 | RD | A1 | D1 |
// -----|-------|---------|--------|---------|------|
// | x | 1 | WR | A1 | D1 |
// |-------|---------|--------|---------|------|
// | x+1 | 2 | WD | A1 | D2 |
// 3 |-------|---------|--------|---------|------|
// | y | 3 | RD | A1 | D2 |
// |-------|---------|--------|---------|------|--------------|
// | y+1 | 3 | RD | A1 | D1 | Not allowed |
// -----|-------|---------|--------|---------|------|--------------|
//
// For each read from the memory, check that the read data contains the most
// update written data. The check is done separately for each CPU written data.
// This check covers the three rules for coherency system.
// task sanity_check_rule1
task sanity_check_rule1_rule2;
input [3:0] cpu_id;
input [ADDR_WIDTH-1:0] mbus_addr;
input [DATA_WIDTH-1:0] mbus_wr_data;
reg [DATA_WIDTH-1:0] cur_mem_data;
 
begin
`ifdef messages
$display("Message: check err 7. time:%d", $time);
`endif
cur_mem_data = mem[mbus_addr];
if (cur_mem_data[(3+1)*8-1 : 3*8] > mbus_wr_data[(3+1)*8-1 : 3*8] |
cur_mem_data[(2+1)*8-1 : 2*8] > mbus_wr_data[(2+1)*8-1 : 2*8] |
cur_mem_data[(1+1)*8-1 : 1*8] > mbus_wr_data[(1+1)*8-1 : 1*8] |
cur_mem_data[(0+1)*8-1 : 0*8] > mbus_wr_data[(0+1)*8-1 : 0*8])
begin
$display("ERROR 7. The current memory data is bigger then the written data\n");
$display(" CPU: %h, Cur data: %h, Written data: %h, Address: %h, time:%d\n",
cpu_id,
cur_mem_data,
mbus_wr_data,
mbus_addr,
$time);
@(negedge clk) $finish();
end
end
endtask
 
// Sanity Check 2- cache states
//================================
// Checks that, at any time, there are not 2 cache lines or more, that contains
// the same memory address, with stats M or state E.
always @(posedge clk or posedge rst)
for (k=0; k < 4; k = k + 1)
if (mbus_ack[k]) sanity_check_cache_status(mbus_addr_array[k]);
 
// task sanity_check_cache_status;
task sanity_check_cache_status;
input [ADDR_WIDTH-1:0] mbus_addr;
reg [1:0] num_of_lines_in_m_e_state;
begin
`ifdef messages
$display("Message: check err 6. time:%d", $time);
`endif
num_of_lines_in_m_e_state = 0;
// \ /
if(mesi_isc_tb_cpu3.cache_state[mbus_addr] == `MESI_ISC_TB_CPU_MESI_E |
// \ /
mesi_isc_tb_cpu3.cache_state[mbus_addr] == `MESI_ISC_TB_CPU_MESI_M)
num_of_lines_in_m_e_state = num_of_lines_in_m_e_state + 1;
 
if(mesi_isc_tb_cpu2.cache_state[mbus_addr] == `MESI_ISC_TB_CPU_MESI_E |
// \ /
mesi_isc_tb_cpu2.cache_state[mbus_addr] == `MESI_ISC_TB_CPU_MESI_M)
num_of_lines_in_m_e_state = num_of_lines_in_m_e_state + 1;
 
if(mesi_isc_tb_cpu1.cache_state[mbus_addr] == `MESI_ISC_TB_CPU_MESI_E |
// \ /
mesi_isc_tb_cpu1.cache_state[mbus_addr] == `MESI_ISC_TB_CPU_MESI_M)
num_of_lines_in_m_e_state = num_of_lines_in_m_e_state + 1;
 
if(mesi_isc_tb_cpu0.cache_state[mbus_addr] == `MESI_ISC_TB_CPU_MESI_E |
// \ /
mesi_isc_tb_cpu0.cache_state[mbus_addr] == `MESI_ISC_TB_CPU_MESI_M)
num_of_lines_in_m_e_state = num_of_lines_in_m_e_state + 1;
 
if (num_of_lines_in_m_e_state > 1)
begin
$display("Error 6. %d of cache lines are in M or E state. time:%d\n",
num_of_lines_in_m_e_state,
$time);
@(negedge clk) $finish;
end
end
endtask
 
 
// Error state
//================================
`ifdef mesi_isc_debug
 
always @(mesi_isc.mesi_isc_breq_fifos.fifo_3.dbg_fifo_overflow or
mesi_isc.mesi_isc_breq_fifos.fifo_3.dbg_fifo_underflow or
mesi_isc.mesi_isc_breq_fifos.fifo_2.dbg_fifo_overflow or
mesi_isc.mesi_isc_breq_fifos.fifo_2.dbg_fifo_underflow or
mesi_isc.mesi_isc_breq_fifos.fifo_1.dbg_fifo_overflow or
mesi_isc.mesi_isc_breq_fifos.fifo_1.dbg_fifo_underflow or
mesi_isc.mesi_isc_breq_fifos.fifo_0.dbg_fifo_overflow or
mesi_isc.mesi_isc_breq_fifos.fifo_0.dbg_fifo_underflow or
mesi_isc.mesi_isc_broad.broad_fifo.dbg_fifo_overflow or
mesi_isc.mesi_isc_broad.broad_fifo.dbg_fifo_underflow)
if (mesi_isc.mesi_isc_breq_fifos.fifo_3.dbg_fifo_overflow |
mesi_isc.mesi_isc_breq_fifos.fifo_3.dbg_fifo_underflow |
mesi_isc.mesi_isc_breq_fifos.fifo_2.dbg_fifo_overflow |
mesi_isc.mesi_isc_breq_fifos.fifo_2.dbg_fifo_underflow |
mesi_isc.mesi_isc_breq_fifos.fifo_1.dbg_fifo_overflow |
mesi_isc.mesi_isc_breq_fifos.fifo_1.dbg_fifo_underflow |
mesi_isc.mesi_isc_breq_fifos.fifo_0.dbg_fifo_overflow |
mesi_isc.mesi_isc_breq_fifos.fifo_0.dbg_fifo_underflow |
mesi_isc.mesi_isc_broad.broad_fifo.dbg_fifo_overflow |
mesi_isc.mesi_isc_broad.broad_fifo.dbg_fifo_underflow)
begin
$display("ERROR 8. Fifo overflow or underflow\n");
$display("mesi_isc.mesi_isc_breq_fifos.fifo_3.dbg_fifo_overflow = %h, mesi_isc.mesi_isc_breq_fifos.fifo_3.dbg_fifo_underflow = %h, mesi_isc.mesi_isc_breq_fifos.fifo_2.dbg_fifo_overflow = %h, mesi_isc.mesi_isc_breq_fifos.fifo_2.dbg_fifo_underflow = %h, mesi_isc.mesi_isc_breq_fifos.fifo_1.dbg_fifo_overflow = %h, mesi_isc.mesi_isc_breq_fifos.fifo_1.dbg_fifo_underflow = %h, mesi_isc.mesi_isc_breq_fifos.fifo_0.dbg_fifo_overflow = %h, mesi_isc.mesi_isc_breq_fifos.fifo_0.dbg_fifo_underflow = %h, mesi_isc.mesi_isc_broad.broad_fifo.dbg_fifo_overflow = %h, mesi_isc.mesi_isc_broad.broad_fifo.dbg_fifo_underflow = %h", mesi_isc.mesi_isc_breq_fifos.fifo_3.dbg_fifo_overflow,
mesi_isc.mesi_isc_breq_fifos.fifo_3.dbg_fifo_underflow,
mesi_isc.mesi_isc_breq_fifos.fifo_2.dbg_fifo_overflow,
mesi_isc.mesi_isc_breq_fifos.fifo_2.dbg_fifo_underflow,
mesi_isc.mesi_isc_breq_fifos.fifo_1.dbg_fifo_overflow,
mesi_isc.mesi_isc_breq_fifos.fifo_1.dbg_fifo_underflow,
mesi_isc.mesi_isc_breq_fifos.fifo_0.dbg_fifo_overflow,
mesi_isc.mesi_isc_breq_fifos.fifo_0.dbg_fifo_underflow,
mesi_isc.mesi_isc_broad.broad_fifo.dbg_fifo_overflow,
mesi_isc.mesi_isc_broad.broad_fifo.dbg_fifo_underflow);
$finish();
end
`endif
/trunk/src/tb/README.txt
0,0 → 1,7
MESI_ISC Project
=================
 
Directoy: tb
=================
 
Contains all the project`s test bench files.
/trunk/src/tb/mesi_isc_tb_cpu.v
0,0 → 1,703
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
//// ////
//// MESI_ISC Project ////
//// ////
//// Author(s): ////
//// - Yair Amitay yair.amitay@yahoo.com ////
//// www.linkedin.com/in/yairamitay ////
//// ////
//// Description ////
//// mesi_isc_tb_cpu ////
//// ------------------- ////
//// Illustrate A coherence CPU with cache and 10 memory lines ////
//// ////
/// To Do: ////
//// - ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`include "mesi_isc_define.v"
`include "mesi_isc_tb_define.v"
 
module mesi_isc_tb_cpu
(
// Inputs
clk,
rst,
cbus_addr_i,
cbus_cmd_i,
mbus_data_i,
mbus_ack_i,
cpu_id_i,
tb_ins_i,
tb_ins_addr_i,
// Outputs
mbus_cmd_o,
mbus_addr_o,
mbus_data_o,
cbus_ack_o,
tb_ins_ack_o
);
parameter
CBUS_CMD_WIDTH = 3,
ADDR_WIDTH = 32,
DATA_WIDTH = 32,
BROAD_TYPE_WIDTH = 2,
BROAD_ID_WIDTH = 5,
BROAD_REQ_FIFO_SIZE = 4,
BROAD_REQ_FIFO_SIZE_LOG2 = 2,
MBUS_CMD_WIDTH = 3,
BREQ_FIFO_SIZE = 2,
BREQ_FIFO_SIZE_LOG2 = 1;
// Inputs
//================================
// System
input clk; // System clock
input rst; // Active high system reset
input [ADDR_WIDTH-1:0] cbus_addr_i; // Coherence bus address. All busses have
// the same address
input [CBUS_CMD_WIDTH-1:0] cbus_cmd_i; // Coherence bus3 command
input [DATA_WIDTH-1:0] mbus_data_i; // Main bus read data
input mbus_ack_i; // Main bus3 acknowledge
// tb
input [1:0] cpu_id_i;
input [3:0] tb_ins_i; // Instruction for CPU to perform an
// action
input [3:0] tb_ins_addr_i; // Instruction address
// Outputs
//================================
// Main buses
output [MBUS_CMD_WIDTH-1:0] mbus_cmd_o; // Main bus3 command
output [ADDR_WIDTH-1:0] mbus_addr_o; // Coherence bus3 address
output [DATA_WIDTH-1:0] mbus_data_o; // Main bus write data
// Coherence buses
output cbus_ack_o; // Coherence bus3 acknowledge
// tb
output tb_ins_ack_o; // Acknowledge for the
// CPU instruction
// Regs & wires
//================================
reg tb_ins_ack_o;
reg [31:0] cache [9:0]; // CPU cache
wire [31:0] cache0;
wire [31:0] cache1;
wire [31:0] cache2;
wire [31:0] cache3;
wire [31:0] cache4;
wire [31:0] cache5;
wire [31:0] cache6;
wire [31:0] cache7;
wire [31:0] cache8;
wire [31:0] cache9;
reg [3:0] cache_state [9:0]; // CPU cache MESI state
wire [3:0] cache_state0;
wire [3:0] cache_state1;
wire [3:0] cache_state2;
wire [3:0] cache_state3;
wire [3:0] cache_state4;
wire [3:0] cache_state5;
wire [3:0] cache_state6;
wire [3:0] cache_state7;
wire [3:0] cache_state8;
wire [3:0] cache_state9;
reg [MBUS_CMD_WIDTH-1:0] mbus_cmd_o; // Main bus3 command
reg [ADDR_WIDTH-1:0] mbus_addr_o; // Coherence bus3 address
reg [2:0] m_state;
reg [7:0] wr_data [5:0];
reg wr_proc_wait_for_en;
reg [ADDR_WIDTH-1:0] wr_proc_addr;
reg rd_proc_wait_for_en;
reg [ADDR_WIDTH-1:0] rd_proc_addr;
reg cbus_ack_o; // Coherence bus3 acknowledge
reg m_state_c_state_priority;
reg [3:0] c_state;
reg [ADDR_WIDTH-1:0] m_addr;
reg [ADDR_WIDTH-1:0] c_addr;
reg [DATA_WIDTH-1:0] mbus_data_o; // Main bus write data
integer m_state_send_wr_br_counter,m_state_send_rd_br_counter;
integer i,j,k; // Loop index
 
// GTKwave can't see arrays. points to array so GTKwave can see these signals
assign cache0 = cache[0];
assign cache1 = cache[1];
assign cache2 = cache[2];
assign cache3 = cache[3];
assign cache4 = cache[4];
assign cache5 = cache[5];
assign cache6 = cache[6];
assign cache7 = cache[7];
assign cache8 = cache[8];
assign cache9 = cache[9];
assign cache_state0 = cache_state[0];
assign cache_state1 = cache_state[1];
assign cache_state2 = cache_state[2];
assign cache_state3 = cache_state[3];
assign cache_state4 = cache_state[4];
assign cache_state5 = cache_state[5];
assign cache_state6 = cache_state[6];
assign cache_state7 = cache_state[7];
assign cache_state8 = cache_state[8];
assign cache_state9 = cache_state[9];
 
 
// initial
//================================
initial
for (i = 0; i < 10; i = i + 1)
begin
cache_state[i] = `MESI_ISC_TB_CPU_MESI_I;
end
// m_state - Main bus state machine and
// c_state - Coherence bus state machine and
//================================
//
// m_state
// ---------------------------------------------------
// | |
// -----> IDLE ----- m_state_c_state_priority == 0 ---
// |
// --------- m_state_c_state_priority == 1 ---
// |
// Other states <------------------------------
//
// c_state
// ---------------------------------------------------
// | |
// -----> IDLE ----- m_state_c_state_priority == 1 ---
// |
// --------- m_state_c_state_priority == 0 ---
// |
// Other states <------------------------------
 
// m_state_c_state_priority
//================================
// When set only m_state can start a process (move from IDLE state).
// When clear only c_state can start a process (move from IDLE state).
always @(posedge clk or posedge rst)
if (rst) m_state_c_state_priority <= 0;
else m_state_c_state_priority <= ~m_state_c_state_priority;
// m_state
// Main bus state machine
//================================
//
// -----------------------------------
// | ------- | |
// | | | | |
// |----> IDLE --------> WR_CACHE |
// | |
// |-----------> RD_CACHE ---|
// | |
// | ------- |
// | | | |
// |-----------> SEND_WR_BR -|
// | |
// | ------- |
// | | | |
// ------------> SEND_RD_BR -|
 
always @(posedge clk or posedge rst)
if (rst)
begin
m_state <= `MESI_ISC_TB_CPU_M_STATE_IDLE;
tb_ins_ack_o <= 0;
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_NOP;
wr_proc_wait_for_en <= 0;
wr_proc_addr <= 0;
rd_proc_wait_for_en <= 0;
rd_proc_addr <= 0;
m_state_send_wr_br_counter <= 0;
m_state_send_rd_br_counter <= 0;
for (k = 0; k < 6; k = k + 1)
wr_data[k] <= 1;
 
end
else case (m_state)
`MESI_ISC_TB_CPU_M_STATE_IDLE:
//----------------------------------
begin
m_state_send_wr_br_counter <= 0; // Clear the counter
m_state_send_rd_br_counter <= 0; // Clear the counter
tb_ins_ack_o <= 0; // Send ack when an action is finished
// CBUS and MBUS can't be active in the same time. When CBUS is
// active - wait.
// If priority is not of m_state - stay on IDLE
if (c_state !=`MESI_ISC_TB_CPU_M_STATE_IDLE |
!m_state_c_state_priority)
begin
m_state <= `MESI_ISC_TB_CPU_M_STATE_IDLE;
end
// Start the action when instruction is received and when there is not a
// pending action - wait for en read or en wr
else if ((tb_ins_i == `MESI_ISC_TB_INS_WR |
tb_ins_i == `MESI_ISC_TB_INS_RD) &
~wr_proc_wait_for_en &
~rd_proc_wait_for_en)
begin
m_addr <= tb_ins_addr_i; // Store the address of the
// instruction
mbus_addr_o <= tb_ins_addr_i; // Send the ins address for a
// case of an actual action.
// Depends of the state of the cache line of the desired address,
// define the action to perform
case (cache_state[tb_ins_addr_i])
// The cache state is Modify. Write to cache or read from cache.
`MESI_ISC_TB_CPU_MESI_M:
if (tb_ins_i == `MESI_ISC_TB_INS_WR)
begin
m_state <= `MESI_ISC_TB_CPU_M_STATE_WR_CACHE;
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_NOP;
end
else
begin
m_state <= `MESI_ISC_TB_CPU_M_STATE_RD_CACHE;
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_NOP;
end
// The memory state is Exclusive. Write to cache or read from cache.
`MESI_ISC_TB_CPU_MESI_E:
if (tb_ins_i == `MESI_ISC_TB_INS_WR)
begin
m_state <= `MESI_ISC_TB_CPU_M_STATE_WR_CACHE;
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_NOP;
end
else
begin
m_state <= `MESI_ISC_TB_CPU_M_STATE_RD_CACHE;
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_NOP;
end
// The memory state is Shared.
`MESI_ISC_TB_CPU_MESI_S:
if (tb_ins_i == `MESI_ISC_TB_INS_WR)
begin // Send a wr broadcast and wait for wr enable.
wr_proc_wait_for_en <= 1;
wr_proc_addr <= tb_ins_addr_i;
m_state <= `MESI_ISC_TB_CPU_M_STATE_SEND_WR_BR;
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_WR_BROAD;
end
else // Read from cache.
begin
m_state <= `MESI_ISC_TB_CPU_M_STATE_RD_CACHE;
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_NOP;
end
// The memory state is Invalid.
`MESI_ISC_TB_CPU_MESI_I:
if (tb_ins_i == `MESI_ISC_TB_INS_WR)
begin // Send a wr broadcast and wait foo wr enable.
wr_proc_wait_for_en <= 1;
wr_proc_addr <= tb_ins_addr_i;
m_state <= `MESI_ISC_TB_CPU_M_STATE_SEND_WR_BR;
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_WR_BROAD;
end
else
begin // Send a rd broadcast and wait foe rd enable.
rd_proc_wait_for_en <= 1;
rd_proc_addr <= tb_ins_addr_i;
m_state <= `MESI_ISC_TB_CPU_M_STATE_SEND_RD_BR;
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_RD_BROAD;
end
endcase
end // if (tb_ins_i == `MESI_ISC_TB_INS_WR)
end // case: `MESI_ISC_TB_CPU_M_STATE_IDLE
// Write to the cache
`MESI_ISC_TB_CPU_M_STATE_WR_CACHE:
//----------------------------------
begin
// State was M or E. After writing it is M
cache_state[m_addr] <= `MESI_ISC_TB_CPU_MESI_M;
// A write data to a line contains the incremental data to the
// related word of the data, depends on the cpu_id_i (word 0 for CPU
// 0, etc.)
case (cpu_id_i)
0: cache[m_addr][ 7 :0] <= wr_data[m_addr];
1: cache[m_addr][15: 8] <= wr_data[m_addr];
2: cache[m_addr][23:16] <= wr_data[m_addr];
3: cache[m_addr][31:24] <= wr_data[m_addr];
endcase // case (cpu_id_i)
wr_data[m_addr] <= wr_data[m_addr] + 1; // Increment the
// write data
// After the write, send acknowledge to main tb and go to the idle
// state
m_state <= `MESI_ISC_TB_CPU_M_STATE_IDLE;
tb_ins_ack_o <= 1;
end // case: `MESI_ISC_TB_CPU_M_STATE_WR_CACHE
// A cache read from a valid line is a symbolic action in this TB
`MESI_ISC_TB_CPU_M_STATE_RD_CACHE:
//----------------------------------
begin
m_state <= `MESI_ISC_TB_CPU_M_STATE_IDLE;
tb_ins_ack_o <= 1;
end
`MESI_ISC_TB_CPU_M_STATE_SEND_WR_BR:
//----------------------------------
// Send the wr broadcast. After receiving acknowledge, send acknowledge to
// main tb and go to the idle
begin
mbus_addr_o <= m_addr;
// Counts the number of cycle which m_state in this state
m_state_send_wr_br_counter = m_state_send_wr_br_counter + 1;
if (mbus_ack_i)
begin
m_state <= `MESI_ISC_TB_CPU_M_STATE_IDLE;
tb_ins_ack_o <= 1;
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_NOP;
 
end
// To prevent a dead lock, after 31 cycles without an acknowledge, go to
// the IDLE state and try again. It enables to the c_state to response to
// broadcast requests in this time.
else if (m_state_send_wr_br_counter > 31)
begin
m_state <= `MESI_ISC_TB_CPU_M_STATE_IDLE;
tb_ins_ack_o <= 0;
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_NOP;
 
end
else // Wait for ack
begin
m_state <= `MESI_ISC_TB_CPU_M_STATE_SEND_WR_BR;
end
end
`MESI_ISC_TB_CPU_M_STATE_SEND_RD_BR:
//----------------------------------
// Send the rd broadcast. After receiving acknowledge, send acknowledge to
// main tb and go to the idle
begin
mbus_addr_o <= m_addr;
// Counts the number of cycle which m_state in this state
m_state_send_rd_br_counter = m_state_send_rd_br_counter + 1;
if (mbus_ack_i)
begin
m_state <= `MESI_ISC_TB_CPU_M_STATE_IDLE;
tb_ins_ack_o <= 1;
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_NOP;
end
// To prevent a dead lock, after 31 cycles without an acknowledge, go to
// the IDLE state and try again. It enables to the c_state to response to
// broadcast requests in this time.
else if (m_state_send_rd_br_counter > 31)
begin
m_state <= `MESI_ISC_TB_CPU_M_STATE_IDLE;
tb_ins_ack_o <= 0;
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_NOP;
 
end
else // Wait for ack
m_state <= `MESI_ISC_TB_CPU_M_STATE_SEND_RD_BR;
end
endcase // case state
 
 
// c_state
// Coherence bus state machine
//================================
//
// -----------------------------------------
// | ------- |
// | | | |
// -----> IDLE --------> WR_SNOOP ---------|
// | | |
// | ---- |
// | | |
// | -> EVICT_INVALIDATE -|
// | |
// |-----------> RD_SNOOP ---------|
// | | |
// | ---- |
// | | |
// | -> EVICT ------------|
// | |
// |-----------> RD_LINE_WR--------|
// | | |
// | ---- |
// | | |
// | -> WR_CACHE --------|
// | |
// |-----------> RD_LINE_RD--------|
//
always @(posedge clk or posedge rst)
if (rst)
begin
c_state <= `MESI_ISC_TB_CPU_C_STATE_IDLE;
cbus_ack_o <= 0;
end
else case (c_state)
 
`MESI_ISC_TB_CPU_C_STATE_IDLE:
//----------------------------------
begin
c_addr <= cbus_addr_i; // Store the address of cbus
// 1. CBUS and MBUS can't be active in the same time. When MBUS is
// active - wait.
// 2. If priority is not of c_state - stay on IDLE
// 3. If cbus_ack_o is asserted the last action is nor finished yet - wait
// for its finish
if (m_state !=`MESI_ISC_TB_CPU_M_STATE_IDLE | // 1
m_state_c_state_priority | // 2
cbus_ack_o) // 3
begin
c_state <= `MESI_ISC_TB_CPU_C_STATE_IDLE;
cbus_ack_o <= 0;
end
// Start the action when instruction is received.
else
begin
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_NOP;
case (cbus_cmd_i)
`MESI_ISC_CBUS_CMD_NOP:
begin
c_state <= `MESI_ISC_TB_CPU_C_STATE_IDLE;
cbus_ack_o <= 0;
end
`MESI_ISC_CBUS_CMD_WR_SNOOP:
begin
c_state <= `MESI_ISC_TB_CPU_C_STATE_WR_SNOOP;
cbus_ack_o <= 0;
end
`MESI_ISC_CBUS_CMD_RD_SNOOP:
begin
c_state <= `MESI_ISC_TB_CPU_C_STATE_RD_SNOOP;
cbus_ack_o <= 0;
end
`MESI_ISC_CBUS_CMD_EN_WR:
begin
c_state <= `MESI_ISC_TB_CPU_C_STATE_RD_LINE_WR;
cbus_ack_o <= 0;
end
`MESI_ISC_CBUS_CMD_EN_RD:
begin
c_state <= `MESI_ISC_TB_CPU_C_STATE_RD_LINE_RD;
cbus_ack_o <= 0;
end
default: $display ("Error 1. Wrong value - CPU:%d, cbus_cmd_i = %h,time=%d\n",
cpu_id_i,
cbus_cmd_i,
$time);
endcase // case (cbus_cmd_i)
end // else: !if(m_state !=`MESI_ISC_TB_CPU_M_STATE_IDLE |...
end // case: `MESI_ISC_TB_CPU_C_STATE_IDLE
 
`MESI_ISC_TB_CPU_C_STATE_WR_SNOOP:
//----------------------------------
if (cache_state[c_addr] == `MESI_ISC_TB_CPU_MESI_M)
c_state <= `MESI_ISC_TB_CPU_C_STATE_EVICT_INVALIDATE;
else
begin // Invalidate the line, send ack and finish the current process
cbus_ack_o <= 1;
c_state <= `MESI_ISC_TB_CPU_C_STATE_IDLE;
cache_state[c_addr] <= `MESI_ISC_TB_CPU_MESI_I;
cache[c_addr] <= 0;
end
 
`MESI_ISC_TB_CPU_C_STATE_RD_SNOOP:
//----------------------------------
if (cache_state[c_addr] == `MESI_ISC_TB_CPU_MESI_M)
c_state <= `MESI_ISC_TB_CPU_C_STATE_EVICT_INVALIDATE;
else if (cache_state[c_addr] == `MESI_ISC_TB_CPU_MESI_E)
begin // Change state from E to S
cbus_ack_o <= 1;
c_state <= `MESI_ISC_TB_CPU_C_STATE_IDLE;
cache_state[c_addr] <= `MESI_ISC_TB_CPU_MESI_S;
end
else
begin // Do nothing send ack and finish the current process
cbus_ack_o <= 1;
c_state <= `MESI_ISC_TB_CPU_C_STATE_IDLE;
end
 
`MESI_ISC_TB_CPU_C_STATE_EVICT_INVALIDATE:
//----------------------------------
begin
// Debug start ---
`ifdef messages // ifdef
$display("Message: check err 2. time:%d", $time);
`endif // endif
// Only a line in a M state can be EVICT_INVALIDATE
if (cache_state[c_addr] != `MESI_ISC_TB_CPU_MESI_M)
begin
$display("Error 2. cache_state[c_addr] is not M.\n",
" CPU:%d,c_addr=%h,cache_state[c_addr]=%h,time:%d",
cpu_id_i,
c_addr,
cache_state[c_addr],
$time);
@(negedge clk) $finish();
end
// Debug end ---
else
// Write line to memory. After receiving acknowledge, invalidate the line,
// send acknowledge to main cbus and go to idle
begin
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_WR;
mbus_addr_o <= c_addr;
mbus_data_o <= cache[c_addr];
if (mbus_ack_i)
begin
cache_state[c_addr] <= `MESI_ISC_TB_CPU_MESI_I;
c_state <= `MESI_ISC_TB_CPU_C_STATE_IDLE;
cbus_ack_o <= 1;
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_NOP;
end
end
end // case: `MESI_ISC_TB_CPU_C_STATE_EVICT_INVALIDATE
 
`MESI_ISC_TB_CPU_C_STATE_EVICT:
//----------------------------------
begin
`ifdef messages
$display("Message: check err 3. time:%d",$time);
`endif
// Only a line in a S or E state can be EVICT_INVALIDATE
if (~(cache_state[c_addr] == `MESI_ISC_TB_CPU_MESI_S |
cache_state[c_addr] == `MESI_ISC_TB_CPU_MESI_E))
begin
$display("Error 3. cache_state[c_addr] is not S or E.\n");
$display(" CPU:%d,c_addr=%h,cache_state[c_addr]=%h,time=%d",
cpu_id_i,
c_addr,
cache_state[c_addr],
$time);
@(negedge clk) $finish();
end
else
// Write line to memory. After receiving acknowledge, change state to S,
// send acknowledge to main cbus and go to idle
begin
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_WR;
mbus_addr_o <= c_addr;
mbus_data_o <= cache[c_addr];
if (mbus_ack_i)
begin
cache_state[c_addr] <= `MESI_ISC_TB_CPU_MESI_S;
c_state <= `MESI_ISC_TB_CPU_C_STATE_IDLE;
cbus_ack_o <= 1;
end
end // else: !if(~(cache_state[c_addr] == `MESI_ISC_TB_CPU_MESI_S |...
end // case: `MESI_ISC_TB_CPU_C_STATE_EVICT
 
`MESI_ISC_TB_CPU_C_STATE_RD_LINE_WR:
//----------------------------------
// Read a line from memory and then go to WR_CACHE
// and write to the cache.
begin
`ifdef messages
$display("Message: check er 4.time:%d",$time);
`endif
if (wr_proc_wait_for_en != 1 |
wr_proc_addr != c_addr)
begin
$display("Error 4. Write to cache without early broadcast.\n",
" CPU:%d,wr_proc_wait_for_en=%h,wr_proc_addr=%h,c_addr=%h, time:%d",
cpu_id_i,
wr_proc_wait_for_en,
wr_proc_addr,
c_addr,
$time);
@(negedge clk) $finish();
end
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_RD;
mbus_addr_o <= c_addr;
if (mbus_ack_i)
begin
// A write data to a line contains the incremental data to the
// related word of the data, depends on the cpu_id_i (word 0 for CPU
// 0, etc.)
cache[m_addr] <= mbus_data_i;
cache_state[m_addr] <= `MESI_ISC_TB_CPU_MESI_S;
c_state <= `MESI_ISC_TB_CPU_C_STATE_WR_CACHE;
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_NOP;
end
end
 
`MESI_ISC_TB_CPU_C_STATE_RD_LINE_RD:
//----------------------------------
// Read a line from memory and then go back to IDLE.
begin
`ifdef messages
$display("Message: check err 5. time:%d",$time);
`endif
// EN_RD means that the line is not valid in the cache
if (rd_proc_wait_for_en != 1 |
rd_proc_addr != c_addr)
begin
$display("Error 5. Read to cache without early broadcast.\n",
" CPU:%d,rd_proc_wait_for_en=%h,rd_proc_addr=%h,c_addr=%h,time:%d\n",
cpu_id_i,
rd_proc_wait_for_en,
rd_proc_addr,
c_addr,
$time);
@(negedge clk) $finish();
end
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_RD;
mbus_addr_o <= c_addr;
if (mbus_ack_i)
begin
// A write data to a line contains the incremental data to the
// related word of the data, depends on the cpu_id_i (word 0 for CPU
// 0, etc.)
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_NOP;
cache[m_addr] <= mbus_data_i;
cache_state[m_addr] <= `MESI_ISC_TB_CPU_MESI_S;
c_state <= `MESI_ISC_TB_CPU_C_STATE_IDLE;
cbus_ack_o <= 1;
rd_proc_wait_for_en <= 0;
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_NOP;
end // if (mbus_ack_i)
end // case: `MESI_ISC_TB_CPU_C_STATE_RD_LINE_RD
 
`MESI_ISC_TB_CPU_C_STATE_WR_CACHE:
//----------------------------------
begin
// A write data to a line contains the incremental data to the
// related word of the data, depends on the cpu_id_i (word 0 for CPU
// 0, etc.)
case (cpu_id_i)
0: cache[m_addr][ 7 :0] <= wr_data[m_addr];
1: cache[m_addr][15: 8] <= wr_data[m_addr];
2: cache[m_addr][23:16] <= wr_data[m_addr];
3: cache[m_addr][31:24] <= wr_data[m_addr];
endcase // case (cpu_id_i)
wr_data[m_addr] <= wr_data[m_addr] + 1; // Increment the wr data
c_state <= `MESI_ISC_TB_CPU_C_STATE_IDLE;
mbus_cmd_o <= `MESI_ISC_MBUS_CMD_NOP;
cache_state[m_addr] <= `MESI_ISC_TB_CPU_MESI_M;
cbus_ack_o <= 1;
wr_proc_wait_for_en <= 0;
end
endcase // case (c_state)
 
endmodule
/trunk/src/tb/mesi_isc_tb_define.v
0,0 → 1,73
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
//// ////
//// MESI_ISC Project ////
//// ////
//// Author(s): ////
//// - Yair Amitay yair.amitay@yahoo.com ////
//// www.linkedin.com/in/yairamitay ////
//// ////
//// Description ////
//// mesi_isc_tb_define ////
//// ------------------- ////
//// Contains the timescale and the define declaration of the ////
//// block tb ////
//// ////
//////////////////////////////////////////////////////////////////////
 
//`define messages
 
`define mesi_isc_debug
 
// CPU instructions
`define MESI_ISC_TB_INS_NOP 4'd0
`define MESI_ISC_TB_INS_WR 4'd1
`define MESI_ISC_TB_INS_RD 4'd2
 
`define MESI_ISC_TB_CPU_M_STATE_IDLE 0
`define MESI_ISC_TB_CPU_M_STATE_WR_CACHE 1
`define MESI_ISC_TB_CPU_M_STATE_RD_CACHE 2
`define MESI_ISC_TB_CPU_M_STATE_SEND_WR_BR 3
`define MESI_ISC_TB_CPU_M_STATE_SEND_RD_BR 4
 
`define MESI_ISC_TB_CPU_C_STATE_IDLE 0
`define MESI_ISC_TB_CPU_C_STATE_WR_SNOOP 1
`define MESI_ISC_TB_CPU_C_STATE_RD_SNOOP 2
`define MESI_ISC_TB_CPU_C_STATE_EVICT_INVALIDATE 3
`define MESI_ISC_TB_CPU_C_STATE_EVICT 4
`define MESI_ISC_TB_CPU_C_STATE_RD_LINE_WR 5
`define MESI_ISC_TB_CPU_C_STATE_RD_LINE_RD 6
`define MESI_ISC_TB_CPU_C_STATE_RD_CACHE 7
`define MESI_ISC_TB_CPU_C_STATE_WR_CACHE 8
 
 
`define MESI_ISC_TB_CPU_MESI_M 4'b1001
`define MESI_ISC_TB_CPU_MESI_E 4'b0101
`define MESI_ISC_TB_CPU_MESI_S 4'b0011
`define MESI_ISC_TB_CPU_MESI_I 4'b0000
/trunk/src/README.txt
0,0 → 1,7
MESI_ISC Project
=================
 
Directoy: src
=================
 
Contains all the project`s source files.

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