URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 10 to Rev 11
- ↔ Reverse comparison
Rev 10 → Rev 11
/minsoc/trunk/bench/verilog/minsoc_bench.v
54,6 → 54,7
initial begin |
reset = 1'b0; |
clock = 1'b0; |
uart_srx = 1'b1; |
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//dual and two port rams from FPGA memory instances have to be initialized to |
//0 |
/minsoc/trunk/sw/support/int.c
66,11 → 66,9
/* Main interrupt handler */ |
void int_main() |
{ |
unsigned long picsr = mfspr(SPR_PICSR); |
unsigned long picsr = mfspr(SPR_PICSR); //process only the interrupts asserted at signal catch, ignore all during process |
unsigned long i = 0; |
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mtspr(SPR_PICSR, 0); |
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while(i < 32) { |
if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) { |
(*int_handlers[i].handler)(int_handlers[i].arg); |
77,6 → 75,9
} |
i++; |
} |
} |
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mtspr(SPR_PICSR, 0); //clear interrupt status: all modules have level interrupts, which have to be cleared by software, |
} //thus this is safe, since non processed interrupts will get re-asserted soon enough |
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#endif |