OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 157 to Rev 158
    Reverse comparison

Rev 157 → Rev 158

/minsoc/trunk/utils/setup/minsoc-install.sh
204,7 → 204,7
#Installing Advanced JTAG Bridge
execcmd "cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge"
execcmd "./autogen.sh"
execcmd "./configure --enable-jsp-server=no --prefix=${DIR_TO_INSTALL}/tools CPPFLAGS=-I${DIR_TO_INSTALL}=tools/include LDFLAGS=-L${DIR_TO_INSTALL}/tools/lib LDFLAGS=-Wl,-R${DIR_TO_INSTALL}/tools/lib"
execcmd "./configure --enable-jsp-server=yes --prefix=${DIR_TO_INSTALL}/tools CPPFLAGS=-I${DIR_TO_INSTALL}=tools/include LDFLAGS=-L${DIR_TO_INSTALL}/tools/lib LDFLAGS=-Wl,-R${DIR_TO_INSTALL}/tools/lib"
execcmd "Compiling Advanced JTAG Bridge" "make"
execcmd "make install"
 
/minsoc/trunk/utils/setup/configure.sh
6,12 → 6,6
execcmd "Configuring MinSoC as standard board (simulatable but not synthesizable)" "./configure"
execcmd "cd ${DIR_TO_INSTALL}"
 
 
#Configuring Advanced Debug System to work with MinSoC
cecho "\nConfiguring Advanced Debug System to work with MinSoC"
execcmd "cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog"
execcmd "Turning off Advanced Debug System's JSP" "sed 's%\`define DBG_JSP_SUPPORTED%//\`define DBG_JSP_SUPPORTED%' adbg_defines.v > TMPFILE && mv TMPFILE adbg_defines.v"
 
#Compiling and moving adv_jtag_bridge debug modules for simulation
execcmd "cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/icarus"
execcmd "Compiling VPI interface to connect GDB with simulation" "make"
/minsoc/trunk/rtl/verilog/interconnect_defines.v
0,0 → 1,26
//
// Interrupts
//
`define APP_INT_RES1 1:0
`define APP_INT_UART 2
`define APP_INT_RES2 3
`define APP_INT_ETH 4
`define APP_INT_PS2 5
`define APP_INT_JSP 6
`define APP_INT_RES3 19:7
 
//
// Address map
//
`define APP_ADDR_DEC_W 8
`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00
`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04
`define APP_ADDR_DECP_W 4
`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9
`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97
`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92
`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d
`define APP_ADDR_UART `APP_ADDR_DEC_W'h90
`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94
`define APP_ADDR_JSP `APP_ADDR_DEC_W'h9e
`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f
/minsoc/trunk/rtl/verilog/minsoc_top.v
1,4 → 1,5
`include "minsoc_defines.v"
`include "interconnect_defines.v"
`include "or1200_defines.v"
 
module minsoc_top (
116,6 → 117,19
wire wb_dm_err_i;
 
//
// Debug core JSP slave i/f wires
//
wire [31:0] wb_jsp_dat_i;
wire [31:0] wb_jsp_dat_o;
wire [31:0] wb_jsp_adr_i;
wire [3:0] wb_jsp_sel_i;
wire wb_jsp_we_i;
wire wb_jsp_cyc_i;
wire wb_jsp_stb_i;
wire wb_jsp_ack_o;
wire wb_jsp_err_o;
 
//
// Debug <-> RISC wires
//
wire [3:0] dbg_lss;
303,13 → 317,6
);
 
//
// Unused WISHBONE signals
//
assign wb_us_err_o = 1'b0;
assign wb_fs_err_o = 1'b0;
assign wb_sp_err_o = 1'b0;
 
//
// Unused interrupts
//
assign pic_ints[`APP_INT_RES1] = 'b0;
445,10 → 452,52
.cpu0_stb_o ( dbg_stb ),
.cpu0_we_o ( dbg_we ),
.cpu0_ack_i ( dbg_ack ),
.cpu0_rst_o ( )
.cpu0_rst_o ( ),
 
// WISHBONE slave interface (JTAG UART)
`ifdef JSP
.wb_jsp_adr_i ( wb_jsp_adr_i[31:0] ),
.wb_jsp_dat_i ( wb_jsp_dat_i[31:0] ),
.wb_jsp_dat_o ( wb_jsp_dat_o[31:0] ),
.wb_jsp_we_i ( wb_jsp_we_i ),
.wb_jsp_stb_i ( wb_jsp_stb_i ),
.wb_jsp_cyc_i ( wb_jsp_cyc_i ),
.wb_jsp_ack_o ( wb_jsp_ack_o ),
.wb_jsp_sel_i ( wb_jsp_sel_i[3:0] ),
.wb_jsp_cab_i ( 1'b0 ),
.wb_jsp_cti_i ( 3'b0 ),
.wb_jsp_bte_i ( 2'b0 ),
 
// Interrupt request
.int_o ( pic_ints[`APP_INT_JSP] )
`else
.wb_jsp_adr_i ( 32'h0000_0000 ),
.wb_jsp_dat_i ( 32'h0000_0000 ),
.wb_jsp_dat_o ( ),
.wb_jsp_we_i ( 1'b0 ),
.wb_jsp_stb_i ( 1'b0 ),
.wb_jsp_cyc_i ( 1'b0 ),
.wb_jsp_ack_o ( ),
.wb_jsp_sel_i ( 4'h0 ),
.wb_jsp_cab_i ( 1'b0 ),
.wb_jsp_cti_i ( 3'b0 ),
.wb_jsp_bte_i ( 2'b0 ),
 
// Interrupt request
.int_o ( )
`endif
);
 
`ifdef JSP
assign wb_jsp_err_o = 1'b0;
`else
assign wb_jsp_dat_o = 32'h0000_0000;
assign wb_jsp_ack_o = 1'b0;
assign wb_jsp_err_o = 1'b1;
assign pic_ints[`APP_INT_JSP] = 1'b0;
`endif
 
 
//
// JTAG TAP controller instantiation
//
631,11 → 680,17
.sclk_pad_o(spi_flash_sclk),
.ss_pad_o(spi_flash_ss)
);
 
assign wb_fs_err_o = 1'b0;
assign wb_sp_err_o = 1'b0;
 
`else
assign wb_fs_dat_o = 32'h0000_0000;
assign wb_fs_ack_o = 1'b0;
assign wb_fs_err_o = 1'b1;
assign wb_sp_dat_o = 32'h0000_0000;
assign wb_sp_ack_o = 1'b0;
assign wb_sp_err_o = 1'b1;
`endif
 
//
703,9 → 758,12
.ri_pad_i ( 1'b0 ),
.dcd_pad_i ( 1'b0 )
);
 
assign wb_us_err_o = 1'b0;
`else
assign wb_us_dat_o = 32'h0000_0000;
assign wb_us_ack_o = 1'b0;
assign wb_us_err_o = 1'b1;
 
assign pic_ints[`APP_INT_UART] = 1'b0;
`endif
768,7 → 826,7
`else
assign wb_es_dat_o = 32'h0000_0000;
assign wb_es_ack_o = 1'b0;
assign wb_es_err_o = 1'b0;
assign wb_es_err_o = 1'b1;
 
assign wb_em_adr_o = 32'h0000_0000;
assign wb_em_sel_o = 4'h0;
793,9 → 851,9
`APP_ADDR_SPI,
`APP_ADDR_ETH,
`APP_ADDR_AUDIO,
`APP_ADDR_UART,
`APP_ADDR_UART,
`APP_ADDR_PS2,
`APP_ADDR_RES1,
`APP_ADDR_JSP,
`APP_ADDR_RES2
) tc_top (
 
955,8 → 1013,8
.t5_wb_dat_o ( wb_us_dat_i ),
.t5_wb_dat_i ( wb_us_dat_o ),
.t5_wb_ack_i ( wb_us_ack_o ),
.t5_wb_err_i ( wb_us_err_o ),
 
.t5_wb_err_i ( wb_us_err_o ),
// WISHBONE Target 6
.t6_wb_cyc_o ( ),
.t6_wb_stb_o ( ),
969,17 → 1027,17
.t6_wb_err_i ( 1'b1 ),
 
// WISHBONE Target 7
.t7_wb_cyc_o ( ),
.t7_wb_stb_o ( ),
.t7_wb_adr_o ( ),
.t7_wb_sel_o ( ),
.t7_wb_we_o ( ),
.t7_wb_dat_o ( ),
.t7_wb_dat_i ( 32'h0000_0000 ),
.t7_wb_ack_i ( 1'b0 ),
.t7_wb_err_i ( 1'b1 ),
.t7_wb_cyc_o ( wb_jsp_cyc_i ),
.t7_wb_stb_o ( wb_jsp_stb_i ),
.t7_wb_adr_o ( wb_jsp_adr_i ),
.t7_wb_sel_o ( wb_jsp_sel_i ),
.t7_wb_we_o ( wb_jsp_we_i ),
.t7_wb_dat_o ( wb_jsp_dat_i ),
.t7_wb_dat_i ( wb_jsp_dat_o ),
.t7_wb_ack_i ( wb_jsp_ack_o ),
.t7_wb_err_i ( wb_jsp_err_o ),
 
// WISHBONE Target 8
// WISHBONE Target 8
.t8_wb_cyc_o ( ),
.t8_wb_stb_o ( ),
.t8_wb_adr_o ( ),
/minsoc/trunk/backend/de2_115_board/configure
0,0 → 1,124
#!/bin/bash
 
#new boards have to udpate this
BOARD=de2_115_board #this has to have the name of the directory this file is in
DEVICE_PART=EP4CE115F29C7
CONSTRAINT_FILE='de2_115_board.ucf'
FAMILY_PART="Cyclone IV E"
#~new boards update
 
#system workings
MINSOC_DIR=`pwd`/../..
BACKEND_DIR=$MINSOC_DIR/backend
SYN_DIR=$MINSOC_DIR/syn
SYNSRC_DIR=$MINSOC_DIR/prj/altera
SYNSUPPORT_DIR=$SYN_DIR/buildSupport
MAKEFILE_DIR=$SYN_DIR/altera
 
PROJECT_FILE=minsoc_top.qsf
 
SYN_FILES=(adbg_top.vprj jtag_top.vprj or1200_top.vprj uart_top.vprj minsoc_top.vprj altera_virtual_jtag.vhdprj)
MAKEFILE=Makefile
 
FIND_PART='DEVICE_PART'
FIND_FAMILY='FAMILY_PART'
FIND_VERSION='SW_VERSION'
FIND_CONSTRAINT='CONSTRAINT_FILE'
 
BOARD_DIR=$BACKEND_DIR/$BOARD
BOARD_FILES=(board.h orp.ld minsoc_defines.v minsoc_bench_defines.v gcc-opt.mk $CONSTRAINT_FILE)
 
in_minsoc=`pwd | grep minsoc/backend/${BOARD}$`
if [ -z $in_minsoc ]
then
echo ""
echo " !!!WARNING!!!"
echo "This script cannot be run if not in a board directory inside minsoc/backend,"
echo "because it relies on the directory structure of the minsoc system."
echo ""
echo "Possibly your minsoc directory is named differently, minsoc_trunk for example."
echo "Its name must be minsoc only."
echo ""
exit 1
fi
 
echo ""
echo "This script sets up the SoC for simulations and synthesis."
echo ""
echo "In order to do so, SoC board's specific files for firmware compilation, "
echo "testbench generation and synthesis are configured."
echo "Firmware and testbench looks for board specific files under $BACKEND_DIR."
echo "Synthesis work under $SYN_DIR."
echo ""
echo ""
 
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory."
echo "__________________________________________________________________________"
echo ""
for file in "${BOARD_FILES[@]}"
do
if [ $file != NONE ]
then
echo "Copying $file, to backend directory..."
cp $BOARD_DIR/$file $BACKEND_DIR
fi
done
 
echo "Generating project files for simulation and synthesis..."
echo "__________________________________________________________________________"
echo ""
make -C $MINSOC_DIR/prj
echo "Generation complete."
echo ""
echo ""
 
if [ $CONSTRAINT_FILE == 'NONE' ]
then
echo "Skipping synthesis preparation. Standard implementation can only be simulated."
echo ""
echo ""
else
echo "Device part and family for files under $SYNSRC_DIR will patched and stored "
echo "temporarily."
echo "Afterwards, they are copied to $SYNSUPPORT_DIR."
echo "__________________________________________________________________________"
echo ""
sed "s/$FIND_PART/$DEVICE_PART/g" $MAKEFILE_DIR/$PROJECT_FILE > TMPFILE
sed "s/$FIND_FAMILY/$FAMILY_PART/g" TMPFILE > TMPFILE2
#sed "s/$FIND_VERSION/$SW_VERSION/g" TMPFILE> TMPFILE
echo "Adding settings from constraint file..."
cat $CONSTRAINT_FILE >> TMPFILE2
 
echo "Generating quartus settings from prj files in $SYNSRC_DIR"
for file in "${SYN_FILES[@]}"
do
echo "Adding settings from file $file..."
cat $SYNSRC_DIR/$file >> TMPFILE2
done
mv TMPFILE2 $SYNSUPPORT_DIR/$PROJECT_FILE
rm TMPFILE
echo ""
echo "Generated quartus settings file in $SYNSUPPORT_DIR/$PROJECT_FILE"
echo ""
 
echo "Copying Makefile from $MAKEFILE_DIR to synthesis directory, $SYN_DIR..."
cp $MAKEFILE_DIR/$MAKEFILE $SYN_DIR/$MAKEFILE
cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat
echo "For synthesis help go to $SYN_DIR and type \"make\"."
echo ""
echo ""
fi
 
#Precompiling firmwares
echo "Precompiling delivered libraries and firmwares..."
make -C ../../sw/utils
make -C ../../sw/support
make -C ../../sw/drivers
make -C ../../sw/uart
make -C ../../sw/jsp
make -C ../../sw/eth
echo "done."
echo ""
echo ""
 
echo "Configuration done."
minsoc/trunk/backend/de2_115_board/configure Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc/trunk/backend/de2_115_board/gcc-opt.mk =================================================================== --- minsoc/trunk/backend/de2_115_board/gcc-opt.mk (nonexistent) +++ minsoc/trunk/backend/de2_115_board/gcc-opt.mk (revision 158) @@ -0,0 +1 @@ +GCC_OPT=-mhard-mul -mhard-div -nostdlib Index: minsoc/trunk/backend/de2_115_board/de2_115_board.ucf =================================================================== --- minsoc/trunk/backend/de2_115_board/de2_115_board.ucf (nonexistent) +++ minsoc/trunk/backend/de2_115_board/de2_115_board.ucf (revision 158) @@ -0,0 +1,1172 @@ +# Altera DE2_115 board based pinout and definitions. +# This file uses quartus qsf file format for compose final config file. + +# Pin mappings required by MinSoc_top + +# RS232 Port +set_location_assignment PIN_G12 -to uart_srx +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_srx +set_location_assignment PIN_G9 -to uart_stx +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_stx + +# 50 Mhz Pin +set_location_assignment PIN_Y2 -to clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk + +# Reset pin. +set_location_assignment PIN_M23 -to reset +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to reset + +# NOTES: pins G12, G9, Y2, and M23 above are overloaded by standard +# DE2_115 design terms below + + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_Y2 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 +set_location_assignment PIN_AG14 -to CLOCK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50 +set_location_assignment PIN_AG15 -to CLOCK3_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50 + +#============================================================ +# Sma +#============================================================ +set_location_assignment PIN_AH14 -to SMA_CLKIN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKIN +set_location_assignment PIN_AE23 -to SMA_CLKOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKOUT + +#============================================================ +# LED +#============================================================ +set_location_assignment PIN_G19 -to LEDR[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[0] +set_location_assignment PIN_F19 -to LEDR[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[1] +set_location_assignment PIN_E19 -to LEDR[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[2] +set_location_assignment PIN_F21 -to LEDR[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[3] +set_location_assignment PIN_F18 -to LEDR[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[4] +set_location_assignment PIN_E18 -to LEDR[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[5] +set_location_assignment PIN_J19 -to LEDR[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[6] +set_location_assignment PIN_H19 -to LEDR[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[7] +set_location_assignment PIN_J17 -to LEDR[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[8] +set_location_assignment PIN_G17 -to LEDR[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[9] +set_location_assignment PIN_J15 -to LEDR[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[10] +set_location_assignment PIN_H16 -to LEDR[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[11] +set_location_assignment PIN_J16 -to LEDR[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[12] +set_location_assignment PIN_H17 -to LEDR[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[13] +set_location_assignment PIN_F15 -to LEDR[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[14] +set_location_assignment PIN_G15 -to LEDR[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[15] +set_location_assignment PIN_G16 -to LEDR[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[16] +set_location_assignment PIN_H15 -to LEDR[17] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[17] +set_location_assignment PIN_E21 -to LEDG[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[0] +set_location_assignment PIN_E22 -to LEDG[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[1] +set_location_assignment PIN_E25 -to LEDG[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[2] +set_location_assignment PIN_E24 -to LEDG[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[3] +set_location_assignment PIN_H21 -to LEDG[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[4] +set_location_assignment PIN_G20 -to LEDG[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[5] +set_location_assignment PIN_G22 -to LEDG[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[6] +set_location_assignment PIN_G21 -to LEDG[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[7] +set_location_assignment PIN_F17 -to LEDG[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[8] + +#============================================================ +# KEY +#============================================================ +set_location_assignment PIN_M23 -to KEY[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[0] +set_location_assignment PIN_M21 -to KEY[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[1] +set_location_assignment PIN_N21 -to KEY[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[2] +set_location_assignment PIN_R24 -to KEY[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[3] + +#============================================================ +# EJTAG +#============================================================ +set_location_assignment PIN_J10 -to EX_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[0] +set_location_assignment PIN_J14 -to EX_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[1] +set_location_assignment PIN_H13 -to EX_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[2] +set_location_assignment PIN_H14 -to EX_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[3] +set_location_assignment PIN_F14 -to EX_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[4] +set_location_assignment PIN_E10 -to EX_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[5] +set_location_assignment PIN_D9 -to EX_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[6] + +#============================================================ +# SW +#============================================================ +set_location_assignment PIN_AB28 -to SW[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0] +set_location_assignment PIN_AC28 -to SW[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1] +set_location_assignment PIN_AC27 -to SW[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2] +set_location_assignment PIN_AD27 -to SW[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3] +set_location_assignment PIN_AB27 -to SW[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[4] +set_location_assignment PIN_AC26 -to SW[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[5] +set_location_assignment PIN_AD26 -to SW[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[6] +set_location_assignment PIN_AB26 -to SW[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[7] +set_location_assignment PIN_AC25 -to SW[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[8] +set_location_assignment PIN_AB25 -to SW[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[9] +set_location_assignment PIN_AC24 -to SW[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[10] +set_location_assignment PIN_AB24 -to SW[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[11] +set_location_assignment PIN_AB23 -to SW[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[12] +set_location_assignment PIN_AA24 -to SW[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[13] +set_location_assignment PIN_AA23 -to SW[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[14] +set_location_assignment PIN_AA22 -to SW[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[15] +set_location_assignment PIN_Y24 -to SW[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[16] +set_location_assignment PIN_Y23 -to SW[17] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[17] + +#============================================================ +# SEG7 +#============================================================ +set_location_assignment PIN_G18 -to HEX0[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[0] +set_location_assignment PIN_F22 -to HEX0[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[1] +set_location_assignment PIN_E17 -to HEX0[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[2] +set_location_assignment PIN_L26 -to HEX0[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[3] +set_location_assignment PIN_L25 -to HEX0[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[4] +set_location_assignment PIN_J22 -to HEX0[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[5] +set_location_assignment PIN_H22 -to HEX0[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[6] +set_location_assignment PIN_M24 -to HEX1[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[0] +set_location_assignment PIN_Y22 -to HEX1[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[1] +set_location_assignment PIN_W21 -to HEX1[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[2] +set_location_assignment PIN_W22 -to HEX1[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[3] +set_location_assignment PIN_W25 -to HEX1[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[4] +set_location_assignment PIN_U23 -to HEX1[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[5] +set_location_assignment PIN_U24 -to HEX1[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[6] +set_location_assignment PIN_AA25 -to HEX2[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[0] +set_location_assignment PIN_AA26 -to HEX2[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[1] +set_location_assignment PIN_Y25 -to HEX2[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[2] +set_location_assignment PIN_W26 -to HEX2[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[3] +set_location_assignment PIN_Y26 -to HEX2[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[4] +set_location_assignment PIN_W27 -to HEX2[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[5] +set_location_assignment PIN_W28 -to HEX2[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[6] +set_location_assignment PIN_V21 -to HEX3[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[0] +set_location_assignment PIN_U21 -to HEX3[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[1] +set_location_assignment PIN_AB20 -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_location_assignment PIN_AA21 -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_location_assignment PIN_AD24 -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_location_assignment PIN_AF23 -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_location_assignment PIN_Y19 -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] +set_location_assignment PIN_AB19 -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_location_assignment PIN_AA19 -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_location_assignment PIN_AG21 -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_location_assignment PIN_AH21 -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_location_assignment PIN_AE19 -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_location_assignment PIN_AF19 -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_location_assignment PIN_AE18 -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] +set_location_assignment PIN_AD18 -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_location_assignment PIN_AC18 -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_location_assignment PIN_AB18 -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_location_assignment PIN_AH19 -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_location_assignment PIN_AG19 -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_location_assignment PIN_AF18 -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_location_assignment PIN_AH18 -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] +set_location_assignment PIN_AA17 -to HEX6[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[0] +set_location_assignment PIN_AB16 -to HEX6[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[1] +set_location_assignment PIN_AA16 -to HEX6[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[2] +set_location_assignment PIN_AB17 -to HEX6[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[3] +set_location_assignment PIN_AB15 -to HEX6[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[4] +set_location_assignment PIN_AA15 -to HEX6[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[5] +set_location_assignment PIN_AC17 -to HEX6[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[6] +set_location_assignment PIN_AD17 -to HEX7[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[0] +set_location_assignment PIN_AE17 -to HEX7[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[1] +set_location_assignment PIN_AG17 -to HEX7[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[2] +set_location_assignment PIN_AH17 -to HEX7[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[3] +set_location_assignment PIN_AF17 -to HEX7[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[4] +set_location_assignment PIN_AG18 -to HEX7[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[5] +set_location_assignment PIN_AA14 -to HEX7[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[6] + +#============================================================ +# LCD +#============================================================ +set_location_assignment PIN_L3 -to LCD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0] +set_location_assignment PIN_L1 -to LCD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1] +set_location_assignment PIN_L2 -to LCD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2] +set_location_assignment PIN_K7 -to LCD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3] +set_location_assignment PIN_K1 -to LCD_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4] +set_location_assignment PIN_K2 -to LCD_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5] +set_location_assignment PIN_M3 -to LCD_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6] +set_location_assignment PIN_M5 -to LCD_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7] +set_location_assignment PIN_L6 -to LCD_BLON +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON +set_location_assignment PIN_M1 -to LCD_RW +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW +set_location_assignment PIN_L4 -to LCD_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN +set_location_assignment PIN_M2 -to LCD_RS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS +set_location_assignment PIN_L5 -to LCD_ON +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_ON + +#============================================================ +# RS232 +#============================================================ +set_location_assignment PIN_G9 -to UART_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD +set_location_assignment PIN_G12 -to UART_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD +set_location_assignment PIN_G14 -to UART_CTS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS +set_location_assignment PIN_J13 -to UART_RTS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS + +#============================================================ +# PS2 for Keyboard and Mouse +#============================================================ +set_location_assignment PIN_G6 -to PS2_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK +set_location_assignment PIN_H5 -to PS2_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT +set_location_assignment PIN_G5 -to PS2_CLK2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2 +set_location_assignment PIN_F5 -to PS2_DAT2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2 + +#============================================================ +# SDCARD +#============================================================ +set_location_assignment PIN_AD14 -to SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD +set_location_assignment PIN_AE13 -to SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK +set_location_assignment PIN_AF14 -to SD_WP_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N +set_location_assignment PIN_AE14 -to SD_DAT[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[0] +set_location_assignment PIN_AF13 -to SD_DAT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[1] +set_location_assignment PIN_AB14 -to SD_DAT[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[2] +set_location_assignment PIN_AC14 -to SD_DAT[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[3] + +#============================================================ +# VGA +#============================================================ +set_location_assignment PIN_G13 -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_location_assignment PIN_C13 -to VGA_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N +set_location_assignment PIN_A12 -to VGA_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK +set_location_assignment PIN_F11 -to VGA_BLANK_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N +set_location_assignment PIN_E12 -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_location_assignment PIN_E11 -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_location_assignment PIN_D10 -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_location_assignment PIN_F12 -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_location_assignment PIN_G10 -to VGA_R[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] +set_location_assignment PIN_J12 -to VGA_R[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] +set_location_assignment PIN_H8 -to VGA_R[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] +set_location_assignment PIN_H10 -to VGA_R[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] +set_location_assignment PIN_G8 -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_location_assignment PIN_G11 -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_location_assignment PIN_F8 -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_location_assignment PIN_H12 -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_location_assignment PIN_C8 -to VGA_G[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] +set_location_assignment PIN_B8 -to VGA_G[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] +set_location_assignment PIN_F10 -to VGA_G[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] +set_location_assignment PIN_C9 -to VGA_G[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] +set_location_assignment PIN_B10 -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_location_assignment PIN_A10 -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_location_assignment PIN_C11 -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_location_assignment PIN_B11 -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_location_assignment PIN_A11 -to VGA_B[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] +set_location_assignment PIN_C12 -to VGA_B[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] +set_location_assignment PIN_D11 -to VGA_B[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] +set_location_assignment PIN_D12 -to VGA_B[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] + +#============================================================ +# Audio +#============================================================ +set_location_assignment PIN_C2 -to AUD_ADCLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK +set_location_assignment PIN_D2 -to AUD_ADCDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT +set_location_assignment PIN_E3 -to AUD_DACLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK +set_location_assignment PIN_D1 -to AUD_DACDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT +set_location_assignment PIN_E1 -to AUD_XCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK +set_location_assignment PIN_F2 -to AUD_BCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK + +#============================================================ +# I2C for EEPROM +#============================================================ +set_location_assignment PIN_D14 -to EEP_I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SCLK +set_location_assignment PIN_E14 -to EEP_I2C_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SDAT + +#============================================================ +# I2C for Audio Tv-Decoder HSMC +#============================================================ +set_location_assignment PIN_B7 -to I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK +set_location_assignment PIN_A8 -to I2C_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT + +#============================================================ +# Ethernet 0 +#============================================================ +set_location_assignment PIN_A14 -to ENETCLK_25 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENETCLK_25 +set_location_assignment PIN_C18 -to ENET0_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[0] +set_location_assignment PIN_C16 -to ENET0_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[0] +set_location_assignment PIN_D19 -to ENET0_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[1] +set_location_assignment PIN_D16 -to ENET0_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[1] +set_location_assignment PIN_A19 -to ENET0_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[2] +set_location_assignment PIN_D17 -to ENET0_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[2] +set_location_assignment PIN_B19 -to ENET0_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[3] +set_location_assignment PIN_C15 -to ENET0_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[3] +set_location_assignment PIN_A17 -to ENET0_GTX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_GTX_CLK +set_location_assignment PIN_A18 -to ENET0_TX_EN +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_EN +set_location_assignment PIN_B18 -to ENET0_TX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_ER +set_location_assignment PIN_A21 -to ENET0_INT_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_INT_N +set_location_assignment PIN_C19 -to ENET0_RST_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RST_N +set_location_assignment PIN_C17 -to ENET0_RX_DV +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DV +set_location_assignment PIN_D18 -to ENET0_RX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_ER +set_location_assignment PIN_D15 -to ENET0_RX_CRS +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CRS +set_location_assignment PIN_E15 -to ENET0_RX_COL +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_COL +set_location_assignment PIN_A15 -to ENET0_RX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CLK +set_location_assignment PIN_B17 -to ENET0_TX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_CLK +set_location_assignment PIN_C20 -to ENET0_MDC +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDC +set_location_assignment PIN_B21 -to ENET0_MDIO +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDIO +set_location_assignment PIN_C14 -to ENET0_LINK100 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET0_LINK100 + +#============================================================ +# Ethernet 1 +#============================================================ +set_location_assignment PIN_C25 -to ENET1_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[0] +set_location_assignment PIN_B23 -to ENET1_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[0] +set_location_assignment PIN_A26 -to ENET1_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[1] +set_location_assignment PIN_C21 -to ENET1_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[1] +set_location_assignment PIN_B26 -to ENET1_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[2] +set_location_assignment PIN_A23 -to ENET1_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[2] +set_location_assignment PIN_C26 -to ENET1_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[3] +set_location_assignment PIN_D21 -to ENET1_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[3] +set_location_assignment PIN_C23 -to ENET1_GTX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_GTX_CLK +set_location_assignment PIN_B25 -to ENET1_TX_EN +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_EN +set_location_assignment PIN_A25 -to ENET1_TX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_ER +set_location_assignment PIN_D24 -to ENET1_INT_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_INT_N +set_location_assignment PIN_D22 -to ENET1_RST_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RST_N +set_location_assignment PIN_A22 -to ENET1_RX_DV +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DV +set_location_assignment PIN_C24 -to ENET1_RX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_ER +set_location_assignment PIN_D20 -to ENET1_RX_CRS +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CRS +set_location_assignment PIN_B22 -to ENET1_RX_COL +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_COL +set_location_assignment PIN_B15 -to ENET1_RX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CLK +set_location_assignment PIN_C22 -to ENET1_TX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_CLK +set_location_assignment PIN_D23 -to ENET1_MDC +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDC +set_location_assignment PIN_D25 -to ENET1_MDIO +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDIO +set_location_assignment PIN_D13 -to ENET1_LINK100 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET1_LINK100 + +#============================================================ +# TV Decoder +#============================================================ +set_location_assignment PIN_E5 -to TD_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS +set_location_assignment PIN_E4 -to TD_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS +set_location_assignment PIN_B14 -to TD_CLK27 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27 +set_location_assignment PIN_G7 -to TD_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N +set_location_assignment PIN_E8 -to TD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0] +set_location_assignment PIN_A7 -to TD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1] +set_location_assignment PIN_D8 -to TD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2] +set_location_assignment PIN_C7 -to TD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3] +set_location_assignment PIN_D7 -to TD_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4] +set_location_assignment PIN_D6 -to TD_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5] +set_location_assignment PIN_E7 -to TD_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6] +set_location_assignment PIN_F7 -to TD_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7] + +#============================================================ +# USB 2.0 OTG +#============================================================ +set_location_assignment PIN_J6 -to OTG_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[0] +set_location_assignment PIN_K4 -to OTG_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[1] +set_location_assignment PIN_J5 -to OTG_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[2] +set_location_assignment PIN_K3 -to OTG_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[3] +set_location_assignment PIN_J4 -to OTG_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[4] +set_location_assignment PIN_J3 -to OTG_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[5] +set_location_assignment PIN_J7 -to OTG_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[6] +set_location_assignment PIN_H6 -to OTG_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[7] +set_location_assignment PIN_H3 -to OTG_DATA[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[8] +set_location_assignment PIN_H4 -to OTG_DATA[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[9] +set_location_assignment PIN_G1 -to OTG_DATA[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[10] +set_location_assignment PIN_G2 -to OTG_DATA[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[11] +set_location_assignment PIN_G3 -to OTG_DATA[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[12] +set_location_assignment PIN_F1 -to OTG_DATA[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[13] +set_location_assignment PIN_F3 -to OTG_DATA[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[14] +set_location_assignment PIN_G4 -to OTG_DATA[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[15] +set_location_assignment PIN_H7 -to OTG_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[0] +set_location_assignment PIN_C3 -to OTG_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[1] +set_location_assignment PIN_A6 -to OTG_INT[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT[0] +set_location_assignment PIN_D5 -to OTG_INT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT[1] +set_location_assignment PIN_J1 -to OTG_DREQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[0] +set_location_assignment PIN_B4 -to OTG_DREQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[1] +set_location_assignment PIN_C4 -to OTG_DACK_N[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DACK_N[0] +set_location_assignment PIN_D4 -to OTG_DACK_N[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DACK_N[1] +set_location_assignment PIN_C6 -to OTG_FSPEED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_FSPEED +set_location_assignment PIN_B6 -to OTG_LSPEED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_LSPEED +set_location_assignment PIN_C5 -to OTG_RST_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RST_N +set_location_assignment PIN_A3 -to OTG_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_CS_N +set_location_assignment PIN_B3 -to OTG_RD_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RD_N +set_location_assignment PIN_A4 -to OTG_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_WE_N + +#============================================================ +# IR Receiver +#============================================================ +set_location_assignment PIN_Y15 -to IRDA_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD + +#============================================================ +# SDRAM +#============================================================ +set_location_assignment PIN_U7 -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_location_assignment PIN_R4 -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_location_assignment PIN_U2 -to DRAM_DQM[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0] +set_location_assignment PIN_W4 -to DRAM_DQM[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1] +set_location_assignment PIN_K8 -to DRAM_DQM[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[2] +set_location_assignment PIN_N8 -to DRAM_DQM[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[3] +set_location_assignment PIN_U6 -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_location_assignment PIN_V7 -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_location_assignment PIN_AA6 -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_location_assignment PIN_AE5 -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_location_assignment PIN_V6 -to DRAM_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +set_location_assignment PIN_T4 -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_location_assignment PIN_W3 -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_location_assignment PIN_W2 -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_location_assignment PIN_V4 -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_location_assignment PIN_W1 -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_location_assignment PIN_V3 -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_location_assignment PIN_V2 -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_location_assignment PIN_V1 -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_location_assignment PIN_U3 -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_location_assignment PIN_Y3 -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_location_assignment PIN_Y4 -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_location_assignment PIN_AB1 -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_location_assignment PIN_AA3 -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_location_assignment PIN_AB2 -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_location_assignment PIN_AC1 -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_location_assignment PIN_AB3 -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_location_assignment PIN_AC2 -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_location_assignment PIN_M8 -to DRAM_DQ[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[16] +set_location_assignment PIN_L8 -to DRAM_DQ[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[17] +set_location_assignment PIN_P2 -to DRAM_DQ[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[18] +set_location_assignment PIN_N3 -to DRAM_DQ[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[19] +set_location_assignment PIN_N4 -to DRAM_DQ[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[20] +set_location_assignment PIN_M4 -to DRAM_DQ[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[21] +set_location_assignment PIN_M7 -to DRAM_DQ[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[22] +set_location_assignment PIN_L7 -to DRAM_DQ[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[23] +set_location_assignment PIN_U5 -to DRAM_DQ[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[24] +set_location_assignment PIN_R7 -to DRAM_DQ[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[25] +set_location_assignment PIN_R1 -to DRAM_DQ[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[26] +set_location_assignment PIN_R2 -to DRAM_DQ[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[27] +set_location_assignment PIN_R3 -to DRAM_DQ[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[28] +set_location_assignment PIN_T3 -to DRAM_DQ[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[29] +set_location_assignment PIN_U4 -to DRAM_DQ[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[30] +set_location_assignment PIN_U1 -to DRAM_DQ[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[31] +set_location_assignment PIN_R6 -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_location_assignment PIN_V8 -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_location_assignment PIN_U8 -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_location_assignment PIN_P1 -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_location_assignment PIN_V5 -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_location_assignment PIN_W8 -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_location_assignment PIN_W7 -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_location_assignment PIN_AA7 -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_location_assignment PIN_Y5 -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_location_assignment PIN_Y6 -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_location_assignment PIN_R5 -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_location_assignment PIN_AA5 -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_location_assignment PIN_Y7 -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] + +#============================================================ +# SRAM +#============================================================ +set_location_assignment PIN_AB7 -to SRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[0] +set_location_assignment PIN_AD7 -to SRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[1] +set_location_assignment PIN_AE7 -to SRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[2] +set_location_assignment PIN_AC7 -to SRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[3] +set_location_assignment PIN_AB6 -to SRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[4] +set_location_assignment PIN_AE6 -to SRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[5] +set_location_assignment PIN_AB5 -to SRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[6] +set_location_assignment PIN_AC5 -to SRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[7] +set_location_assignment PIN_AF5 -to SRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[8] +set_location_assignment PIN_T7 -to SRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[9] +set_location_assignment PIN_AF2 -to SRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[10] +set_location_assignment PIN_AD3 -to SRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[11] +set_location_assignment PIN_AB4 -to SRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[12] +set_location_assignment PIN_AC3 -to SRAM_ADDR[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[13] +set_location_assignment PIN_AA4 -to SRAM_ADDR[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[14] +set_location_assignment PIN_AB11 -to SRAM_ADDR[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[15] +set_location_assignment PIN_AC11 -to SRAM_ADDR[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[16] +set_location_assignment PIN_AB9 -to SRAM_ADDR[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[17] +set_location_assignment PIN_AB8 -to SRAM_ADDR[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[18] +set_location_assignment PIN_T8 -to SRAM_ADDR[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[19] +set_location_assignment PIN_AH3 -to SRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[0] +set_location_assignment PIN_AF4 -to SRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[1] +set_location_assignment PIN_AG4 -to SRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[2] +set_location_assignment PIN_AH4 -to SRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[3] +set_location_assignment PIN_AF6 -to SRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[4] +set_location_assignment PIN_AG6 -to SRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[5] +set_location_assignment PIN_AH6 -to SRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[6] +set_location_assignment PIN_AF7 -to SRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[7] +set_location_assignment PIN_AD1 -to SRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[8] +set_location_assignment PIN_AD2 -to SRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[9] +set_location_assignment PIN_AE2 -to SRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[10] +set_location_assignment PIN_AE1 -to SRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[11] +set_location_assignment PIN_AE3 -to SRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[12] +set_location_assignment PIN_AE4 -to SRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[13] +set_location_assignment PIN_AF3 -to SRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[14] +set_location_assignment PIN_AG3 -to SRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[15] +set_location_assignment PIN_AC4 -to SRAM_UB_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_UB_N +set_location_assignment PIN_AD4 -to SRAM_LB_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_LB_N +set_location_assignment PIN_AF8 -to SRAM_CE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_CE_N +set_location_assignment PIN_AD5 -to SRAM_OE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_OE_N +set_location_assignment PIN_AE8 -to SRAM_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_WE_N + +#============================================================ +# Flash +#============================================================ +set_location_assignment PIN_AG12 -to FL_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0] +set_location_assignment PIN_AH7 -to FL_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1] +set_location_assignment PIN_Y13 -to FL_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2] +set_location_assignment PIN_Y14 -to FL_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3] +set_location_assignment PIN_Y12 -to FL_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4] +set_location_assignment PIN_AA13 -to FL_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5] +set_location_assignment PIN_AA12 -to FL_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6] +set_location_assignment PIN_AB13 -to FL_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7] +set_location_assignment PIN_AB12 -to FL_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8] +set_location_assignment PIN_AB10 -to FL_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9] +set_location_assignment PIN_AE9 -to FL_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10] +set_location_assignment PIN_AF9 -to FL_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11] +set_location_assignment PIN_AA10 -to FL_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12] +set_location_assignment PIN_AD8 -to FL_ADDR[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13] +set_location_assignment PIN_AC8 -to FL_ADDR[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14] +set_location_assignment PIN_Y10 -to FL_ADDR[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15] +set_location_assignment PIN_AA8 -to FL_ADDR[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16] +set_location_assignment PIN_AH12 -to FL_ADDR[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17] +set_location_assignment PIN_AC12 -to FL_ADDR[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18] +set_location_assignment PIN_AD12 -to FL_ADDR[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19] +set_location_assignment PIN_AE10 -to FL_ADDR[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20] +set_location_assignment PIN_AD10 -to FL_ADDR[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21] +set_location_assignment PIN_AD11 -to FL_ADDR[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[22] +set_location_assignment PIN_AH8 -to FL_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0] +set_location_assignment PIN_AF10 -to FL_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1] +set_location_assignment PIN_AG10 -to FL_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2] +set_location_assignment PIN_AH10 -to FL_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3] +set_location_assignment PIN_AF11 -to FL_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4] +set_location_assignment PIN_AG11 -to FL_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5] +set_location_assignment PIN_AH11 -to FL_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6] +set_location_assignment PIN_AF12 -to FL_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7] +set_location_assignment PIN_AG7 -to FL_CE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N +set_location_assignment PIN_AG8 -to FL_OE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N +set_location_assignment PIN_AE11 -to FL_RST_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N +set_location_assignment PIN_Y1 -to FL_RY +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY +set_location_assignment PIN_AC10 -to FL_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N +set_location_assignment PIN_AE12 -to FL_WP_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N + +#============================================================ +# GPIO, GPIO connect to GPIO Default +#============================================================ +set_location_assignment PIN_AB22 -to GPIO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] +set_location_assignment PIN_AC15 -to GPIO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] +set_location_assignment PIN_AB21 -to GPIO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] +set_location_assignment PIN_Y17 -to GPIO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] +set_location_assignment PIN_AC21 -to GPIO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] +set_location_assignment PIN_Y16 -to GPIO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] +set_location_assignment PIN_AD21 -to GPIO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] +set_location_assignment PIN_AE16 -to GPIO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] +set_location_assignment PIN_AD15 -to GPIO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] +set_location_assignment PIN_AE15 -to GPIO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] +set_location_assignment PIN_AC19 -to GPIO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] +set_location_assignment PIN_AF16 -to GPIO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] +set_location_assignment PIN_AD19 -to GPIO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] +set_location_assignment PIN_AF15 -to GPIO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] +set_location_assignment PIN_AF24 -to GPIO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] +set_location_assignment PIN_AE21 -to GPIO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] +set_location_assignment PIN_AF25 -to GPIO[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] +set_location_assignment PIN_AC22 -to GPIO[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] +set_location_assignment PIN_AE22 -to GPIO[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] +set_location_assignment PIN_AF21 -to GPIO[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] +set_location_assignment PIN_AF22 -to GPIO[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] +set_location_assignment PIN_AD22 -to GPIO[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] +set_location_assignment PIN_AG25 -to GPIO[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] +set_location_assignment PIN_AD25 -to GPIO[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] +set_location_assignment PIN_AH25 -to GPIO[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] +set_location_assignment PIN_AE25 -to GPIO[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] +set_location_assignment PIN_AG22 -to GPIO[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] +set_location_assignment PIN_AE24 -to GPIO[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] +set_location_assignment PIN_AH22 -to GPIO[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] +set_location_assignment PIN_AF26 -to GPIO[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] +set_location_assignment PIN_AE20 -to GPIO[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] +set_location_assignment PIN_AG23 -to GPIO[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] +set_location_assignment PIN_AF20 -to GPIO[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] +set_location_assignment PIN_AH26 -to GPIO[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] +set_location_assignment PIN_AH23 -to GPIO[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] +set_location_assignment PIN_AG26 -to GPIO[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] + +#============================================================ +# HSMC, HSMC connect to HSMC Default +#============================================================ +set_location_assignment PIN_AD28 -to HSMC_CLKOUT0 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT0 +set_location_assignment PIN_AH15 -to HSMC_CLKIN0 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN0 +set_location_assignment PIN_AE26 -to HSMC_D[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0] +set_location_assignment PIN_AE28 -to HSMC_D[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1] +set_location_assignment PIN_AE27 -to HSMC_D[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2] +set_location_assignment PIN_AF27 -to HSMC_D[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3] +set_location_assignment PIN_D27 -to HSMC_TX_D_P[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_P[0] +set_location_assignment PIN_F24 -to HSMC_RX_D_P[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_P[0] +set_location_assignment PIN_D28 -to HSMC_TX_D_N[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_N[0] +set_location_assignment PIN_F25 -to HSMC_RX_D_N[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_N[0] +set_location_assignment PIN_E27 -to HSMC_TX_D_P[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_P[1] +set_location_assignment PIN_D26 -to HSMC_RX_D_P[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_P[1] +set_location_assignment PIN_E28 -to HSMC_TX_D_N[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_N[1] +set_location_assignment PIN_C27 -to HSMC_RX_D_N[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_N[1] +set_location_assignment PIN_F27 -to HSMC_TX_D_P[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_P[2] +set_location_assignment PIN_F26 -to HSMC_RX_D_P[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_P[2] +set_location_assignment PIN_F28 -to HSMC_TX_D_N[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_N[2] +set_location_assignment PIN_E26 -to HSMC_RX_D_N[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_N[2] +set_location_assignment PIN_G27 -to HSMC_TX_D_P[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_P[3] +set_location_assignment PIN_G25 -to HSMC_RX_D_P[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_P[3] +set_location_assignment PIN_G28 -to HSMC_TX_D_N[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_N[3] +set_location_assignment PIN_G26 -to HSMC_RX_D_N[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_N[3] +set_location_assignment PIN_K27 -to HSMC_TX_D_P[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_P[4] +set_location_assignment PIN_H25 -to HSMC_RX_D_P[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_P[4] +set_location_assignment PIN_K28 -to HSMC_TX_D_N[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_N[4] +set_location_assignment PIN_H26 -to HSMC_RX_D_N[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_N[4] +set_location_assignment PIN_M27 -to HSMC_TX_D_P[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_P[5] +set_location_assignment PIN_K25 -to HSMC_RX_D_P[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_P[5] +set_location_assignment PIN_M28 -to HSMC_TX_D_N[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_N[5] +set_location_assignment PIN_K26 -to HSMC_RX_D_N[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_N[5] +set_location_assignment PIN_K21 -to HSMC_TX_D_P[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_P[6] +set_location_assignment PIN_L23 -to HSMC_RX_D_P[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_P[6] +set_location_assignment PIN_K22 -to HSMC_TX_D_N[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_N[6] +set_location_assignment PIN_L24 -to HSMC_RX_D_N[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_N[6] +set_location_assignment PIN_H23 -to HSMC_TX_D_P[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_P[7] +set_location_assignment PIN_M25 -to HSMC_RX_D_P[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_P[7] +set_location_assignment PIN_H24 -to HSMC_TX_D_N[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_N[7] +set_location_assignment PIN_M26 -to HSMC_RX_D_N[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_N[7] +set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_P1 +set_location_assignment PIN_J27 -to HSMC_CLKIN_P1 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_P1 +set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_N1 +set_location_assignment PIN_J28 -to HSMC_CLKIN_N1 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_N1 +set_location_assignment PIN_J23 -to HSMC_TX_D_P[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_P[8] +set_location_assignment PIN_R25 -to HSMC_RX_D_P[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_P[8] +set_location_assignment PIN_J24 -to HSMC_TX_D_N[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_N[8] +set_location_assignment PIN_R26 -to HSMC_RX_D_N[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_N[8] +set_location_assignment PIN_P27 -to HSMC_TX_D_P[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_P[9] +set_location_assignment PIN_T25 -to HSMC_RX_D_P[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_P[9] +set_location_assignment PIN_P28 -to HSMC_TX_D_N[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_N[9] +set_location_assignment PIN_T26 -to HSMC_RX_D_N[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_N[9] +set_location_assignment PIN_J25 -to HSMC_TX_D_P[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_P[10] +set_location_assignment PIN_U25 -to HSMC_RX_D_P[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_P[10] +set_location_assignment PIN_J26 -to HSMC_TX_D_N[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_N[10] +set_location_assignment PIN_U26 -to HSMC_RX_D_N[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_N[10] +set_location_assignment PIN_L27 -to HSMC_TX_D_P[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_P[11] +set_location_assignment PIN_L21 -to HSMC_RX_D_P[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_P[11] +set_location_assignment PIN_L28 -to HSMC_TX_D_N[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_N[11] +set_location_assignment PIN_L22 -to HSMC_RX_D_N[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_N[11] +set_location_assignment PIN_V25 -to HSMC_TX_D_P[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_P[12] +set_location_assignment PIN_N25 -to HSMC_RX_D_P[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_P[12] +set_location_assignment PIN_V26 -to HSMC_TX_D_N[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_N[12] +set_location_assignment PIN_N26 -to HSMC_RX_D_N[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_N[12] +set_location_assignment PIN_R27 -to HSMC_TX_D_P[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_P[13] +set_location_assignment PIN_P25 -to HSMC_RX_D_P[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_P[13] +set_location_assignment PIN_R28 -to HSMC_TX_D_N[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_N[13] +set_location_assignment PIN_P26 -to HSMC_RX_D_N[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_N[13] +set_location_assignment PIN_U27 -to HSMC_TX_D_P[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_P[14] +set_location_assignment PIN_P21 -to HSMC_RX_D_P[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_P[14] +set_location_assignment PIN_U28 -to HSMC_TX_D_N[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_N[14] +set_location_assignment PIN_R21 -to HSMC_RX_D_N[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_N[14] +set_location_assignment PIN_V27 -to HSMC_TX_D_P[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_P[15] +set_location_assignment PIN_R22 -to HSMC_RX_D_P[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_P[15] +set_location_assignment PIN_V28 -to HSMC_TX_D_N[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_N[15] +set_location_assignment PIN_R23 -to HSMC_RX_D_N[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_N[15] +set_location_assignment PIN_U22 -to HSMC_TX_D_P[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_P[16] +set_location_assignment PIN_T21 -to HSMC_RX_D_P[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_P[16] +set_location_assignment PIN_V22 -to HSMC_TX_D_N[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_TX_D_N[16] +set_location_assignment PIN_T22 -to HSMC_RX_D_N[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_RX_D_N[16] +set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_P2 +set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_P2 +set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT_N2 +set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKIN_N2 Index: minsoc/trunk/backend/de2_115_board/minsoc_bench_defines.v =================================================================== --- minsoc/trunk/backend/de2_115_board/minsoc_bench_defines.v (nonexistent) +++ minsoc/trunk/backend/de2_115_board/minsoc_bench_defines.v (revision 158) @@ -0,0 +1,29 @@ +//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) +`define GENERIC_FPGA +`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting. +`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) +//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) + +`define FREQ_NUM_FOR_NS 100000000 + +`define FREQ 25000000 +`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) + +`define ETH_PHY_FREQ 25000000 +`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns + +`define UART_BAUDRATE 115200 + +`define VPI_DEBUG + +//`define WAVEFORM_OUTPUT + +//`define START_UP //pass firmware over spi to or1k_startup + +`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware + //only use with the memory model. + //If you use the original memory (`define MEMORY_MODEL + //commented out), comment this too. + +`define TEST_UART +//`define TEST_ETHERNET Index: minsoc/trunk/backend/de2_115_board/minsoc_defines.v =================================================================== --- minsoc/trunk/backend/de2_115_board/minsoc_defines.v (nonexistent) +++ minsoc/trunk/backend/de2_115_board/minsoc_defines.v (revision 158) @@ -0,0 +1,125 @@ +// +// Define FPGA manufacturer: DE2_115 board +// +//`define GENERIC_FPGA +`define ALTERA_FPGA +//`define XILINX_FPGA + +// +// Define Xilinx FPGA family +// +`ifdef XILINX_FPGA +//`define SPARTAN2 +//`define SPARTAN3 +//`define SPARTAN3E +`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + +// +// Define Altera FPGA family +// +`elsif ALTERA_FPGA +//`define ARRIA_GX +//`define ARRIA_II_GX +//`define CYCLONE_I +//`define CYCLONE_II +//`define CYCLONE_III +//`define CYCLONE_III_LS +`define CYCLONE_IV_E +//`define CYCLONE_IV_GS +//`define MAX_II +//`define MAX_V +//`define MAX3000A +//`define MAX7000AE +//`define MAX7000B +//`define MAX7000S +//`define STRATIX +//`define STRATIX_II +//`define STRATIX_II_GX +//`define STRATIX_III +`endif + +// +// Memory +// +`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, + //memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, + //2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, + //memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. + +// +// Define division +// +`define CLOCK_DIVISOR 2 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded + //down to an even value in FPGA case, check minsoc_clock_manager + //for allowed divisors. + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION + //INSTEAD. + +// +// Reset polarity +// +`define NEGATIVE_RESET //rstn +//`define POSITIVE_RESET //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +`define JSP +//`define ETHERNET + +// +// Ethernet reset +// +//`define ETH_RESET 1'b0 +`define ETH_RESET 1'b1 + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `undef FPGA_TAP + `undef FPGA_CLOCK_DIVISION + `undef ALTERA_FPGA + `undef CYCLONE_IV_E + + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif Index: minsoc/trunk/backend/de2_115_board/board.h =================================================================== --- minsoc/trunk/backend/de2_115_board/board.h (nonexistent) +++ minsoc/trunk/backend/de2_115_board/board.h (revision 158) @@ -0,0 +1,24 @@ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define MC_ENABLED 0 + +#define IC_ENABLE 0 +#define IC_SIZE 8192 +#define DC_ENABLE 0 +#define DC_SIZE 8192 + +#define IN_CLK 25000000 + +#define STACK_SIZE 0x01000 + +#define UART_BAUD_RATE 115200 + +#define ETH_MACADDR0 0x00 +#define ETH_MACADDR1 0x12 +#define ETH_MACADDR2 0x34 +#define ETH_MACADDR3 0x56 +#define ETH_MACADDR4 0x78 +#define ETH_MACADDR5 0x9a + +#endif Index: minsoc/trunk/backend/de2_115_board/orp.ld =================================================================== --- minsoc/trunk/backend/de2_115_board/orp.ld (nonexistent) +++ minsoc/trunk/backend/de2_115_board/orp.ld (revision 158) @@ -0,0 +1,60 @@ +MEMORY + { + reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 + vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 + ram : ORIGIN = 0x00001200, LENGTH = 0x0001EE00 /*0x20000 total*/ + } + +SECTIONS +{ + .reset : + { + *(.reset) + } > reset + + + + .vectors : + { + _vec_start = .; + *(.vectors) + _vec_end = .; + } > vectors + + .text : + { + *(.text) + } > ram + + .rodata : + { + *(.rodata) + *(.rodata.*) + } > ram + + .icm : + { + _icm_start = .; + *(.icm) + _icm_end = .; + } > ram + + .data : + { + _dst_beg = .; + *(.data) + _dst_end = .; + } > ram + + .bss : + { + *(.bss) + } > ram + + .stack (NOLOAD) : + { + *(.stack) + _src_addr = .; + } > ram + +} Index: minsoc/trunk/backend/spartan3a_dsp_kit/configure =================================================================== --- minsoc/trunk/backend/spartan3a_dsp_kit/configure (revision 157) +++ minsoc/trunk/backend/spartan3a_dsp_kit/configure (revision 158) @@ -107,6 +107,7 @@ make -C ../../sw/support make -C ../../sw/drivers make -C ../../sw/uart +make -C ../../sw/jsp make -C ../../sw/eth echo "done." echo "" Index: minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_defines.v =================================================================== --- minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_defines.v (revision 157) +++ minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_defines.v (revision 158) @@ -98,6 +98,7 @@ // Connected modules // `define UART +`define JSP `define ETHERNET // @@ -107,32 +108,6 @@ `define ETH_RESET 1'b1 // -// Interrupts -// -`define APP_INT_RES1 1:0 -`define APP_INT_UART 2 -`define APP_INT_RES2 3 -`define APP_INT_ETH 4 -`define APP_INT_PS2 5 -`define APP_INT_RES3 19:6 - -// -// Address map -// -`define APP_ADDR_DEC_W 8 -`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 -`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 -`define APP_ADDR_DECP_W 4 -`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 -`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 -`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 -`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d -`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 -`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 -`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e -`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f - -// // Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen // and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set //
/minsoc/trunk/backend/spartan3a_dsp_kit/board.h
8,28 → 8,12
#define DC_ENABLE 0
#define DC_SIZE 8192
 
 
#define IN_CLK 25000000
 
 
#define STACK_SIZE 0x01000
 
#define UART_BAUD_RATE 115200
 
#define UART_BASE 0x90000000
#define UART_IRQ 2
#define ETH_BASE 0x92000000
#define ETH_IRQ 4
#define I2C_BASE 0x9D000000
#define I2C_IRQ 3
#define CAN_BASE 0x94000000
#define CAN_IRQ 5
 
#define MC_BASE_ADDR 0x60000000
#define SPI_BASE 0xa0000000
 
#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */
 
#define ETH_MACADDR0 0x00
#define ETH_MACADDR1 0x12
#define ETH_MACADDR2 0x34
/minsoc/trunk/backend/ug257/configure
109,6 → 109,7
make -C ../../sw/support
make -C ../../sw/drivers
make -C ../../sw/uart
make -C ../../sw/jsp
make -C ../../sw/eth
echo "done."
echo ""
/minsoc/trunk/backend/ug257/minsoc_defines.v
98,6 → 98,7
// Connected modules
//
`define UART
//`define JSP
//`define ETHERNET
 
//
107,32 → 108,6
//`define ETH_RESET 1'b1
 
//
// Interrupts
//
`define APP_INT_RES1 1:0
`define APP_INT_UART 2
`define APP_INT_RES2 3
`define APP_INT_ETH 4
`define APP_INT_PS2 5
`define APP_INT_RES3 19:6
 
//
// Address map
//
`define APP_ADDR_DEC_W 8
`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00
`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04
`define APP_ADDR_DECP_W 4
`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9
`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97
`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92
`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d
`define APP_ADDR_UART `APP_ADDR_DEC_W'h90
`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94
`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e
`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f
 
//
// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen
// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set
//
/minsoc/trunk/backend/ug257/board.h
8,28 → 8,12
#define DC_ENABLE 0
#define DC_SIZE 8192
 
 
#define IN_CLK 10000000
 
 
#define STACK_SIZE 0x01000
 
#define UART_BAUD_RATE 9600
 
#define UART_BASE 0x90000000
#define UART_IRQ 2
#define ETH_BASE 0x92000000
#define ETH_IRQ 4
#define I2C_BASE 0x9D000000
#define I2C_IRQ 3
#define CAN_BASE 0x94000000
#define CAN_IRQ 5
 
#define MC_BASE_ADDR 0x60000000
#define SPI_BASE 0xa0000000
 
#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */
 
#define ETH_MACADDR0 0x00
#define ETH_MACADDR1 0x12
#define ETH_MACADDR2 0x34
/minsoc/trunk/backend/std/configure
107,6 → 107,7
make -C ../../sw/support
make -C ../../sw/drivers
make -C ../../sw/uart
make -C ../../sw/jsp
make -C ../../sw/eth
echo "done."
echo ""
/minsoc/trunk/backend/std/minsoc_defines.v
98,6 → 98,7
// Connected modules
//
`define UART
`define JSP
`define ETHERNET
 
//
107,32 → 108,6
//`define ETH_RESET 1'b1
 
//
// Interrupts
//
`define APP_INT_RES1 1:0
`define APP_INT_UART 2
`define APP_INT_RES2 3
`define APP_INT_ETH 4
`define APP_INT_PS2 5
`define APP_INT_RES3 19:6
 
//
// Address map
//
`define APP_ADDR_DEC_W 8
`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00
`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04
`define APP_ADDR_DECP_W 4
`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9
`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97
`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92
`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d
`define APP_ADDR_UART `APP_ADDR_DEC_W'h90
`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94
`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e
`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f
 
//
// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen
// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set
//
/minsoc/trunk/backend/std/board.h
8,28 → 8,12
#define DC_ENABLE 0
#define DC_SIZE 8192
 
 
#define IN_CLK 25000000
 
 
#define STACK_SIZE 0x01000
 
#define UART_BAUD_RATE 115200
 
#define UART_BASE 0x90000000
#define UART_IRQ 2
#define ETH_BASE 0x92000000
#define ETH_IRQ 4
#define I2C_BASE 0x9D000000
#define I2C_IRQ 3
#define CAN_BASE 0x94000000
#define CAN_IRQ 5
 
#define MC_BASE_ADDR 0x60000000
#define SPI_BASE 0xa0000000
 
#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */
 
#define ETH_MACADDR0 0x00
#define ETH_MACADDR1 0x12
#define ETH_MACADDR2 0x34
/minsoc/trunk/backend/altera_3c25_board/configure
115,6 → 115,7
make -C ../../sw/support
make -C ../../sw/drivers
make -C ../../sw/uart
make -C ../../sw/jsp
make -C ../../sw/eth
echo "done."
echo ""
/minsoc/trunk/backend/altera_3c25_board/minsoc_defines.v
98,6 → 98,7
// Connected modules
//
`define UART
//`define JSP
//`define ETHERNET
 
//
107,32 → 108,6
`define ETH_RESET 1'b1
 
//
// Interrupts
//
`define APP_INT_RES1 1:0
`define APP_INT_UART 2
`define APP_INT_RES2 3
`define APP_INT_ETH 4
`define APP_INT_PS2 5
`define APP_INT_RES3 19:6
 
//
// Address map
//
`define APP_ADDR_DEC_W 8
`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00
`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04
`define APP_ADDR_DECP_W 4
`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9
`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97
`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92
`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d
`define APP_ADDR_UART `APP_ADDR_DEC_W'h90
`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94
`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e
`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f
 
//
// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen
// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set
//
/minsoc/trunk/backend/altera_3c25_board/board.h
8,28 → 8,12
#define DC_ENABLE 0
#define DC_SIZE 8192
 
 
#define IN_CLK 25000000
 
 
#define STACK_SIZE 0x01000
 
#define UART_BAUD_RATE 115200
 
#define UART_BASE 0x90000000
#define UART_IRQ 2
#define ETH_BASE 0x92000000
#define ETH_IRQ 4
#define I2C_BASE 0x9D000000
#define I2C_IRQ 3
#define CAN_BASE 0x94000000
#define CAN_IRQ 5
 
#define MC_BASE_ADDR 0x60000000
#define SPI_BASE 0xa0000000
 
#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */
 
#define ETH_MACADDR0 0x00
#define ETH_MACADDR1 0x12
#define ETH_MACADDR2 0x34
/minsoc/trunk/backend/spartan3e_starter_kit/configure
124,6 → 124,7
make -C ../../sw/support
make -C ../../sw/drivers
make -C ../../sw/uart
make -C ../../sw/jsp
make -C ../../sw/eth
echo "done."
echo ""
/minsoc/trunk/backend/spartan3e_starter_kit/minsoc_defines.v
98,6 → 98,7
// Connected modules
//
`define UART
//`define JSP
//`define ETHERNET
 
//
107,32 → 108,6
//`define ETH_RESET 1'b1
 
//
// Interrupts
//
`define APP_INT_RES1 1:0
`define APP_INT_UART 2
`define APP_INT_RES2 3
`define APP_INT_ETH 4
`define APP_INT_PS2 5
`define APP_INT_RES3 19:6
 
//
// Address map
//
`define APP_ADDR_DEC_W 8
`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00
`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04
`define APP_ADDR_DECP_W 4
`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9
`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97
`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92
`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d
`define APP_ADDR_UART `APP_ADDR_DEC_W'h90
`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94
`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e
`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f
 
//
// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen
// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set
//
/minsoc/trunk/backend/spartan3e_starter_kit/board.h
8,28 → 8,12
#define DC_ENABLE 0
#define DC_SIZE 8192
 
 
#define IN_CLK 25000000
 
 
#define STACK_SIZE 0x01000
 
#define UART_BAUD_RATE 115200
 
#define UART_BASE 0x90000000
#define UART_IRQ 2
#define ETH_BASE 0x92000000
#define ETH_IRQ 4
#define I2C_BASE 0x9D000000
#define I2C_IRQ 3
#define CAN_BASE 0x94000000
#define CAN_IRQ 5
 
#define MC_BASE_ADDR 0x60000000
#define SPI_BASE 0xa0000000
 
#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */
 
#define ETH_MACADDR0 0x00
#define ETH_MACADDR1 0x12
#define ETH_MACADDR2 0x34
/minsoc/trunk/backend/spartan3e_starter_kit_eth/configure
124,6 → 124,7
make -C ../../sw/support
make -C ../../sw/drivers
make -C ../../sw/uart
make -C ../../sw/jsp
make -C ../../sw/eth
echo "done."
echo ""
/minsoc/trunk/backend/spartan3e_starter_kit_eth/spartan3e_starter_kit_eth.ucf
11,8 → 11,8
#
# UART serial port (RS232 DCE) - connector DB9 female.
#
NET "uart_srx" LOC = "R7";
NET "uart_stx" LOC = "M14" | DRIVE = 8 | SLEW = SLOW ;
#NET "uart_srx" LOC = "R7";
#NET "uart_stx" LOC = "M14" | DRIVE = 8 | SLEW = SLOW ;
 
###########################
##
/minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_defines.v
97,7 → 97,8
//
// Connected modules
//
`define UART
//`define UART
`define JSP
`define ETHERNET
 
//
107,32 → 108,6
//`define ETH_RESET 1'b1
 
//
// Interrupts
//
`define APP_INT_RES1 1:0
`define APP_INT_UART 2
`define APP_INT_RES2 3
`define APP_INT_ETH 4
`define APP_INT_PS2 5
`define APP_INT_RES3 19:6
 
//
// Address map
//
`define APP_ADDR_DEC_W 8
`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00
`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04
`define APP_ADDR_DECP_W 4
`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9
`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97
`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92
`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d
`define APP_ADDR_UART `APP_ADDR_DEC_W'h90
`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94
`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e
`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f
 
//
// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen
// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set
//
/minsoc/trunk/backend/spartan3e_starter_kit_eth/board.h
8,28 → 8,12
#define DC_ENABLE 0
#define DC_SIZE 8192
 
 
#define IN_CLK 10000000
 
 
#define STACK_SIZE 0x00180
 
#define UART_BAUD_RATE 19200
 
#define UART_BASE 0x90000000
#define UART_IRQ 2
#define ETH_BASE 0x92000000
#define ETH_IRQ 4
#define I2C_BASE 0x9D000000
#define I2C_IRQ 3
#define CAN_BASE 0x94000000
#define CAN_IRQ 5
 
#define MC_BASE_ADDR 0x60000000
#define SPI_BASE 0xa0000000
 
#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */
 
#define ETH_MACADDR0 0x00
#define ETH_MACADDR1 0x12
#define ETH_MACADDR2 0x34
/minsoc/trunk/sw/eth/eth.c
1,4 → 1,4
#include <board.h>
#include <interconnect.h>
#include <support.h>
#include <or1200.h>
#include <int.h>
29,7 → 29,7
 
int main()
{
uart_init();
uart_init(UART_BASE);
 
int_init();
eth_init();
/minsoc/trunk/sw/eth/Makefile
10,7 → 10,7
VERSION = 0.1
MODE = debug #release|debug
 
INCLUDEDIRS = $(BACKEND_DIR) $(SUPPORT_DIR) $(DRIVERS_DIR)
INCLUDEDIRS = $(SUPPORT_DIR) $(DRIVERS_DIR)
#libsystemc or systemc (system ignores lib at the beginning)
LIBNAMES =
LIBDIRS =
/minsoc/trunk/sw/uart/uart.c
1,4 → 1,4
#include <board.h>
#include <interconnect.h>
#include <support.h>
#include <or1200.h>
#include <int.h>
7,7 → 7,7
 
int main()
{
uart_init();
uart_init(UART_BASE);
 
int_init();
int_add(UART_IRQ, &uart_interrupt, NULL);
/minsoc/trunk/sw/uart/Makefile
10,7 → 10,7
VERSION = 0.1
MODE = debug #release|debug
 
INCLUDEDIRS = $(BACKEND_DIR) $(SUPPORT_DIR) $(DRIVERS_DIR)
INCLUDEDIRS = $(SUPPORT_DIR) $(DRIVERS_DIR)
#libsystemc or systemc (system ignores lib at the beginning)
LIBNAMES =
LIBDIRS =
/minsoc/trunk/sw/jsp/Makefile
0,0 → 1,125
include ../support/Makefile.inc
include $(BACKEND_DIR)/gcc-opt.mk
 
#USER INPUT
SRCS = jsp.c
OR32_TARGET = jsp.hex
TARGET =
TARGETLIB =
MODEL = static #dynamic|static
VERSION = 0.1
MODE = debug #release|debug
 
INCLUDEDIRS = $(SUPPORT_DIR) $(DRIVERS_DIR)
#libsystemc or systemc (system ignores lib at the beginning)
LIBNAMES =
LIBDIRS =
DEPENDDIR = ./depend
 
 
#CONFIGURATION
DEBUGPARAM =
RELEASEPARAM =
 
DEBUGFLAGS = -g -O0
RELEASEFLAGS = -O2 -fomit-frame-pointer
 
CFLAGS = -Wall
CC = or32-elf-gcc
AR = or32-elf-ar
RANLIB = or32-elf-ranlib
 
CFLAGS += $(GCC_OPT)
 
 
#MECHANICS
INCLUDESPATH = $(addprefix -I, $(INCLUDEDIRS))
LIBSPATH = $(addprefix -L, $(LIBDIRS))
LIBSLINKAGE = $(addprefix -l, $(subst lib, , $(LIBNAMES)) )
COMMA = ,
RPATH = $(addprefix -Wl$(COMMA)-R, $(LIBDIRS))
 
OBJS = $(addsuffix .o, $(basename $(SRCS)))
DEPS = $(addprefix $(DEPENDDIR)/, $(addsuffix .d, $(basename $(SRCS) ) ) )
 
STATICLIB = $(addprefix lib, $(addsuffix .a, $(TARGETLIB) ) )
DYNAMICLIB = $(addprefix lib, $(addsuffix .so, $(TARGETLIB) ) )
SONAME = $(addsuffix .$(VERSION), $(DYNAMICLIB))
 
ifeq (debug,$(findstring debug, $(MODE)))
CFLAGS += $(DEBUGFLAGS) $(addprefix -D, $(DEBUGPARAM))
else
CFLAGS += $(RELEASEFLAGS) $(addprefix -D, $(RELEASEPARAM))
endif
 
ifdef TARGETLIB
ifeq (dynamic,$(findstring dynamic, $(MODEL)))
TARGET = $(DYNAMICLIB)
CFLAGS += -fPIC
else
TARGET = $(STATICLIB)
endif
endif
 
 
#MAKEFILE RULES
all: $(TARGET) $(OR32_TARGET)
 
depend: $(DEPS)
 
docs: Doxyfile
doxygen
 
distclean:
make clean
rm -rf $(DEPENDDIR) Doxygen
 
 
-include $(DEPS)
 
 
ifndef TARGETLIB
$(TARGET): $(OBJS)
$(CC) $(LIBSPATH) $(RPATH) -o $@ $^ $(LIBSLINKAGE)
endif
 
 
$(STATICLIB): $(OBJS)
$(AR) cru $@ $^
$(RANLIB) $@
 
$(DYNAMICLIB): $(OBJS)
$(CC) -shared -Wl,-soname,$(SONAME) -o $@ $^
ln -fs $@ $(SONAME)
 
 
%.o: %.c
$(CC) $(CFLAGS) $(INCLUDESPATH) -c $< -o $@
 
 
$(DEPENDDIR)/%.d: %.c
mkdir -p $(DEPENDDIR)
$(CC) $(INCLUDESPATH) -MM -MF $@ $<
 
 
# DO NOT DELETE
 
STEM = $(subst .hex, , $(OR32_TARGET))
BINARY = $(addsuffix .bin, $(STEM) )
EXECUTABLE = $(addsuffix .or32, $(STEM) )
 
$(OR32_TARGET): $(BINARY)
$(BIN2HEX) $? 1 -size_word > $@
 
$(BINARY): $(EXECUTABLE)
$(OR32_TOOL_PREFIX)-objcopy -O binary $? $@
 
#except.o and reset.o should be already inside of $(SUPPORT) (libsupport.a) but for some reason the compiler ignores that fact
#(e.g. or32-elf-objdump -t libsupport.a shows it)
$(EXECUTABLE): $(OBJS) ../support/except.o ../support/reset.o $(SUPPORT) $(DRIVERS)
$(CC) $(CFLAGS) $(GCC_LIB_OPTS) -T $(LINKER_SCRIPT) $^ -o $@
 
clean:
rm -f *.o *~ $(TARGET) $(STATICLIB) $(DYNAMICLIB) $(SONAME) $(OR32_TARGET) $(BINARY) $(EXECUTABLE)
 
#EOF
/minsoc/trunk/sw/jsp/jsp.c
0,0 → 1,21
#include <interconnect.h>
#include <support.h>
#include <or1200.h>
#include <int.h>
 
#include <uart.h>
 
int main()
{
uart_init(JSP_BASE);
 
int_init();
int_add(JSP_IRQ, &uart_interrupt, NULL);
/* We can't use printf because in this simple example
we don't link C library. */
uart_print_str("Hello World.\n");
report(0xdeaddead);
or32_exit(0);
}
minsoc/trunk/sw/jsp/jsp.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc/trunk/sw/drivers/eth.c =================================================================== --- minsoc/trunk/sw/drivers/eth.c (revision 157) +++ minsoc/trunk/sw/drivers/eth.c (revision 158) @@ -1,5 +1,5 @@ -#include #include +#include "interconnect.h" #include "eth.h" int eth_tx_done;
/minsoc/trunk/sw/drivers/uart.h
117,7 → 117,7
#define UART_EFR_ENI 0x10 /* Enhanced Interrupt */
 
 
void uart_init(void);
void uart_init(unsigned long);
void uart_putc(char);
char uart_getc(void);
void uart_print_str(char *);
/minsoc/trunk/sw/drivers/interconnect.h
0,0 → 1,17
#ifndef _INTERCONNECT_H_
#define _INTERCONNECT_H_
 
#define UART_BASE 0x90000000
#define UART_IRQ 2
#define ETH_BASE 0x92000000
#define ETH_IRQ 4
#define I2C_BASE 0x9D000000
#define I2C_IRQ 3
#define CAN_BASE 0x94000000
#define CAN_IRQ 5
#define JSP_BASE 0x9E000000
#define JSP_IRQ 6
 
#define SPI_BASE 0xa0000000
 
#endif
/minsoc/trunk/sw/drivers/can.c
1,5 → 1,5
#include <board.h>
#include <support.h>
#include "interconnect.h"
#include "can.h"
 
int can_rx_done, can_tx_done;
/minsoc/trunk/sw/drivers/uart.c
6,47 → 6,49
 
#define WAIT_FOR_XMITR \
do { \
lsr = REG8(UART_BASE + UART_LSR); \
lsr = REG8(uart_base + UART_LSR); \
} while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
 
#define WAIT_FOR_THRE \
do { \
lsr = REG8(UART_BASE + UART_LSR); \
lsr = REG8(uart_base + UART_LSR); \
} while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
 
#define CHECK_FOR_CHAR (REG8(UART_BASE + UART_LSR) & UART_LSR_DR)
#define CHECK_FOR_CHAR (REG8(uart_base + UART_LSR) & UART_LSR_DR)
 
#define WAIT_FOR_CHAR \
do { \
lsr = REG8(UART_BASE + UART_LSR); \
lsr = REG8(uart_base + UART_LSR); \
} while ((lsr & UART_LSR_DR) != UART_LSR_DR)
 
#define UART_TX_BUFF_LEN 32
#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
 
static unsigned long uart_base = 0;
 
char tx_buff[UART_TX_BUFF_LEN];
volatile int tx_level, rx_level;
 
void uart_init(void)
void uart_init(unsigned long base)
{
int divisor;
 
uart_base = base;
/* Reset receiver and transmiter */
/* Set RX interrupt for each byte */
REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_1;
REG8(uart_base + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_1;
 
/* Enable RX interrupt */
REG8(UART_BASE + UART_IER) = UART_IER_RDI | UART_IER_THRI;
REG8(uart_base + UART_IER) = UART_IER_RDI | UART_IER_THRI;
 
/* Set 8 bit char, 1 stop bit, no parity */
REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
REG8(uart_base + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
 
/* Set baud rate */
divisor = IN_CLK/(16 * UART_BAUD_RATE);
REG8(UART_BASE + UART_LCR) |= UART_LCR_DLAB;
REG8(UART_BASE + UART_DLM) = (divisor >> 8) & 0x000000ff;
REG8(UART_BASE + UART_DLL) = divisor & 0x000000ff;
REG8(UART_BASE + UART_LCR) &= ~(UART_LCR_DLAB);
REG8(uart_base + UART_LCR) |= UART_LCR_DLAB;
REG8(uart_base + UART_DLM) = (divisor >> 8) & 0x000000ff;
REG8(uart_base + UART_DLL) = divisor & 0x000000ff;
REG8(uart_base + UART_LCR) &= ~(UART_LCR_DLAB);
 
return;
}
56,7 → 58,7
unsigned char lsr;
 
WAIT_FOR_THRE;
REG8(UART_BASE + UART_TX) = c;
REG8(uart_base + UART_TX) = c;
WAIT_FOR_XMITR;
}
 
65,7 → 67,7
char uart_getc()
{
char c;
c = REG8(UART_BASE + UART_RX);
c = REG8(uart_base + UART_RX);
return c;
}
 
74,7 → 76,7
{
char lala;
unsigned char interrupt_id;
interrupt_id = REG8(UART_BASE + UART_IIR);
interrupt_id = REG8(uart_base + UART_IIR);
if ( interrupt_id & UART_IIR_RDI )
{
lala = uart_getc();
/minsoc/trunk/sw/drivers/i2c.c
1,5 → 1,5
#include <board.h>
#include <support.h>
#include "interconnect.h"
#include "i2c.h"
 
int i2c_rd_done, i2c_wr_done;
/minsoc/trunk/prj/src/minsoc_top.prj
1,6 → 1,7
PROJECT_DIR=(backend rtl/verilog rtl/verilog/minsoc_startup rtl/verilog/or1200/rtl/verilog rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog rtl/verilog/ethmac/rtl/verilog rtl/verilog/uart16550/rtl/verilog)
PROJECT_SRC=(minsoc_defines.v
timescale.v
interconnect_defines.v
minsoc_top.v
minsoc_tc_top.v
minsoc_onchip_ram.v
/minsoc/trunk/prj/src/adbg_top.prj
1,11 → 1,16
PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
PROJECT_SRC=(adbg_wb_biu.v
adbg_wb_module.v
adbg_or1k_module.v
adbg_wb_defines.v
PROJECT_SRC=(adbg_crc32.v
adbg_defines.v
adbg_crc32.v
adbg_jsp_biu.v
adbg_jsp_module.v
adbg_or1k_biu.v
adbg_or1k_defines.v
adbg_or1k_module.v
adbg_or1k_status_reg.v
adbg_top.v)
adbg_top.v
adbg_wb_biu.v
adbg_wb_defines.v
adbg_wb_module.v
bytefifo.v
syncflop.v
syncreg.v)

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