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URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

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Rev 164 → Rev 165

/minsoc/trunk/backend/nexys2_1200/configure
0,0 → 1,116
#!/bin/bash
 
#new boards have to udpate this
BOARD=nexys2_1200 #this has to have the name of the directory this file is in
DEVICE_PART='XC3S1200E-FG320'
CONSTRAINT_FILE='nexys2_1200.ucf'
#~new boards update
 
#system workings
MINSOC_DIR=`pwd`/../..
BACKEND_DIR=$MINSOC_DIR/backend
SYN_DIR=$MINSOC_DIR/syn
SYNSRC_DIR=$MINSOC_DIR/prj/xilinx
SYNSUPPORT_DIR=$SYN_DIR/buildSupport
MAKEFILE_DIR=$SYN_DIR/xilinx
 
SYN_FILES=(ethmac.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst)
MAKEFILE=Makefile
 
FIND_PART='DEVICE_PART'
FIND_CONSTRAINT='CONSTRAINT_FILE'
 
BOARD_DIR=$BACKEND_DIR/$BOARD
BOARD_FILES=(board.h orp.ld minsoc_defines.v minsoc_bench_defines.v gcc-opt.mk $CONSTRAINT_FILE)
 
in_minsoc=`pwd | grep minsoc/backend/${BOARD}$`
if [ -z $in_minsoc ]
then
echo ""
echo " !!!WARNING!!!"
echo "This script cannot be run if not in a board directory inside minsoc/backend,"
echo "because it relies on the directory structure of the minsoc system."
echo ""
echo "Possibly your minsoc directory is named differently, minsoc_trunk for example."
echo "Its name must be minsoc only."
echo ""
exit 1
fi
 
echo ""
echo "This script sets up the SoC for simulations and synthesis."
echo ""
echo "In order to do so, SoC board's specific files for firmware compilation, "
echo "testbench generation and synthesis are configured."
echo "Firmware and testbench looks for board specific files under $BACKEND_DIR."
echo "Synthesis work under $SYN_DIR."
echo ""
echo ""
 
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory."
echo "__________________________________________________________________________"
echo ""
for file in "${BOARD_FILES[@]}"
do
if [ $file != NONE ]
then
echo "Copying $file, to backend directory..."
cp $BOARD_DIR/$file $BACKEND_DIR
fi
done
echo ""
echo ""
 
echo "Generating project files for simulation and synthesis..."
echo "__________________________________________________________________________"
echo ""
make -C $MINSOC_DIR/prj
echo "Generation complete."
echo ""
echo ""
 
if [ $CONSTRAINT_FILE == 'NONE' ]
then
echo "Skipping synthesis preparation. Standard implementation can only be simulated."
echo ""
echo ""
else
echo "Device part for files under $SYNSRC_DIR will be patched and stored "
echo "temporarily."
echo "Afterwards, they are copied to $SYNSUPPORT_DIR."
echo "__________________________________________________________________________"
echo ""
for file in "${SYN_FILES[@]}"
do
echo "Updating synthesis file, $file..."
echo "Copying $file to synthesis directory..."
echo ""
sed "s/$FIND_PART/$DEVICE_PART/g" $SYNSRC_DIR/$file > TMPFILE
sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYNSUPPORT_DIR/$file
rm TMPFILE
done
 
echo "Updating Makefile file under $MAKEFILE_DIR..."
echo "Copying Makefile to synthesis directory, $SYN_DIR..."
echo ""
sed "s/$FIND_PART/$DEVICE_PART/g" $MAKEFILE_DIR/$MAKEFILE > TMPFILE
sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYN_DIR/$MAKEFILE
rm TMPFILE
cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat
echo ""
echo ""
fi
 
#Precompiling firmwares
echo "Precompiling delivered libraries and firmwares..."
make -C ../../sw/utils
make -C ../../sw/support
make -C ../../sw/drivers
make -C ../../sw/uart
make -C ../../sw/jsp
make -C ../../sw/eth
echo "done."
echo ""
echo ""
 
echo "Configuration done."
minsoc/trunk/backend/nexys2_1200/configure Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc/trunk/backend/nexys2_1200/gcc-opt.mk =================================================================== --- minsoc/trunk/backend/nexys2_1200/gcc-opt.mk (nonexistent) +++ minsoc/trunk/backend/nexys2_1200/gcc-opt.mk (revision 165) @@ -0,0 +1 @@ +GCC_OPT=-mhard-mul -mhard-div -nostdlib Index: minsoc/trunk/backend/nexys2_1200/nexys2_1200.ucf =================================================================== --- minsoc/trunk/backend/nexys2_1200/nexys2_1200.ucf (nonexistent) +++ minsoc/trunk/backend/nexys2_1200/nexys2_1200.ucf (revision 165) @@ -0,0 +1,67 @@ +# +# Soldered 50MHz clock. +# +NET "clk" LOC = "B8"; + +# +# Use button "BTN0" as reset. +# +NET "reset" LOC = "B18" | PULLDOWN ; + +# +# UART serial port (RS232 DCE) - connector DB9 female. +# +NET "uart_srx" LOC = "U6"; +NET "uart_stx" LOC = "P9" | DRIVE = 8 | SLEW = SLOW ; + +# Pins below are probably invalid since they are simply a copy of spartan3e_starter_kit configuration. +# They are still kept here because the signal list is still useful for adaptations. + +########################### +## +## ETH +## +#NET "eth_txd(3)" LOC = "t5"; +#NET "eth_txd(2)" LOC = "r5"; +#NET "eth_txd(1)" LOC = "t15"; +#NET "eth_txd(0)" LOC = "r11"; +# +#NET "eth_tx_en" LOC = "p15"; +#NET "eth_tx_clk" LOC = "t7" | CLOCK_DEDICATED_ROUTE = FALSE; +#NET "eth_tx_er" LOC = "r6"; +# +#NET "eth_rxd(3)" LOC = "v14"; +#NET "eth_rxd(2)" LOC = "u11"; +#NET "eth_rxd(1)" LOC = "t11"; +#NET "eth_rxd(0)" LOC = "v8"; +# +#NET "eth_rx_er" LOC = "u14"; +#NET "eth_rx_dv" LOC = "v2"; +# +#NET "eth_rx_clk" LOC = "v3" | CLOCK_DEDICATED_ROUTE = FALSE; +# +#NET "eth_mdio" LOC = "u5" | PULLUP; +#NET "eth_crs" LOC = "u13"; +#NET "eth_col" LOC = "u6"; +#NET "eth_mdc" LOC = "p9"; +# +#NET "eth_trste" LOC = "p13"; #put it to a non connected FPGA pin (starter kit schematic BANK3) +# +#NET "eth_fds_mdint" LOC = "r13" | PULLUP; #put it to a non connected FPGA pin (starter kit schematic BANK3)(pullup not to generate interrupts) +########################### + +# +# JTAG signals - on J4 6-pin accessory header. +# + +#NET "jtag_tms" LOC = "D7" | PULLDOWN ; +#NET "jtag_tdi" LOC = "C7" | PULLDOWN ; +#NET "jtag_tdo" LOC = "F8" | SLEW = FAST | DRIVE = 8 ; +#NET "jtag_tck" LOC = "E8" | PULLDOWN ; + +#net "jtag_gnd" loc = "k2"; #put it to a non connected FPGA pin (starter kit schematic BANK3) +#net "jtag_vref" loc = "k7"; #put it to a non connected FPGA pin (starter kit schematic BANK3) + +# +# End of file. +#
minsoc/trunk/backend/nexys2_1200/nexys2_1200.ucf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc/trunk/backend/nexys2_1200/minsoc_bench_defines.v =================================================================== --- minsoc/trunk/backend/nexys2_1200/minsoc_bench_defines.v (nonexistent) +++ minsoc/trunk/backend/nexys2_1200/minsoc_bench_defines.v (revision 165) @@ -0,0 +1,29 @@ +//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) +`define GENERIC_FPGA +`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting. +`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) +//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) + +`define FREQ_NUM_FOR_NS 100000000 + +`define FREQ 25000000 +`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) + +`define ETH_PHY_FREQ 25000000 +`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns + +`define UART_BAUDRATE 115200 + +`define VPI_DEBUG + +//`define WAVEFORM_OUTPUT + +//`define START_UP //pass firmware over spi to or1k_startup + +`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware + //only use with the memory model. + //If you use the original memory (`define MEMORY_MODEL + //commented out), comment this too. + +`define TEST_UART +//`define TEST_ETHERNET
minsoc/trunk/backend/nexys2_1200/minsoc_bench_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc/trunk/backend/nexys2_1200/minsoc_defines.v =================================================================== --- minsoc/trunk/backend/nexys2_1200/minsoc_defines.v (nonexistent) +++ minsoc/trunk/backend/nexys2_1200/minsoc_defines.v (revision 165) @@ -0,0 +1,125 @@ +// +// Define FPGA manufacturer +// +//`define GENERIC_FPGA +//`define ALTERA_FPGA +`define XILINX_FPGA + +// +// Define Xilinx FPGA family +// +`ifdef XILINX_FPGA +//`define SPARTAN2 +//`define SPARTAN3 +`define SPARTAN3E +//`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + +// +// Define Altera FPGA family +// +`elsif ALTERA_FPGA +//`define ARRIA_GX +//`define ARRIA_II_GX +//`define CYCLONE_I +//`define CYCLONE_II +`define CYCLONE_III +//`define CYCLONE_III_LS +//`define CYCLONE_IV_E +//`define CYCLONE_IV_GS +//`define MAX_II +//`define MAX_V +//`define MAX3000A +//`define MAX7000AE +//`define MAX7000B +//`define MAX7000S +//`define STRATIX +//`define STRATIX_II +//`define STRATIX_II_GX +//`define STRATIX_III +`endif + +// +// Memory +// +`define MEMORY_ADR_WIDTH 12 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, + //memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, + //2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, + //memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. + +// +// Define division +// +`define CLOCK_DIVISOR 2 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded + //down to an even value in FPGA case, check minsoc_clock_manager + //for allowed divisors. + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION + //INSTEAD. + +// +// Reset polarity +// +//`define NEGATIVE_RESET //rstn +`define POSITIVE_RESET //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +`define JSP +//`define ETHERNET + +// +// Ethernet reset +// +`define ETH_RESET 1'b0 +//`define ETH_RESET 1'b1 + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `undef FPGA_TAP + `undef FPGA_CLOCK_DIVISION + `undef XILINX_FPGA + `undef SPARTAN3E + + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif
minsoc/trunk/backend/nexys2_1200/minsoc_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc/trunk/backend/nexys2_1200/board.h =================================================================== --- minsoc/trunk/backend/nexys2_1200/board.h (nonexistent) +++ minsoc/trunk/backend/nexys2_1200/board.h (revision 165) @@ -0,0 +1,24 @@ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define MC_ENABLED 0 + +#define IC_ENABLE 0 +#define IC_SIZE 8192 +#define DC_ENABLE 0 +#define DC_SIZE 8192 + +#define IN_CLK 25000000 + +#define STACK_SIZE 0x01000 + +#define UART_BAUD_RATE 115200 + +#define ETH_MACADDR0 0x00 +#define ETH_MACADDR1 0x12 +#define ETH_MACADDR2 0x34 +#define ETH_MACADDR3 0x56 +#define ETH_MACADDR4 0x78 +#define ETH_MACADDR5 0x9a + +#endif
minsoc/trunk/backend/nexys2_1200/board.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc/trunk/backend/nexys2_1200/orp.ld =================================================================== --- minsoc/trunk/backend/nexys2_1200/orp.ld (nonexistent) +++ minsoc/trunk/backend/nexys2_1200/orp.ld (revision 165) @@ -0,0 +1,60 @@ +MEMORY + { + reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 + vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 + ram : ORIGIN = 0x00001200, LENGTH = 0x00002E00 /*0x8000 total*/ + } + +SECTIONS +{ + .reset : + { + *(.reset) + } > reset + + + + .vectors : + { + _vec_start = .; + *(.vectors) + _vec_end = .; + } > vectors + + .text : + { + *(.text) + } > ram + + .rodata : + { + *(.rodata) + *(.rodata.*) + } > ram + + .icm : + { + _icm_start = .; + *(.icm) + _icm_end = .; + } > ram + + .data : + { + _dst_beg = .; + *(.data) + _dst_end = .; + } > ram + + .bss : + { + *(.bss) + } > ram + + .stack (NOLOAD) : + { + *(.stack) + _src_addr = .; + } > ram + +}
minsoc/trunk/backend/nexys2_1200/orp.ld Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v =================================================================== --- minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v (revision 164) +++ minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v (revision 165) @@ -16,7 +16,7 @@ `define VPI_DEBUG -//`define VCD_OUTPUT +//`define WAVEFORM_OUTPUT //`define START_UP //pass firmware over spi to or1k_startup

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