URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
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/minsoc/trunk/doc/THESIS.txt
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/minsoc/trunk/doc/FAQ.pdf
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/minsoc/trunk/doc/src/FAQ.odt
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/minsoc/trunk/doc/README.txt
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IMPORTANT: By any arisen problems, doubts or special requirements, take a look into the FAQ.pdf document. It includes possible adaptations you can easily make to the system, most reported problems using MinSoC and the Advanced Debug System, and even some tweak possibilities. If you have a problem which is not described there or you cannot make it work, please start a thread about your problem on OpenRISC forum: http://opencores.org/forum,OpenRISC |
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FINALLY: My system is up and running, what do I do next? The real system documentation is the minsoc.pdf document. It gives a thorough insight into MinSoC, its goals, design and ideas. It helps you to better understand the system and can give you a good idea of what to do next, after your system is up and running. |
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I WANT TO TWEAK THINGS: check THESIS.txt |
/minsoc/trunk/doc/INSTALL.pdf
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/minsoc/trunk/utils/contributions/minsoc_tc_top_B3.v
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/minsoc/trunk/utils/contributions/gpio/sw/Makefile
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/minsoc/trunk/utils/contributions/gpio/sw/old/gpio.c
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/minsoc/trunk/utils/contributions/gpio/sw/old/gpio.h
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/minsoc/trunk/utils/contributions/gpio/sw/gpio.c
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/minsoc/trunk/utils/contributions/gpio/sw/gpio.h
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/minsoc/trunk/utils/contributions/gpio/sw/udelay.c
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/minsoc/trunk/utils/contributions/.directory
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/minsoc/trunk/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_altera.v
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/minsoc/trunk/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v
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/minsoc/trunk/utils/contributions/synthesis_makefile/guideTop.pdf
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Index: minsoc/trunk/utils/contributions/synthesis_makefile/Makefile
===================================================================
--- minsoc/trunk/utils/contributions/synthesis_makefile/Makefile (revision 40)
+++ minsoc/trunk/utils/contributions/synthesis_makefile/Makefile (nonexistent)
@@ -1,107 +0,0 @@
-ROOT = /home/mdhicks2/Desktop/softPatch/baseSoC
-MINSOC = $(ROOT)/minsoc
-MINSOC_RTL = $(MINSOC)/rtl/verilog
-UART_RTL = $(ROOT)/uart16550/rtl/verilog
-ADV_DEBUG_ROOT = $(ROOT)/adv_debug_sys/Hardware
-DEBUG_RTL = $(ADV_DEBUG_ROOT)/adv_dbg_if/rtl/verilog
-XIL_DEBUG_RTL = $(ADV_DEBUG_ROOT)/xilinx_internal_jtag/rtl/verilog
-OR1200_RTL = $(ROOT)/or1200/rtl/verilog
-
-help:
- @echo " all: Synthesize and implement the SoC, then generate a bit stream"
- @echo " soc: Synthesize the SoC"
- @echo " translate: Convert the SoC's ngc file to an ngd file for mapping"
- @echo " map: Express the SoC netlist in the target hardware"
- @echo " par: Place the target hardware, then route the wires"
- @echo " bitgen: Generate a programming file for the target FPGA"
- @echo " clean: Delete all superfluous files generated by Xilinx tools"
- @echo " distclean: Delete all generated files"
- @echo " uart: Synthesize the UART"
- @echo " debug: Synthesize the debug interface"
- @echo " xilDebug: Synthesize the Xilinx JTAG user interface"
- @echo " or1200: Synthesize the OR1200 processor"
-all: minsoc_top.ngc minsoc.ngd minsoc.ncd minsoc_par.ncd minsoc.bit
-soc: minsoc_top.ngc
-translate: minsoc.ngd
-map: minsoc.ncd
-par: minsoc_par.ncd
-bitgen: minsoc.bit
-
-distclean:
- rm -f _xmsgs xst *.{ngc,ncd,ngd,bit,xst,xrpt,srp,lso,log}
-clean:
- rm -f _xmsgs xst *.{xst,xrpt,srp,lso,log}
-
-minsoc_top.ngc: $(MINSOC_RTL)/*.v buildSupport/*.xst buildSupport/*.prj #uart_top.ngc adbg_top.ngc xilinx_internal_jtag.ngc or1200_top.ngc
- xst -ifn "buildSupport/minsoc_top.xst"
- rm -f minsoc_top_xst.xrpt
- rm -f minsoc_top.srp
- rm -f minsoc_top.lso
- rm -rf _xmsgs
- rm -rf xst
-uart: uart_top.ngc
-uart_top.ngc: $(UART_RTL)/*.v buildSupport/uart_top.xst buildSupport/uart_top.prj
- xst -ifn "buildSupport/uart_top.xst"
- rm -f uart_top_xst.xrpt
- rm -f uart_top.srp
- rm -f uart_top.lso
- rm -rf _xmsgs
- rm -rf xst
-debug: adbg_top.ngc
-adbg_top.ngc: $(DEBUG_RTL)/*.v buildSupport/adbg_top.xst buildSupport/adbg_top.prj
- xst -ifn "buildSupport/adbg_top.xst"
- rm -f adbg_top_xst.xrpt
- rm -f adbg_top.srp
- rm -f adbg_top.lso
- rm -rf _xmsgs
- rm -rf xst
-xilDebug: xilinx_internal_jtag.ngc
-xilinx_internal_jtag.ngc: $(XIL_DEBUG_RTL)/*.v buildSupport/xilinx_internal_jtag.xst buildSupport/xilinx_internal_jtag.prj
- xst -ifn "buildSupport/xilinx_internal_jtag.xst"
- rm -f xilinx_internal_jtag_xst.xrpt
- rm -f xilinx_internal_jtag.srp
- rm -f xilinx_internal_jtag.lso
- rm -rf _xmsgs
- rm -rf xst
-or1200: or1200_top.ngc
-or1200_top.ngc: $(OR1200_RTL)/*.v buildSupport/or1200_top.xst buildSupport/or1200_top.prj
- xst -ifn "buildSupport/or1200_top.xst"
- rm -f or1200_top_xst.xrpt
- rm -f or1200_top.srp
- rm -f or1200_top.lso
- rm -rf _xmsgs
- rm -rf xst
-minsoc.ngd: $(MINSOC)/backend/ml509.ucf minsoc_top.ngc
- ngdbuild -p xc5vlx110t-ff1136-3 -uc $(MINSOC)/backend/ml509.ucf -aul -aut minsoc_top.ngc minsoc.ngd
- rm -rf netlist.lst
- rm -rf minsoc.bld
- rm -rf minsoc*.xrpt
- rm -rf xlnx_auto_0_xdb
- rm -rf _xmsgs
-minsoc.ncd : minsoc.ngd
- map -bp -timing -cm speed -equivalent_register_removal on -global_opt speed -logic_opt on -mt 2 -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd
- rm -rf minsoc.map
- rm -rf minsoc.mrp
- rm -rf minsoc.ngm
- rm -rf minsoc.pcf
- rm -rf minsoc.psr
- rm -rf minsoc*.xml
- rm -rf minsoc_top*.xrpt
- rm -rf _xmsgs
-minsoc_par.ncd: minsoc.ncd
- par -mt 4 -ol high -w -xe n minsoc.ncd minsoc_par.ncd
- rm -rf minsoc_par.pad
- rm -rf minsoc_par.par
- rm -rf minsoc_par.ptwx
- rm -rf minsoc_par.unroutes
- rm -rf minsoc_par.xpi
- rm -rf minsoc_par_pad*
- rm -rf minsoc_top*.xrpt
- rm -rf _xmsgs
-minsoc.bit: minsoc_par.ncd
- bitgen -d -w minsoc_par.ncd minsoc.bit
- rm -rf minsoc.bgn
- rm -rf *.xwbt
- rm -rf *.xml
- rm -rf *.log
- rm -rf _xmsgs
Index: minsoc/trunk/backend/ml509.ucf
===================================================================
--- minsoc/trunk/backend/ml509.ucf (revision 40)
+++ minsoc/trunk/backend/ml509.ucf (nonexistent)
@@ -1,45 +0,0 @@
-NET clk LOC="AH15" | PERIOD=10ns | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI
-NET reset LOC="E9" | PULLUP | IOSTANDARD=LVDCI_33; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
-NET uart_srx LOC="AG15" | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI
-NET uart_stx LOC="AG20" | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI
-
-## #------------------------------------------------------------------------------
-## # IO Pad Location Constraints / Properties for Ethernet
-## #------------------------------------------------------------------------------
-
-#NET eth_col LOC = B32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
-#NET eth_crs LOC = E34 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
-#NET eth_rx_dv LOC = E32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
-#NET eth_rx_clk LOC = H17 | IOSTANDARD = LVCMOS25;
-#NET eth_rxd<3> LOC = C32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
-#NET eth_rxd<2> LOC = C33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
-#NET eth_rxd<1> LOC = B33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
-#NET eth_rxd<0> LOC = A33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
-
-#NET eth_rx_er LOC = E33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
-#NET eth_tx_clk LOC = K17 | IOSTANDARD = LVCMOS25;
-#NET eth_trste LOC = J14 | IOSTANDARD = LVCMOS25 | PULLUP | TIG; # PHY_RESET pin on phy
-#NET eth_txd<3> LOC = AH10 | IOSTANDARD = LVDCI_33;
-#NET eth_txd<2> LOC = AH9 | IOSTANDARD = LVDCI_33;
-#NET eth_txd<1> LOC = AE11 | IOSTANDARD = LVDCI_33;
-#NET eth_txd<0> LOC = AF11 | IOSTANDARD = LVDCI_33;
-#NET eth_tx_en LOC = AJ10 | IOSTANDARD = LVDCI_33;
-#NET eth_tx_er LOC = AJ9 | IOSTANDARD = LVDCI_33;
-
-## PHY Serial Management Interface pins
-#NET eth_mdc LOC = H19 | IOSTANDARD = LVCMOS25;
-#NET eth_mdio LOC = H13 | IOSTANDARD = LVCMOS25;
-
-## # Timing Constraints (these are recommended in documentation and
-## # are unaltered except for the TIG)
-#NET "eth_rx_clk_BUFGP" TNM_NET = "RXCLK_GRP";
-#NET "eth_tx_clk_BUFGP" TNM_NET = "TXCLK_GRP";
-#TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;
-#TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;
-
-## # Timing ignores (to specify unconstrained paths)
-#FIXME? NET "*clkgen0/wb_clk_o" TNM_NET = "sys_clk"; # Wishbone clock
-#TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG;
-#TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG;
-#TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG;
-#TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG;