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  • This comparison shows the changes necessary to convert path
    /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit
    from Rev 118 to Rev 124
    Reverse comparison

Rev 118 → Rev 124

/minsoc_bench_defines.v
4,7 → 4,7
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down)
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
 
`define FREQ_NUM_FOR_NS 1000000000
`define FREQ_NUM_FOR_NS 100000000
 
`define FREQ 25000000
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
24,3 → 24,6
//only use with the memory model.
//If you use the original memory (`define MEMORY_MODEL
//commented out), comment this too.
 
`define TEST_UART
//`define TEST_ETHERNET

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