URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/branches/rc-1.0/backend/std
- from Rev 109 to Rev 105
- ↔ Reverse comparison
Rev 109 → Rev 105
/configure
File deleted
configure
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: gcc-opt.mk
===================================================================
--- gcc-opt.mk (revision 109)
+++ gcc-opt.mk (nonexistent)
@@ -1 +0,0 @@
-GCC_OPT=-mhard-mul -mhard-div -nostdlib
Index: minsoc_bench_defines.v
===================================================================
--- minsoc_bench_defines.v (revision 109)
+++ minsoc_bench_defines.v (nonexistent)
@@ -1,26 +0,0 @@
-//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
-`define GENERIC_FPGA
-`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting.
-`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down)
-//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
-
-`define FREQ_NUM_FOR_NS 1000000000
-
-`define FREQ 25000000
-`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
-
-`define ETH_PHY_FREQ 25000000
-`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns
-
-`define UART_BAUDRATE 115200
-
-`define VPI_DEBUG
-
-//`define VCD_OUTPUT
-
-//`define START_UP //pass firmware over spi to or1k_startup
-
-`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware
- //only use with the memory model.
- //If you use the original memory (`define MEMORY_MODEL
- //commented out), comment this too.
minsoc_bench_defines.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: minsoc_defines.v
===================================================================
--- minsoc_defines.v (revision 109)
+++ minsoc_defines.v (nonexistent)
@@ -1,148 +0,0 @@
-//
-// Define FPGA manufacturer
-//
-`define GENERIC_FPGA
-//`define ALTERA_FPGA
-//`define XILINX_FPGA
-
-//
-// Define Xilinx FPGA family
-//
-`ifdef XILINX_FPGA
-//`define SPARTAN2
-//`define SPARTAN3
-//`define SPARTAN3E
-`define SPARTAN3A
-//`define VIRTEX
-//`define VIRTEX2
-//`define VIRTEX4
-//`define VIRTEX5
-
-//
-// Define Altera FPGA family
-//
-`elsif ALTERA_FPGA
-//`define ARRIA_GX
-//`define ARRIA_II_GX
-//`define CYCLONE_I
-//`define CYCLONE_II
-`define CYCLONE_III
-//`define CYCLONE_III_LS
-//`define CYCLONE_IV_E
-//`define CYCLONE_IV_GS
-//`define MAX_II
-//`define MAX_V
-//`define MAX3000A
-//`define MAX7000AE
-//`define MAX7000B
-//`define MAX7000S
-//`define STRATIX
-//`define STRATIX_II
-//`define STRATIX_II_GX
-//`define STRATIX_III
-`endif
-
-//
-// Memory
-//
-`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12,
- //memory is composed by blocks of address width 11
- //Address width of memory -> select memory depth,
- //2 powers MEMORY_ADR_WIDTH defines the memory depth
- //the memory data width is 32 bit,
- //memory amount in Bytes = 4*memory depth
-
-//
-// Memory type (uncomment something if ASIC or generic memory)
-//
-//`define GENERIC_MEMORY
-//`define AVANT_ATP
-//`define VIRAGE_SSP
-//`define VIRTUALSILICON_SSP
-
-
-//
-// TAP selection
-//
-//`define GENERIC_TAP
-`define FPGA_TAP
-
-//
-// Clock Division selection
-//
-//`define NO_CLOCK_DIVISION
-//`define GENERIC_CLOCK_DIVISION
-`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested.
-
-//
-// Define division
-//
-`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded
- //down to an even value in FPGA case, check minsoc_clock_manager
- //for allowed divisors.
- //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION
- //INSTEAD.
-
-//
-// Reset polarity
-//
-`define NEGATIVE_RESET //rstn
-//`define POSITIVE_RESET //rst
-
-//
-// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
-//
-//`define START_UP
-
-//
-// Connected modules
-//
-`define UART
-`define ETHERNET
-
-//
-// Ethernet reset
-//
-`define ETH_RESET 1'b0
-//`define ETH_RESET 1'b1
-
-//
-// Interrupts
-//
-`define APP_INT_RES1 1:0
-`define APP_INT_UART 2
-`define APP_INT_RES2 3
-`define APP_INT_ETH 4
-`define APP_INT_PS2 5
-`define APP_INT_RES3 19:6
-
-//
-// Address map
-//
-`define APP_ADDR_DEC_W 8
-`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00
-`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04
-`define APP_ADDR_DECP_W 4
-`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9
-`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97
-`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92
-`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d
-`define APP_ADDR_UART `APP_ADDR_DEC_W'h90
-`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94
-`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e
-`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f
-
-//
-// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen
-// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set
-//
-`ifdef GENERIC_FPGA
- `undef FPGA_TAP
- `undef FPGA_CLOCK_DIVISION
-
- `define GENERIC_TAP
- `define GENERIC_MEMORY
- `ifndef NO_CLOCK_DIVISION
- `define GENERIC_CLOCK_DIVISION
- `endif
-`endif
minsoc_defines.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: board.h
===================================================================
--- board.h (revision 109)
+++ board.h (nonexistent)
@@ -1,40 +0,0 @@
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-#define MC_ENABLED 0
-
-#define IC_ENABLE 0
-#define IC_SIZE 8192
-#define DC_ENABLE 0
-#define DC_SIZE 8192
-
-
-#define IN_CLK 25000000
-
-
-#define STACK_SIZE 0x01000
-
-#define UART_BAUD_RATE 115200
-
-#define UART_BASE 0x90000000
-#define UART_IRQ 2
-#define ETH_BASE 0x92000000
-#define ETH_IRQ 4
-#define I2C_BASE 0x9D000000
-#define I2C_IRQ 3
-#define CAN_BASE 0x94000000
-#define CAN_IRQ 5
-
-#define MC_BASE_ADDR 0x60000000
-#define SPI_BASE 0xa0000000
-
-#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */
-
-#define ETH_MACADDR0 0x00
-#define ETH_MACADDR1 0x12
-#define ETH_MACADDR2 0x34
-#define ETH_MACADDR3 0x56
-#define ETH_MACADDR4 0x78
-#define ETH_MACADDR5 0x9a
-
-#endif
board.h
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orp.ld
===================================================================
--- orp.ld (revision 109)
+++ orp.ld (nonexistent)
@@ -1,60 +0,0 @@
-MEMORY
- {
- reset : ORIGIN = 0x00000000, LENGTH = 0x00000200
- vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000
- ram : ORIGIN = 0x00001200, LENGTH = 0x00006E00 /*0x8000 total*/
- }
-
-SECTIONS
-{
- .reset :
- {
- *(.reset)
- } > reset
-
-
-
- .vectors :
- {
- _vec_start = .;
- *(.vectors)
- _vec_end = .;
- } > vectors
-
- .text :
- {
- *(.text)
- } > ram
-
- .rodata :
- {
- *(.rodata)
- *(.rodata.*)
- } > ram
-
- .icm :
- {
- _icm_start = .;
- *(.icm)
- _icm_end = .;
- } > ram
-
- .data :
- {
- _dst_beg = .;
- *(.data)
- _dst_end = .;
- } > ram
-
- .bss :
- {
- *(.bss)
- } > ram
-
- .stack (NOLOAD) :
- {
- *(.stack)
- _src_addr = .;
- } > ram
-
-}
orp.ld
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property