OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /minsoc/branches/rc-1.0/bench
    from Rev 145 to Rev 147
    Reverse comparison

Rev 145 → Rev 147

/verilog/minsoc_bench.v
60,6 → 60,7
reg [12*8-1:0] hello;
reg new_line;
reg new_char;
reg flush_line;
`endif
`ifdef ETHERNET
reg [7:0] eth_rx_data [0:1535]; //receive buffer ETH (max packet 1536)
310,7 → 311,7
if ( line[7:0] == "B" )
$display("UART interrupt working.");
else
$display("UART interrupt failed.");
$display("UART interrupt failed. B was expected, %c was received.", line[7:0]);
uart_echo = 1'b1;
 
if ( hello == "Hello World." )
347,9 → 348,9
#((`CLK_PERIOD)/2) clock <= ~clock;
end
 
`ifdef VCD_OUTPUT
`ifdef WAVEFORM_OUTPUT
initial begin
$dumpfile("../results/minsoc_wave.vcd");
$dumpfile("../results/minsoc_wave.lxt");
$dumpvars();
end
`endif
400,6 → 401,7
begin
new_line = 1'b0;
new_char = 1'b0;
flush_line = 1'b0;
end
 
always @ (posedge clock)
411,6 → 413,7
reg [7:0] tx_byte;
begin
new_char = 1'b0;
new_line = 1'b0;
// Wait for start bit
while (uart_stx == 1'b1)
@(uart_stx);
431,16 → 434,19
//$display("* USER UART returned to idle at time %d",$time);
end
// display the char
new_char = 1'b1;
if ( uart_echo )
$write("%c", tx_byte);
if ( new_line )
if ( flush_line ) begin
line = "";
if ( tx_byte == "\n" )
flush_line = 1'b0;
end
if ( tx_byte == "\n" ) begin
new_line = 1'b1;
flush_line = 1'b1;
end
else begin
line = { line[39*8-1:0], tx_byte};
new_line = 1'b0;
new_char = 1'b1;
end
end
endtask

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.