URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/branches/rc-1.0/prj
- from Rev 110 to Rev 113
- ↔ Reverse comparison
Rev 110 → Rev 113
/src/blackboxes/or1200_top.v
38,8 → 38,6
pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o, |
pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o |
|
,sig_tick |
|
); |
|
parameter dw = `OR1200_OPERAND_WIDTH; |
143,10 → 141,5
output pm_wakeup_o; |
output pm_lvolt_o; |
|
// |
// CPU and TT |
// |
output sig_tick; // jb |
|
|
endmodule |
/Makefile
16,7 → 16,7
XILINX_XST_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .xst, $(basename $(PROJECTS)))) |
|
ALTERA_VERILOG_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .vprj, $(basename $(VERILOG_PROJECTS)))) |
ALTERA_VHD_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .vhdprj, $(basename $(VHDL_PROJECTS)))) |
ALTERA_VHDL_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .vhdprj, $(basename $(VHDL_PROJECTS)))) |
|
all: $(SIMULATION_DIR)/minsoc_verilog.src $(SIMULATION_DIR)/minsoc_vhdl.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES) $(ALTERA_VERILOG_PRJ_FILES) $(ALTERA_VHDL_PRJ_FILES) |
|