OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /minsoc/branches/rc-1.0/sim/modelsim
    from Rev 104 to Rev 109
    Reverse comparison

Rev 104 → Rev 109

/compile_design.bat
0,0 → 1,5
@echo off
vlog -incr -work minsoc -f ../../prj/sim/minsoc_verilog.src
::vcom -work minsoc -f ../../prj/sim/minsoc_vhdl.src
echo Finished...
set /p exit=Press ENTER to close this window...
/compile_design.sh
0,0 → 1,4
#!/bin/bash
 
vlog -incr -work minsoc -f ../../prj/sim/minsoc_verilog.src
#vcom -work minsoc -f ../../prj/sim/minsoc_vhdl.src
compile_design.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: run_sim.bat =================================================================== --- run_sim.bat (nonexistent) +++ run_sim.bat (revision 109) @@ -0,0 +1,8 @@ +@echo off +set /p target_firmware=Input the target firmware hex file along with its path. Ex: "..\..\sw\uart\uart-nocache.hex": +if EXIST %target_firmware% ( +vsim -lib minsoc minsoc_bench -pli ../../bench/verilog/vpi/jp-io-vpi.dll +file_name=%target_firmware% +) else ( +echo %target_firmware% could not be found. +set /p exit=Press ENTER to close this window... +) \ No newline at end of file Index: prepare_modelsim.bat =================================================================== --- prepare_modelsim.bat (nonexistent) +++ prepare_modelsim.bat (revision 109) @@ -0,0 +1,5 @@ +@echo off +vlib minsoc +vmap minsoc ./minsoc +echo Finished... +set /p exit=Press ENTER to close this window... \ No newline at end of file Index: prepare_modelsim.sh =================================================================== --- prepare_modelsim.sh (nonexistent) +++ prepare_modelsim.sh (revision 109) @@ -0,0 +1,4 @@ +#!/bin/bash + +vlib minsoc +vmap minsoc ./minsoc
prepare_modelsim.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: run_sim.sh =================================================================== --- run_sim.sh (nonexistent) +++ run_sim.sh (revision 109) @@ -0,0 +1,3 @@ +#!/bin/bash + +vsim -lib minsoc minsoc_bench -pli ../../bench/verilog/vpi/jp-io-vpi.so +file_name=$1
run_sim.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.