Subversion Repositories minsoc

/setup.bat File deleted \ No newline at end of file

setup.bat Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: minsoc_top.qsf =================================================================== --- minsoc_top.qsf (revision 109) +++ minsoc_top.qsf (nonexistent) @@ -1,37 +0,0 @@ -set_global_assignment -name FAMILY "FAMILY_PART" -set_global_assignment -name DEVICE DEVICE_PART -set_global_assignment -name TOP_LEVEL_ENTITY minsoc_top -#set_global_assignment -name ORIGINAL_QUARTUS_VERSION SW_VERSION -#set_global_assignment -name LAST_QUARTUS_VERSION SW_VERSION -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2 -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" -#set_global_assignment -name MISC_FILE ./minsoc_top.dpf -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "BSDL (Boundary Scan)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT BSDL -section_id eda_board_design_boundary_scan -set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION POST_CONFIG -section_id eda_board_design_boundary_scan -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" -set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_timing_analysis -set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_timing_analysis -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_timing_analysis -set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL OFF -section_id eda_timing_analysis - -set_global_assignment -name SDC_FILE minsoc_top.sdc -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top - Index: Makefile =================================================================== --- Makefile (revision 109) +++ Makefile (nonexistent) @@ -1,60 +0,0 @@ -MINSOC = .. -MINSOC_DEFINES = ${MINSOC}/backend -MINSOC_RTL = ${MINSOC}/rtl/verilog -MINSOC_STARTUP_RTL = ${MINSOC_RTL}/minsoc_startup -UART_RTL = ${MINSOC_RTL}/uart16550/rtl/verilog -ADV_DEBUG_ROOT = ${MINSOC_RTL}/adv_debug_sys/Hardware -DEBUG_RTL = ${ADV_DEBUG_ROOT}/adv_dbg_if/rtl/verilog -OR1200_RTL = ${MINSOC_RTL}/or1200/rtl/verilog -ETH_RTL = ${MINSOC_RTL}/ethmac/rtl/verilog -BUILD_SUPPORT = $(MINSOC)/syn/buildSupport -PROJECT_DIR = $(MINSOC)/prj/altera -QSF_FILE = $(BUILD_SUPPORT)/minsoc_top -help: - @echo " all: Synthesize and implement the SoC, then generate a bit stream" - @echo "" - @echo " bitgen: Generate a programming file for the target FPGA" - @echo " map: Express the SoC netlist in the target hardware" - @echo " fit: Place the target hardware, then route the wires" - @echo " sta: Perfom a timming analysis" - @echo " eda: Generate a netlist of the hardware" - @echo " config: Load the bitstream into the device using ALTERA USB Blaster and JTAG configuration" - @echo "" - @echo " clean: Delete all superfluous files generated by Altera tools" - @echo " distclean: Delete all generated files" - -all: bitgen eda sta -map: $(BUILD_SUPPORT)/minsoc_top.map.summary -fit: $(BUILD_SUPPORT)/minsoc_top.fit.summary -bitgen: minsoc_top.sof -eda: $(BUILD_SUPPORT)/minsoc_top.eda.summary -sta: $(BUILD_SUPPORT)/minsoc_top.sta.summary - -#minsoc_top.map.summary: ${MINSOC_RTL}/*.v $(UART_RTL)/*.v $(ADV_DEBUG_ROOT)/*.v $(DEBUG_RTL)/*.v $(OR1200_RTL)/*.v $(ETH_RTL)/*.v ${MINSOC_DEFINES}/minsoc_defines.v minsoc_top.qsf -$(BUILD_SUPPORT)/minsoc_top.map.summary: ${MINSOC_DEFINES}/minsoc_defines.v $(BUILD_SUPPORT)/minsoc_top.qsf - - quartus_map $(QSF_FILE) --write_settings_files=off - -$(BUILD_SUPPORT)/minsoc_top.fit.summary: $(BUILD_SUPPORT)/minsoc_top.map.summary - quartus_fit $(QSF_FILE) --write_Settings_files=off --pack_register=minimize_area - -minsoc_top.sof: $(BUILD_SUPPORT)/minsoc_top.fit.summary - quartus_asm $(QSF_FILE) - mv $(BUILD_SUPPORT)/*.sof . - -$(BUILD_SUPPORT)/minsoc_top.sta.summary: $(BUILD_SUPPORT)/minsoc_top.fit.summary - quartus_sta $(QSF_FILE) - -$(BUILD_SUPPORT)/minsoc_top.eda.summary: $(BUILD_SUPPORT)/minsoc_top.fit.summary - quartus_eda $(QSF_FILE) --write_settings_files=off - -config: minsoc_top.sof - quartus_pgm -c USB-Blaster -m jtag -o "p;minsoc_top.sof" - -distclean: - $(RM) *.sof - make clean - -clean: - $(RM) $(BUILD_SUPPORT)/*.rpt $(BUILD_SUPPORT)/*.summary $(BUILD_SUPPORT)/*.jdi $(BUILD_SUPPORT)/*.smsg $(BUILD_SUPPORT)/*.pin $(BUILD_SUPPORT)/*.qpf - $(RM) -r $(BUILD_SUPPORT)/db $(BUILD_SUPPORT)/incremental_db