URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/branches/rc-1.0/utils/contributions
- from Rev 109 to Rev 64
- ↔ Reverse comparison
Rev 109 → Rev 64
/gpio/todo.txt
File deleted
\ No newline at end of file
/gpio/rtl/gpio_defines.v
File deleted
/gpio/rtl/gpio_top.v
File deleted
/gpio/rtl/minsoc_top.ucf
File deleted
/gpio/rtl/minsoc_defines.v
File deleted
/gpio/rtl/minsoc_spartan_3a_starter_kit_ios.v
File deleted
/gpio/rtl/minsoc_top.v
File deleted
/gpio/sw/gpio.c
File deleted
/gpio/sw/udelay.c
File deleted
/gpio/sw/gpio.h
File deleted
/gpio/sw/Makefile
File deleted
/gpio/sw/old/gpio.c
File deleted
/gpio/sw/old/udelay.c
File deleted
/gpio/sw/old/gpio.h
File deleted
/gpio/sw/old/Makefile
File deleted
/setup/beautify.sh
File deleted
/setup/TODO.txt
File deleted
/setup/minsoc-install.sh
File deleted
setup/minsoc-install.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: setup/toolchain-install.sh
===================================================================
--- setup/toolchain-install.sh (revision 109)
+++ setup/toolchain-install.sh (nonexistent)
@@ -1,51 +0,0 @@
-#!/bin/bash
-# Xanthopoulos Constantinos
-# Installing OR GNU Toolchain.
-# Only tested in Debian Squeeze.
-
-
-# ===== CONFIGURATIONS =====
-# ==========================
-
-# Where will I put the binaries?
-# ex. /opt/openrisc/bin
-DIR_TO_INSTALL="";
-
-# Debian's kernel architecture {32,64}
-# ex. KERNEL_ARCH="32"
-KERNEL_ARCH=""
-
-# ===== SCRIPT ======
-# ===================
-export DEBUG=0;
-. conxshlib.sh
-
-if [ `whoami` == "root" ];
-then
- errormsg "You shouldn't be root for this script to run.";
-fi;
-
-if [ ! -d $DIR_TO_INSTALL ]
-then
- errormsg "Directory doesn't exist. Please create it";
-fi;
-
-execcmd "Change permissions" "chmod 777 $DIR_TO_INSTALL";
-
-cd $DIR_TO_INSTALL;
-
-if [ $KERNEL_ARCH == "32" ];
-then
- execcmd "Download toolchain (it may take a while)" "wget ftp://ocuser:oc@opencores.org/toolchain/or32-elf-linux-x86.tar.bz2";
-elif [ $KERNEL_ARCH == "64"];
-then
- execcmd "Download toolchain (it may take a while)" "wget ftp://ocuser:oc@opencores.org/toolchain/or32-elf-linux-x86_64.tar.bz2";
-else
- errormsg "Not a correct architecture. Check Configurations";
-fi
-
-execcmd "Un-tar" "tar xf *bz2";
-
-execcmd "Adding toolchain to PATH" "echo \"PATH=\\\$PATH:$DIR_TO_INSTALL/or32-elf/bin/\" >> /home/$(whoami)/.bashrc;";
-
-cecho "Install completed"
setup/toolchain-install.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: initialized_onchip_ram/minsoc_onchip_ram_top_altera.v
===================================================================
--- initialized_onchip_ram/minsoc_onchip_ram_top_altera.v (revision 109)
+++ initialized_onchip_ram/minsoc_onchip_ram_top_altera.v (nonexistent)
@@ -1,310 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Generic Wishbone controller for ////
-//// Single-Port Synchronous RAM ////
-//// ////
-//// This file is part of memory library available from ////
-//// http://www.opencores.org/cvsweb.shtml/minsoc/ ////
-//// ////
-//// Description ////
-//// This Wishbone controller connects to the wrapper of ////
-//// the single-port synchronous memory interface. ////
-//// Besides universal memory due to onchip_ram it provides a ////
-//// generic way to set the depth of the memory. ////
-//// ////
-//// To Do: ////
-//// ////
-//// Author(s): ////
-//// - Raul Fajardo, rfajardo@gmail.com ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.gnu.org/licenses/lgpl.html ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// Revision History
-//
-// Revision 1.1 2009/10/02 16:49 fajardo
-// Not using the oe signal (output enable) from
-// memories, instead multiplexing the outputs
-// between the different instantiated blocks
-//
-//
-// Revision 1.0 2009/08/18 15:15:00 fajardo
-// Created interface and tested
-//
-`include "minsoc_defines.v"
-
-`define mem_init_file "uart-nocache.mif" //specific memory initalization file name, which can be intel hex(.hex) or Altera mif file
- //if no initalization file used, give a name of "UNUSED"
-
-module minsoc_onchip_ram_top (
- wb_clk_i, wb_rst_i,
-
- wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
- wb_stb_i, wb_ack_o, wb_err_o
-);
-
-//
-// Parameters
-//
-parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12
-localparam aw_int = 11; //11 = 2048
-localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data
-
-//
-// I/O Ports
-//
-input wb_clk_i;
-input wb_rst_i;
-
-//
-// WB slave i/f
-//
-input [31:0] wb_dat_i;
-output [31:0] wb_dat_o;
-input [31:0] wb_adr_i;
-input [3:0] wb_sel_i;
-input wb_we_i;
-input wb_cyc_i;
-input wb_stb_i;
-output wb_ack_o;
-output wb_err_o;
-
-//
-// Internal regs and wires
-//
-wire we;
-wire [3:0] be_i;
-wire [31:0] wb_dat_o;
-reg ack_we;
-reg ack_re;
-//
-// Aliases and simple assignments
-//
-assign wb_ack_o = ack_re | ack_we;
-assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored)
-assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]);
-assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i;
-
-//
-// Write acknowledge
-//
-always @ (negedge wb_clk_i or posedge wb_rst_i)
-begin
-if (wb_rst_i)
- ack_we <= 1'b0;
- else
- if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
- ack_we <= #1 1'b1;
- else
- ack_we <= #1 1'b0;
-end
-
-//
-// read acknowledge
-//
-always @ (posedge wb_clk_i or posedge wb_rst_i)
-begin
- if (wb_rst_i)
- ack_re <= 1'b0;
- else
- if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re)
- ack_re <= #1 1'b1;
- else
- ack_re <= #1 1'b0;
-end
-
-`ifdef ALTERA_FPGA //only for altera memory initialization
-
-//2^adr_width x 32bit single-port ram.
-altsyncram altsyncram_component (
- .wren_a (we),
- .clock0 (wb_clk_i),
- .byteena_a (be_i),
- .address_a (wb_adr_i[adr_width+1:2]),
- .data_a (wb_dat_i),
- .q_a (wb_dat_o),
- .aclr0 (1'b0),
- .aclr1 (1'b0),
- .address_b (1'b1),
- .addressstall_a (1'b0),
- .addressstall_b (1'b0),
- .byteena_b (1'b1),
- .clock1 (1'b1),
- .clocken0 (1'b1),
- .clocken1 (1'b1),
- .clocken2 (1'b1),
- .clocken3 (1'b1),
- .data_b (1'b1),
- .eccstatus (),
- .q_b (),
- .rden_a (1'b1),
- .rden_b (1'b1),
- .wren_b (1'b0));
- defparam
- altsyncram_component.clock_enable_input_a = "BYPASS",
- altsyncram_component.clock_enable_output_a = "BYPASS",
- altsyncram_component.init_file = `mem_init_file,
- altsyncram_component.intended_device_family = "Stratix III",
- altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
- altsyncram_component.lpm_type = "altsyncram",
- altsyncram_component.operation_mode = "SINGLE_PORT",
- altsyncram_component.outdata_aclr_a = "NONE",
- altsyncram_component.outdata_reg_a = "UNREGISTERED",
- altsyncram_component.power_up_uninitialized = "FALSE",
- altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
- altsyncram_component.numwords_a = (1<>(j+1)); k=k+1) begin : MUX
- if (j==0) begin
- mux2 #
- (
- .dw(32)
- )
- mux_int(
- .sel( wb_adr_i[aw_int+2+j] ),
- .in1( int_dat_o[k*2] ),
- .in2( int_dat_o[k*2+1] ),
- .out( mux_out[k] )
- );
- end
- else begin
- mux2 #
- (
- .dw(32)
- )
- mux_int(
- .sel( wb_adr_i[aw_int+2+j] ),
- .in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ),
- .in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ),
- .out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] )
- );
- end
- end
- end
-endgenerate
-
-//last output = total output
-assign wb_dat_o = mux_out[mux_out_nr-1];
-
-//(mux_in_nr-(mux_in_nr>>j)):
-//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x
-//so, with this expression I'm evaluating how many times the internal loop has been run
-
-wire [blocks-1:0] bank;
-
-generate
-genvar i;
- for (i=0; i < blocks; i=i+1) begin : MEM
-
- assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i;
-
- //BANK0
- minsoc_onchip_ram block_ram_0 (
- .clk(wb_clk_i),
- .rst(wb_rst_i),
- .addr(wb_adr_i[aw_int+1:2]),
- .di(wb_dat_i[7:0]),
- .doq(int_dat_o[i][7:0]),
- .we(we & bank[i]),
- .oe(1'b1),
- .ce(be_i[0])
- );
-
-
- minsoc_onchip_ram block_ram_1 (
- .clk(wb_clk_i),
- .rst(wb_rst_i),
- .addr(wb_adr_i[aw_int+1:2]),
- .di(wb_dat_i[15:8]),
- .doq(int_dat_o[i][15:8]),
- .we(we & bank[i]),
- .oe(1'b1),
- .ce(be_i[1])
- );
-
- minsoc_onchip_ram block_ram_2 (
- .clk(wb_clk_i),
- .rst(wb_rst_i),
- .addr(wb_adr_i[aw_int+1:2]),
- .di(wb_dat_i[23:16]),
- .doq(int_dat_o[i][23:16]),
- .we(we & bank[i]),
- .oe(1'b1),
- .ce(be_i[2])
- );
-
- minsoc_onchip_ram block_ram_3 (
- .clk(wb_clk_i),
- .rst(wb_rst_i),
- .addr(wb_adr_i[aw_int+1:2]),
- .di(wb_dat_i[31:24]),
- .doq(int_dat_o[i][31:24]),
- .we(we & bank[i]),
- .oe(1'b1),
- .ce(be_i[3])
- );
-
- end
-endgenerate
-`endif
-
-endmodule
-
-module mux2(sel,in1,in2,out);
-
-parameter dw = 32;
-
-input sel;
-input [dw-1:0] in1, in2;
-output reg [dw-1:0] out;
-
-always @ (sel or in1 or in2)
-begin
- case (sel)
- 1'b0: out = in1;
- 1'b1: out = in2;
- endcase
-end
-
-endmodule
Index: initialized_onchip_ram/bin2init.py
===================================================================
--- initialized_onchip_ram/bin2init.py (revision 109)
+++ initialized_onchip_ram/bin2init.py (nonexistent)
@@ -1,212 +0,0 @@
-"""
-*****************************************************************************
- *
- H E A D E R I N F O R M A T I O N *
- *
-*****************************************************************************
-Project Name : SysPy (System Python)
- http://cgi.di.uoa.gr/~evlog/syspy.html
-
-File Name : bin2init.py
-
-Created by : Evangelos Logaras
-
-
-*****************************************************************************
- *
- C O P Y R I G H T N O T I C E *
- *
-*****************************************************************************
-
- This library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation;
- version 2.1 of the License, a copy of which is available from
- http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt.
-
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with this library; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-
-
-*****************************************************************************
- *
- D E S C R I P T I O N *
- *
-*****************************************************************************
-
- Generates block_ram.init file from binary images. Binary images are first converted in hex files
- using bin2hex.c file, provided with the ORPSoC v2 project. bin2hex executable must exist in the same folder with this script.
-
- Currently init file is generated for Xilinx's RAMB16_S9 BRAMs
-
- Usage: python bin2init.py (Python 2.6)
-"""
-
-import commands
-import sys
-
-
-# Python's variable declarations
-#----------------------------------------------------------------------------------------------------------------------------------
-y = ' '
-mem_arr = []
-block_ram_num = 4
-block0 = []
-block1 = []
-block2 = []
-block3 = []
-block_ram = [block3, block2, block1, block0]
-init_arr = []
-mem_size2 = 8192
-mem_count = 0
-bram_count = -1
-init_count = -1
-hex_count = 0
-zero_pad = ''
-filename = ''
-#----------------------------------------------------------------------------------------------------------------------------------
-
-# Exceptions' class
-#----------------------------------------------------------------------------------------------------------------------------------
-class MyExceptions(Exception):
- def __init__(self, value):
- self.value = value
- def __str__(self):
- return repr(self.value)
-#----------------------------------------------------------------------------------------------------------------------------------
-
-# Raising exception if a *.bin file is not provided as an argument
-#----------------------------------------------------------------------------------------------------------------------------------
-filename = sys.argv[len(sys.argv) - 1]
-
-if (filename.find(".bin") == -1):
- raise MyExceptions("*.bin file required")
-#----------------------------------------------------------------------------------------------------------------------------------
-
-i = filename.find(".bin")
-
-filename = filename[:i]
-
-# Deleting old *.hex and *.bin files
-#----------------------------------------------------------------------------------------------------------------------------------
-commands.getoutput("rm " + filename + ".hex")
-commands.getoutput("rm " + filename + ".init")
-#----------------------------------------------------------------------------------------------------------------------------------
-
-## Calling bin2hex executable to convert *.bin file to *.hex
-commands.getoutput("./bin2hex " + filename + ".bin 4 > "+ filename + ".hex")
-
-# Opening the *.hex and the *.init file
-#----------------------------------------------------------------------------------------------------------------------------------
-hexFile = open(filename + ".hex", 'r')
-initFile = open(filename + ".init", 'w')
-#----------------------------------------------------------------------------------------------------------------------------------
-
-# Reading the *.hex file and appending its contents to mem_arr[]
-#----------------------------------------------------------------------------------------------------------------------------------
-y = ' '
-hex_count = 0
-while(y):
- hex_count = hex_count + 1
- if (hex_count == 127):
- mem_arr.append("00000000")
-
- y = hexFile.readline()
- mem_arr.append(y)
-#----------------------------------------------------------------------------------------------------------------------------------
-
-# Reading mem_arr[] and creating the contents of BRAMs
-#----------------------------------------------------------------------------------------------------------------------------------
-for i in range(len(mem_arr)):
- bram_count = bram_count + 1
- if (bram_count < 32):
- block_ram[0].append(mem_arr[i][6:8])
- block_ram[1].append(mem_arr[i][4:6])
- block_ram[2].append(mem_arr[i][2:4])
- block_ram[3].append(mem_arr[i][0:2])
-
- elif (bram_count >= 32):
- bram_count = 0
-
- init_count = init_count + 1
-
- if (init_count >= 64):
- init_count = 0
- mem_count = mem_count + 1
-
- hex_init_count = str(hex(init_count))
- hex_init_count = hex_init_count[2:]
- hex_init_count = hex_init_count.upper()
- if (init_count < 16):
- hex_init_count = '0' + hex_init_count
-
-
- for j in range((block_ram_num - 1), -1, -1):
- if (j == (block_ram_num - 1)):
- init_arr.append(";\ndefparam MEM[" + str(mem_count) + "].block_ram_" + str(j) + ".INIT_" + hex_init_count + " = 256'h")
- block_ram[j].reverse()
- for k in range(len(block_ram[j])):
- init_arr.append(block_ram[j][k].replace("\n", ''))
- else:
- init_arr.append(";\ndefparam MEM[" + str(mem_count) + "].block_ram_" + str(j) + ".INIT_" + hex_init_count + " = 256'h")
- block_ram[j].reverse()
- for k in range(len(block_ram[j])):
- init_arr.append(block_ram[j][k].replace("\n", ''))
-
- block_ram[0] = []
- block_ram[1] = []
- block_ram[2] = []
- block_ram[3] = []
-
- block_ram[0].append(mem_arr[i][6:8])
- block_ram[1].append(mem_arr[i][4:6])
- block_ram[2].append(mem_arr[i][2:4])
- block_ram[3].append(mem_arr[i][0:2])
-
-
-if (bram_count != -1):
- init_count = init_count + 1
- hex_init_count = str(hex(init_count))
- hex_init_count = hex_init_count[2:]
- hex_init_count = hex_init_count.upper()
- if (init_count < 16):
- hex_init_count = '0' + hex_init_count
-
- if (init_count == 0):
- for j in range(64 - 2 * bram_count):
- zero_pad = zero_pad + '0'
- else:
- for j in range(64 - 2 * bram_count):
- zero_pad = zero_pad + '0'
-
- for j in range((block_ram_num - 1), -1, -1):
- init_arr.append(";\ndefparam MEM[" + str(mem_count) + "].block_ram_" + str(j) + ".INIT_" + hex_init_count + " = 256'h")
- block_ram[j].reverse()
- init_arr.append(zero_pad)
- for k in range(len(block_ram[j])):
- init_arr.append(block_ram[j][k].replace("\n", ''))
-
-init_arr.append(';')
-#----------------------------------------------------------------------------------------------------------------------------------
-
-# Writing BRAMs contetns to *.init file
-#----------------------------------------------------------------------------------------------------------------------------------
-i = init_arr[0].find(";/n")
-
-init_arr[0] = init_arr[0][i + 2:]
-
-for i in range(len(init_arr)):
- initFile.write(init_arr[i])
-#----------------------------------------------------------------------------------------------------------------------------------
-
-# Closing the *.hex and the *.init file
-#----------------------------------------------------------------------------------------------------------------------------------
-hexFile.close()
-initFile.close()
-#----------------------------------------------------------------------------------------------------------------------------------
Index: initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v
===================================================================
--- initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v (revision 109)
+++ initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v (nonexistent)
@@ -1,312 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Generic Wishbone controller for ////
-//// Single-Port Synchronous RAM ////
-//// ////
-//// This file is part of memory library available from ////
-//// http://www.opencores.org/cvsweb.shtml/minsoc/ ////
-//// ////
-//// Description ////
-//// This Wishbone controller connects to the wrapper of ////
-//// the single-port synchronous memory interface. ////
-//// Besides universal memory due to onchip_ram it provides a ////
-//// generic way to set the depth of the memory. ////
-//// ////
-//// To Do: ////
-//// ////
-//// Author(s): ////
-//// - Raul Fajardo, rfajardo@gmail.com ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.gnu.org/licenses/lgpl.html ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// Revision History
-//
-// Revision 1.1 2009/10/02 16:49 fajardo
-// Not using the oe signal (output enable) from
-// memories, instead multiplexing the outputs
-// between the different instantiated blocks
-//
-//
-// Revision 1.0 2009/08/18 15:15:00 fajardo
-// Created interface and tested
-//
-`include "minsoc_defines.v"
-
-module minsoc_onchip_ram_top (
- wb_clk_i, wb_rst_i,
-
- wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
- wb_stb_i, wb_ack_o, wb_err_o
-);
-
-//
-// Parameters
-//
-parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12
-localparam aw_int = 11; //11 = 2048
-localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data
-
-//
-// I/O Ports
-//
-input wb_clk_i;
-input wb_rst_i;
-
-//
-// WB slave i/f
-//
-input [31:0] wb_dat_i;
-output [31:0] wb_dat_o;
-input [31:0] wb_adr_i;
-input [3:0] wb_sel_i;
-input wb_we_i;
-input wb_cyc_i;
-input wb_stb_i;
-output wb_ack_o;
-output wb_err_o;
-
-//
-// Internal regs and wires
-//
-wire we;
-wire [3:0] be_i;
-wire [31:0] wb_dat_o;
-reg ack_we;
-reg ack_re;
-//
-// Aliases and simple assignments
-//
-assign wb_ack_o = ack_re | ack_we;
-assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored)
-assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]);
-assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i;
-
-//
-// Write acknowledge
-//
-always @ (negedge wb_clk_i or posedge wb_rst_i)
-begin
-if (wb_rst_i)
- ack_we <= 1'b0;
- else
- if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
- ack_we <= #1 1'b1;
- else
- ack_we <= #1 1'b0;
-end
-
-//
-// read acknowledge
-//
-always @ (posedge wb_clk_i or posedge wb_rst_i)
-begin
- if (wb_rst_i)
- ack_re <= 1'b0;
- else
- if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re)
- ack_re <= #1 1'b1;
- else
- ack_re <= #1 1'b0;
-end
-
-//Generic (multiple inputs x 1 output) MUX
-localparam mux_in_nr = blocks;
-localparam slices = adr_width-aw_int;
-localparam mux_out_nr = blocks-1;
-
-wire [31:0] int_dat_o[0:mux_in_nr-1];
-wire [31:0] mux_out[0:mux_out_nr-1];
-
-generate
-genvar j, k;
- for (j=0; j>(j+1)); k=k+1) begin : MUX
- if (j==0) begin
- mux21 #
- (
- .dw(32)
- )
- mux_int(
- .sel( wb_adr_i[aw_int+2+j] ),
- .in1( int_dat_o[k*2] ),
- .in2( int_dat_o[k*2+1] ),
- .out( mux_out[k] )
- );
- end
- else begin
- mux21 #
- (
- .dw(32)
- )
- mux_int(
- .sel( wb_adr_i[aw_int+2+j] ),
- .in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ),
- .in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ),
- .out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] )
- );
- end
- end
- end
-endgenerate
-
-//last output = total output
-assign wb_dat_o = mux_out[mux_out_nr-1];
-
-//(mux_in_nr-(mux_in_nr>>j)):
-//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x
-//so, with this expression I'm evaluating how many times the internal loop has been run
-
-wire [blocks-1:0] bank;
-
-generate
-genvar i;
- for (i=0; i < blocks; i=i+1) begin : MEM
-
- assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i;
-
- //BANK0
-/* minsoc_onchip_ram block_ram_0 (
- .clk(wb_clk_i),
- .rst(wb_rst_i),
- .addr(wb_adr_i[aw_int+1:2]),
- .di(wb_dat_i[7:0]),
- .doq(int_dat_o[i][7:0]),
- .we(we & bank[i]),
- .oe(1'b1),
- .ce(be_i[0])
- );
-*/
- RAMB16_S9 block_ram_0(
- .CLK(wb_clk_i),
- .SSR(wb_rst_i),
- .ADDR(wb_adr_i[aw_int+1:2]),
- .DI(wb_dat_i[7:0]),
- .DIP(1'b0),
- .EN(be_i[0]),
- .WE(we & bank[i]),
- .DO(int_dat_o[i][7:0]),
- .DOP()
- );
-
-/*
- minsoc_onchip_ram block_ram_1 (
- .clk(wb_clk_i),
- .rst(wb_rst_i),
- .addr(wb_adr_i[aw_int+1:2]),
- .di(wb_dat_i[15:8]),
- .doq(int_dat_o[i][15:8]),
- .we(we & bank[i]),
- .oe(1'b1),
- .ce(be_i[1])
- );
-*/
- RAMB16_S9 block_ram_1(
- .CLK(wb_clk_i),
- .SSR(wb_rst_i),
- .ADDR(wb_adr_i[aw_int+1:2]),
- .DI(wb_dat_i[15:8]),
- .DIP(1'b0),
- .EN(be_i[1]),
- .WE(we & bank[i]),
- .DO(int_dat_o[i][15:8]),
- .DOP()
- );
-/*
- minsoc_onchip_ram block_ram_2 (
- .clk(wb_clk_i),
- .rst(wb_rst_i),
- .addr(wb_adr_i[aw_int+1:2]),
- .di(wb_dat_i[23:16]),
- .doq(int_dat_o[i][23:16]),
- .we(we & bank[i]),
- .oe(1'b1),
- .ce(be_i[2])
- );
-*/
- RAMB16_S9 block_ram_2(
- .CLK(wb_clk_i),
- .SSR(wb_rst_i),
- .ADDR(wb_adr_i[aw_int+1:2]),
- .DI(wb_dat_i[23:16]),
- .DIP(1'b0),
- .EN(be_i[2]),
- .WE(we & bank[i]),
- .DO(int_dat_o[i][23:16]),
- .DOP()
- );
-
-/*
- minsoc_onchip_ram block_ram_3 (
- .clk(wb_clk_i),
- .rst(wb_rst_i),
- .addr(wb_adr_i[aw_int+1:2]),
- .di(wb_dat_i[31:24]),
- .doq(int_dat_o[i][31:24]),
- .we(we & bank[i]),
- .oe(1'b1),
- .ce(be_i[3])
- );
-*/
- RAMB16_S9 block_ram_3(
- .CLK(wb_clk_i),
- .SSR(wb_rst_i),
- .ADDR(wb_adr_i[aw_int+1:2]),
- .DI(wb_dat_i[31:24]),
- .DIP(1'b0),
- .EN(be_i[3]),
- .WE(we & bank[i]),
- .DO(int_dat_o[i][31:24]),
- .DOP()
- );
-
- end
-endgenerate
-
-`ifdef BLOCK_RAM_INIT
-`include "block_ram.init"
-`endif
-
-endmodule
-
-module mux21(sel,in1,in2,out);
-
-parameter dw = 32;
-
-input sel;
-input [dw-1:0] in1, in2;
-output reg [dw-1:0] out;
-
-always @ (sel or in1 or in2)
-begin
- case (sel)
- 1'b0: out = in1;
- 1'b1: out = in2;
- endcase
-end
-
-endmodule
Index: synthesis_makefile/guideTop.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: synthesis_makefile/guideTop.pdf
===================================================================
--- synthesis_makefile/guideTop.pdf (revision 109)
+++ synthesis_makefile/guideTop.pdf (nonexistent)
synthesis_makefile/guideTop.pdf
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: synthesis_makefile/Makefile
===================================================================
--- synthesis_makefile/Makefile (revision 109)
+++ synthesis_makefile/Makefile (nonexistent)
@@ -1,107 +0,0 @@
-ROOT = /home/mdhicks2/Desktop/softPatch/baseSoC
-MINSOC = $(ROOT)/minsoc
-MINSOC_RTL = $(MINSOC)/rtl/verilog
-UART_RTL = $(ROOT)/uart16550/rtl/verilog
-ADV_DEBUG_ROOT = $(ROOT)/adv_debug_sys/Hardware
-DEBUG_RTL = $(ADV_DEBUG_ROOT)/adv_dbg_if/rtl/verilog
-XIL_DEBUG_RTL = $(ADV_DEBUG_ROOT)/xilinx_internal_jtag/rtl/verilog
-OR1200_RTL = $(ROOT)/or1200/rtl/verilog
-
-help:
- @echo " all: Synthesize and implement the SoC, then generate a bit stream"
- @echo " soc: Synthesize the SoC"
- @echo " translate: Convert the SoC's ngc file to an ngd file for mapping"
- @echo " map: Express the SoC netlist in the target hardware"
- @echo " par: Place the target hardware, then route the wires"
- @echo " bitgen: Generate a programming file for the target FPGA"
- @echo " clean: Delete all superfluous files generated by Xilinx tools"
- @echo " distclean: Delete all generated files"
- @echo " uart: Synthesize the UART"
- @echo " debug: Synthesize the debug interface"
- @echo " xilDebug: Synthesize the Xilinx JTAG user interface"
- @echo " or1200: Synthesize the OR1200 processor"
-all: minsoc_top.ngc minsoc.ngd minsoc.ncd minsoc_par.ncd minsoc.bit
-soc: minsoc_top.ngc
-translate: minsoc.ngd
-map: minsoc.ncd
-par: minsoc_par.ncd
-bitgen: minsoc.bit
-
-distclean:
- rm -f _xmsgs xst *.{ngc,ncd,ngd,bit,xst,xrpt,srp,lso,log}
-clean:
- rm -f _xmsgs xst *.{xst,xrpt,srp,lso,log}
-
-minsoc_top.ngc: $(MINSOC_RTL)/*.v buildSupport/*.xst buildSupport/*.prj #uart_top.ngc adbg_top.ngc xilinx_internal_jtag.ngc or1200_top.ngc
- xst -ifn "buildSupport/minsoc_top.xst"
- rm -f minsoc_top_xst.xrpt
- rm -f minsoc_top.srp
- rm -f minsoc_top.lso
- rm -rf _xmsgs
- rm -rf xst
-uart: uart_top.ngc
-uart_top.ngc: $(UART_RTL)/*.v buildSupport/uart_top.xst buildSupport/uart_top.prj
- xst -ifn "buildSupport/uart_top.xst"
- rm -f uart_top_xst.xrpt
- rm -f uart_top.srp
- rm -f uart_top.lso
- rm -rf _xmsgs
- rm -rf xst
-debug: adbg_top.ngc
-adbg_top.ngc: $(DEBUG_RTL)/*.v buildSupport/adbg_top.xst buildSupport/adbg_top.prj
- xst -ifn "buildSupport/adbg_top.xst"
- rm -f adbg_top_xst.xrpt
- rm -f adbg_top.srp
- rm -f adbg_top.lso
- rm -rf _xmsgs
- rm -rf xst
-xilDebug: xilinx_internal_jtag.ngc
-xilinx_internal_jtag.ngc: $(XIL_DEBUG_RTL)/*.v buildSupport/xilinx_internal_jtag.xst buildSupport/xilinx_internal_jtag.prj
- xst -ifn "buildSupport/xilinx_internal_jtag.xst"
- rm -f xilinx_internal_jtag_xst.xrpt
- rm -f xilinx_internal_jtag.srp
- rm -f xilinx_internal_jtag.lso
- rm -rf _xmsgs
- rm -rf xst
-or1200: or1200_top.ngc
-or1200_top.ngc: $(OR1200_RTL)/*.v buildSupport/or1200_top.xst buildSupport/or1200_top.prj
- xst -ifn "buildSupport/or1200_top.xst"
- rm -f or1200_top_xst.xrpt
- rm -f or1200_top.srp
- rm -f or1200_top.lso
- rm -rf _xmsgs
- rm -rf xst
-minsoc.ngd: $(MINSOC)/backend/ml509.ucf minsoc_top.ngc
- ngdbuild -p xc5vlx110t-ff1136-3 -uc $(MINSOC)/backend/ml509.ucf -aul -aut minsoc_top.ngc minsoc.ngd
- rm -rf netlist.lst
- rm -rf minsoc.bld
- rm -rf minsoc*.xrpt
- rm -rf xlnx_auto_0_xdb
- rm -rf _xmsgs
-minsoc.ncd : minsoc.ngd
- map -bp -timing -cm speed -equivalent_register_removal on -global_opt speed -logic_opt on -mt 2 -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd
- rm -rf minsoc.map
- rm -rf minsoc.mrp
- rm -rf minsoc.ngm
- rm -rf minsoc.pcf
- rm -rf minsoc.psr
- rm -rf minsoc*.xml
- rm -rf minsoc_top*.xrpt
- rm -rf _xmsgs
-minsoc_par.ncd: minsoc.ncd
- par -mt 4 -ol high -w -xe n minsoc.ncd minsoc_par.ncd
- rm -rf minsoc_par.pad
- rm -rf minsoc_par.par
- rm -rf minsoc_par.ptwx
- rm -rf minsoc_par.unroutes
- rm -rf minsoc_par.xpi
- rm -rf minsoc_par_pad*
- rm -rf minsoc_top*.xrpt
- rm -rf _xmsgs
-minsoc.bit: minsoc_par.ncd
- bitgen -d -w minsoc_par.ncd minsoc.bit
- rm -rf minsoc.bgn
- rm -rf *.xwbt
- rm -rf *.xml
- rm -rf *.log
- rm -rf _xmsgs
Index: minsoc_tc_top_B3.v
===================================================================
--- minsoc_tc_top_B3.v (revision 109)
+++ minsoc_tc_top_B3.v (nonexistent)
@@ -1,1883 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Xess Traffic Cop ////
-//// ////
-//// This file is part of the OR1K test application ////
-//// http://www.opencores.org/cores/or1k/ ////
-//// ////
-//// Description ////
-//// This block connectes the RISC and peripheral controller ////
-//// cores together. ////
-//// ////
-//// To Do: ////
-//// - nothing really ////
-//// ////
-//// Author(s): ////
-//// - Damjan Lampret, lampret@opencores.org ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2002 OpenCores ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: tc_top.v,v $
-// Revision 1.4 2004/04/05 08:44:34 lampret
-// Merged branch_qmem into main tree.
-//
-// Revision 1.2 2002/03/29 20:57:30 lampret
-// Removed unused ports wb_clki and wb_rst_i
-//
-// Revision 1.1.1.1 2002/03/21 16:55:44 lampret
-// First import of the "new" XESS XSV environment.
-//
-//
-//
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-
-//
-// Width of address bus
-//
-`define TC_AW 32
-
-//
-// Width of data bus
-//
-`define TC_DW 32
-
-//
-// Width of byte select bus
-//
-`define TC_BSW 4
-
-//
-// Width of WB target inputs (coming from WB slave)
-//
-// data bus width + ack + err
-//
-`define TC_TIN_W `TC_DW+1+1
-
-//
-// Width of WB initiator inputs (coming from WB masters)
-//
-// cyc + stb + address bus width +
-// byte select bus width + we + data bus width
-//
-`define TC_IIN_W 1+1+1+`TC_AW+`TC_BSW+1+`TC_DW
-
-//
-// Traffic Cop Top
-//
-module minsoc_tc_top (
- wb_clk_i,
- wb_rst_i,
-
- i0_wb_cyc_i,
- i0_wb_stb_i,
- i0_wb_adr_i,
- i0_wb_sel_i,
- i0_wb_we_i,
- i0_wb_dat_i,
- i0_wb_dat_o,
- i0_wb_ack_o,
- i0_wb_err_o,
- i0_wb_cti_i,
- i0_wb_bte_i,
-
- i1_wb_cyc_i,
- i1_wb_stb_i,
- i1_wb_adr_i,
- i1_wb_sel_i,
- i1_wb_we_i,
- i1_wb_dat_i,
- i1_wb_dat_o,
- i1_wb_ack_o,
- i1_wb_err_o,
- i1_wb_cti_i,
- i1_wb_bte_i,
-
- i2_wb_cyc_i,
- i2_wb_stb_i,
- i2_wb_adr_i,
- i2_wb_sel_i,
- i2_wb_we_i,
- i2_wb_dat_i,
- i2_wb_dat_o,
- i2_wb_ack_o,
- i2_wb_err_o,
- i2_wb_cti_i,
- i2_wb_bte_i,
-
- i3_wb_cyc_i,
- i3_wb_stb_i,
- i3_wb_adr_i,
- i3_wb_sel_i,
- i3_wb_we_i,
- i3_wb_dat_i,
- i3_wb_dat_o,
- i3_wb_ack_o,
- i3_wb_err_o,
- i3_wb_cti_i,
- i3_wb_bte_i,
-
- i4_wb_cyc_i,
- i4_wb_stb_i,
- i4_wb_adr_i,
- i4_wb_sel_i,
- i4_wb_we_i,
- i4_wb_dat_i,
- i4_wb_dat_o,
- i4_wb_ack_o,
- i4_wb_err_o,
- i4_wb_cti_i,
- i4_wb_bte_i,
-
- i5_wb_cyc_i,
- i5_wb_stb_i,
- i5_wb_adr_i,
- i5_wb_sel_i,
- i5_wb_we_i,
- i5_wb_dat_i,
- i5_wb_dat_o,
- i5_wb_ack_o,
- i5_wb_err_o,
- i5_wb_cti_i,
- i5_wb_bte_i,
-
- i6_wb_cyc_i,
- i6_wb_stb_i,
- i6_wb_adr_i,
- i6_wb_sel_i,
- i6_wb_we_i,
- i6_wb_dat_i,
- i6_wb_dat_o,
- i6_wb_ack_o,
- i6_wb_err_o,
- i6_wb_cti_i,
- i6_wb_bte_i,
-
- i7_wb_cyc_i,
- i7_wb_stb_i,
- i7_wb_adr_i,
- i7_wb_sel_i,
- i7_wb_we_i,
- i7_wb_dat_i,
- i7_wb_dat_o,
- i7_wb_ack_o,
- i7_wb_err_o,
- i7_wb_cti_i,
- i7_wb_bte_i,
-
- t0_wb_cyc_o,
- t0_wb_stb_o,
- t0_wb_adr_o,
- t0_wb_sel_o,
- t0_wb_we_o,
- t0_wb_dat_o,
- t0_wb_dat_i,
- t0_wb_ack_i,
- t0_wb_err_i,
- t0_wb_cti_o,
- t0_wb_bte_o,
-
- t1_wb_cyc_o,
- t1_wb_stb_o,
- t1_wb_adr_o,
- t1_wb_sel_o,
- t1_wb_we_o,
- t1_wb_dat_o,
- t1_wb_dat_i,
- t1_wb_ack_i,
- t1_wb_err_i,
- t1_wb_cti_o,
- t1_wb_bte_o,
-
- t2_wb_cyc_o,
- t2_wb_stb_o,
- t2_wb_adr_o,
- t2_wb_sel_o,
- t2_wb_we_o,
- t2_wb_dat_o,
- t2_wb_dat_i,
- t2_wb_ack_i,
- t2_wb_err_i,
- t2_wb_cti_o,
- t2_wb_bte_o,
-
- t3_wb_cyc_o,
- t3_wb_stb_o,
- t3_wb_adr_o,
- t3_wb_sel_o,
- t3_wb_we_o,
- t3_wb_dat_o,
- t3_wb_dat_i,
- t3_wb_ack_i,
- t3_wb_err_i,
- t3_wb_cti_o,
- t3_wb_bte_o,
-
- t4_wb_cyc_o,
- t4_wb_stb_o,
- t4_wb_adr_o,
- t4_wb_sel_o,
- t4_wb_we_o,
- t4_wb_dat_o,
- t4_wb_dat_i,
- t4_wb_ack_i,
- t4_wb_err_i,
- t4_wb_cti_o,
- t4_wb_bte_o,
-
- t5_wb_cyc_o,
- t5_wb_stb_o,
- t5_wb_adr_o,
- t5_wb_sel_o,
- t5_wb_we_o,
- t5_wb_dat_o,
- t5_wb_dat_i,
- t5_wb_ack_i,
- t5_wb_err_i,
- t5_wb_cti_o,
- t5_wb_bte_o,
-
- t6_wb_cyc_o,
- t6_wb_stb_o,
- t6_wb_adr_o,
- t6_wb_sel_o,
- t6_wb_we_o,
- t6_wb_dat_o,
- t6_wb_dat_i,
- t6_wb_ack_i,
- t6_wb_err_i,
- t6_wb_cti_o,
- t6_wb_bte_o,
-
- t7_wb_cyc_o,
- t7_wb_stb_o,
- t7_wb_adr_o,
- t7_wb_sel_o,
- t7_wb_we_o,
- t7_wb_dat_o,
- t7_wb_dat_i,
- t7_wb_ack_i,
- t7_wb_err_i,
- t7_wb_cti_o,
- t7_wb_bte_o,
-
- t8_wb_cyc_o,
- t8_wb_stb_o,
- t8_wb_adr_o,
- t8_wb_sel_o,
- t8_wb_we_o,
- t8_wb_dat_o,
- t8_wb_dat_i,
- t8_wb_ack_i,
- t8_wb_err_i,
- t8_wb_cti_o,
- t8_wb_bte_o
-
-
-);
-
-//
-// Parameters
-//
-parameter t0_addr_w = 4;
-parameter t0_addr = 4'd8;
-parameter t1_addr_w = 4;
-parameter t1_addr = 4'd0;
-parameter t28c_addr_w = 4;
-parameter t28_addr = 4'd0;
-parameter t28i_addr_w = 4;
-parameter t2_addr = 4'd1;
-parameter t3_addr = 4'd2;
-parameter t4_addr = 4'd3;
-parameter t5_addr = 4'd4;
-parameter t6_addr = 4'd5;
-parameter t7_addr = 4'd6;
-parameter t8_addr = 4'd7;
-
-//
-// I/O Ports
-//
-input wb_clk_i;
-input wb_rst_i;
-//
-// WB slave i/f connecting initiator 0
-//
-input i0_wb_cyc_i;
-input i0_wb_stb_i;
-input [`TC_AW-1:0] i0_wb_adr_i;
-input [`TC_BSW-1:0] i0_wb_sel_i;
-input i0_wb_we_i;
-input [`TC_DW-1:0] i0_wb_dat_i;
-output [`TC_DW-1:0] i0_wb_dat_o;
-output i0_wb_ack_o;
-output i0_wb_err_o;
-input [2:0] i0_wb_cti_i;
-input [1:0] i0_wb_bte_i;
-
-//
-// WB slave i/f connecting initiator 1
-//
-input i1_wb_cyc_i;
-input i1_wb_stb_i;
-input [`TC_AW-1:0] i1_wb_adr_i;
-input [`TC_BSW-1:0] i1_wb_sel_i;
-input i1_wb_we_i;
-input [`TC_DW-1:0] i1_wb_dat_i;
-output [`TC_DW-1:0] i1_wb_dat_o;
-output i1_wb_ack_o;
-output i1_wb_err_o;
-input [2:0] i1_wb_cti_i;
-input [1:0] i1_wb_bte_i;
-
-//
-// WB slave i/f connecting initiator 2
-//
-input i2_wb_cyc_i;
-input i2_wb_stb_i;
-input [`TC_AW-1:0] i2_wb_adr_i;
-input [`TC_BSW-1:0] i2_wb_sel_i;
-input i2_wb_we_i;
-input [`TC_DW-1:0] i2_wb_dat_i;
-output [`TC_DW-1:0] i2_wb_dat_o;
-output i2_wb_ack_o;
-output i2_wb_err_o;
-input [2:0] i2_wb_cti_i;
-input [1:0] i2_wb_bte_i;
-
-//
-// WB slave i/f connecting initiator 3
-//
-input i3_wb_cyc_i;
-input i3_wb_stb_i;
-input [`TC_AW-1:0] i3_wb_adr_i;
-input [`TC_BSW-1:0] i3_wb_sel_i;
-input i3_wb_we_i;
-input [`TC_DW-1:0] i3_wb_dat_i;
-output [`TC_DW-1:0] i3_wb_dat_o;
-output i3_wb_ack_o;
-output i3_wb_err_o;
-input [2:0] i3_wb_cti_i;
-input [1:0] i3_wb_bte_i;
-
-//
-// WB slave i/f connecting initiator 4
-//
-input i4_wb_cyc_i;
-input i4_wb_stb_i;
-input [`TC_AW-1:0] i4_wb_adr_i;
-input [`TC_BSW-1:0] i4_wb_sel_i;
-input i4_wb_we_i;
-input [`TC_DW-1:0] i4_wb_dat_i;
-output [`TC_DW-1:0] i4_wb_dat_o;
-output i4_wb_ack_o;
-output i4_wb_err_o;
-input [2:0] i4_wb_cti_i;
-input [1:0] i4_wb_bte_i;
-
-//
-// WB slave i/f connecting initiator 5
-//
-input i5_wb_cyc_i;
-input i5_wb_stb_i;
-input [`TC_AW-1:0] i5_wb_adr_i;
-input [`TC_BSW-1:0] i5_wb_sel_i;
-input i5_wb_we_i;
-input [`TC_DW-1:0] i5_wb_dat_i;
-output [`TC_DW-1:0] i5_wb_dat_o;
-output i5_wb_ack_o;
-output i5_wb_err_o;
-input [2:0] i5_wb_cti_i;
-input [1:0] i5_wb_bte_i;
-
-//
-// WB slave i/f connecting initiator 6
-//
-input i6_wb_cyc_i;
-input i6_wb_stb_i;
-input [`TC_AW-1:0] i6_wb_adr_i;
-input [`TC_BSW-1:0] i6_wb_sel_i;
-input i6_wb_we_i;
-input [`TC_DW-1:0] i6_wb_dat_i;
-output [`TC_DW-1:0] i6_wb_dat_o;
-output i6_wb_ack_o;
-output i6_wb_err_o;
-input [2:0] i6_wb_cti_i;
-input [1:0] i6_wb_bte_i;
-
-//
-// WB slave i/f connecting initiator 7
-//
-input i7_wb_cyc_i;
-input i7_wb_stb_i;
-input [`TC_AW-1:0] i7_wb_adr_i;
-input [`TC_BSW-1:0] i7_wb_sel_i;
-input i7_wb_we_i;
-input [`TC_DW-1:0] i7_wb_dat_i;
-output [`TC_DW-1:0] i7_wb_dat_o;
-output i7_wb_ack_o;
-output i7_wb_err_o;
-input [2:0] i7_wb_cti_i;
-input [1:0] i7_wb_bte_i;
-
-//
-// WB master i/f connecting target 0
-//
-output t0_wb_cyc_o;
-output t0_wb_stb_o;
-output [`TC_AW-1:0] t0_wb_adr_o;
-output [`TC_BSW-1:0] t0_wb_sel_o;
-output t0_wb_we_o;
-output [`TC_DW-1:0] t0_wb_dat_o;
-input [`TC_DW-1:0] t0_wb_dat_i;
-input t0_wb_ack_i;
-input t0_wb_err_i;
-output [2:0] t0_wb_cti_o;
-output [1:0] t0_wb_bte_o;
-
-//
-// WB master i/f connecting target 1
-//
-output t1_wb_cyc_o;
-output t1_wb_stb_o;
-output [`TC_AW-1:0] t1_wb_adr_o;
-output [`TC_BSW-1:0] t1_wb_sel_o;
-output t1_wb_we_o;
-output [`TC_DW-1:0] t1_wb_dat_o;
-input [`TC_DW-1:0] t1_wb_dat_i;
-input t1_wb_ack_i;
-input t1_wb_err_i;
-output [2:0] t1_wb_cti_o;
-output [1:0] t1_wb_bte_o;
-
-//
-// WB master i/f connecting target 2
-//
-output t2_wb_cyc_o;
-output t2_wb_stb_o;
-output [`TC_AW-1:0] t2_wb_adr_o;
-output [`TC_BSW-1:0] t2_wb_sel_o;
-output t2_wb_we_o;
-output [`TC_DW-1:0] t2_wb_dat_o;
-input [`TC_DW-1:0] t2_wb_dat_i;
-input t2_wb_ack_i;
-input t2_wb_err_i;
-output [2:0] t2_wb_cti_o;
-output [1:0] t2_wb_bte_o;
-
-//
-// WB master i/f connecting target 3
-//
-output t3_wb_cyc_o;
-output t3_wb_stb_o;
-output [`TC_AW-1:0] t3_wb_adr_o;
-output [`TC_BSW-1:0] t3_wb_sel_o;
-output t3_wb_we_o;
-output [`TC_DW-1:0] t3_wb_dat_o;
-input [`TC_DW-1:0] t3_wb_dat_i;
-input t3_wb_ack_i;
-input t3_wb_err_i;
-output [2:0] t3_wb_cti_o;
-output [1:0] t3_wb_bte_o;
-
-//
-// WB master i/f connecting target 4
-//
-output t4_wb_cyc_o;
-output t4_wb_stb_o;
-output [`TC_AW-1:0] t4_wb_adr_o;
-output [`TC_BSW-1:0] t4_wb_sel_o;
-output t4_wb_we_o;
-output [`TC_DW-1:0] t4_wb_dat_o;
-input [`TC_DW-1:0] t4_wb_dat_i;
-input t4_wb_ack_i;
-input t4_wb_err_i;
-output [2:0] t4_wb_cti_o;
-output [1:0] t4_wb_bte_o;
-
-//
-// WB master i/f connecting target 5
-//
-output t5_wb_cyc_o;
-output t5_wb_stb_o;
-output [`TC_AW-1:0] t5_wb_adr_o;
-output [`TC_BSW-1:0] t5_wb_sel_o;
-output t5_wb_we_o;
-output [`TC_DW-1:0] t5_wb_dat_o;
-input [`TC_DW-1:0] t5_wb_dat_i;
-input t5_wb_ack_i;
-input t5_wb_err_i;
-output [2:0] t5_wb_cti_o;
-output [1:0] t5_wb_bte_o;
-
-//
-// WB master i/f connecting target 6
-//
-output t6_wb_cyc_o;
-output t6_wb_stb_o;
-output [`TC_AW-1:0] t6_wb_adr_o;
-output [`TC_BSW-1:0] t6_wb_sel_o;
-output t6_wb_we_o;
-output [`TC_DW-1:0] t6_wb_dat_o;
-input [`TC_DW-1:0] t6_wb_dat_i;
-input t6_wb_ack_i;
-input t6_wb_err_i;
-output [2:0] t6_wb_cti_o;
-output [1:0] t6_wb_bte_o;
-
-//
-// WB master i/f connecting target 7
-//
-output t7_wb_cyc_o;
-output t7_wb_stb_o;
-output [`TC_AW-1:0] t7_wb_adr_o;
-output [`TC_BSW-1:0] t7_wb_sel_o;
-output t7_wb_we_o;
-output [`TC_DW-1:0] t7_wb_dat_o;
-input [`TC_DW-1:0] t7_wb_dat_i;
-input t7_wb_ack_i;
-input t7_wb_err_i;
-output [2:0] t7_wb_cti_o;
-output [1:0] t7_wb_bte_o;
-
-//
-// WB master i/f connecting target 8
-//
-output t8_wb_cyc_o;
-output t8_wb_stb_o;
-output [`TC_AW-1:0] t8_wb_adr_o;
-output [`TC_BSW-1:0] t8_wb_sel_o;
-output t8_wb_we_o;
-output [`TC_DW-1:0] t8_wb_dat_o;
-input [`TC_DW-1:0] t8_wb_dat_i;
-input t8_wb_ack_i;
-input t8_wb_err_i;
-output [2:0] t8_wb_cti_o;
-output [1:0] t8_wb_bte_o;
-
-
-//
-// Internal wires & registers
-//
-
-//
-// Outputs for initiators from both mi_to_st blocks
-//
-wire [`TC_DW-1:0] xi0_wb_dat_o;
-wire xi0_wb_ack_o;
-wire xi0_wb_err_o;
-wire [`TC_DW-1:0] xi1_wb_dat_o;
-wire xi1_wb_ack_o;
-wire xi1_wb_err_o;
-wire [`TC_DW-1:0] xi2_wb_dat_o;
-wire xi2_wb_ack_o;
-wire xi2_wb_err_o;
-wire [`TC_DW-1:0] xi3_wb_dat_o;
-wire xi3_wb_ack_o;
-wire xi3_wb_err_o;
-wire [`TC_DW-1:0] xi4_wb_dat_o;
-wire xi4_wb_ack_o;
-wire xi4_wb_err_o;
-wire [`TC_DW-1:0] xi5_wb_dat_o;
-wire xi5_wb_ack_o;
-wire xi5_wb_err_o;
-wire [`TC_DW-1:0] xi6_wb_dat_o;
-wire xi6_wb_ack_o;
-wire xi6_wb_err_o;
-wire [`TC_DW-1:0] xi7_wb_dat_o;
-wire xi7_wb_ack_o;
-wire xi7_wb_err_o;
-wire [`TC_DW-1:0] yi0_wb_dat_o;
-wire yi0_wb_ack_o;
-wire yi0_wb_err_o;
-wire [`TC_DW-1:0] yi1_wb_dat_o;
-wire yi1_wb_ack_o;
-wire yi1_wb_err_o;
-wire [`TC_DW-1:0] yi2_wb_dat_o;
-wire yi2_wb_ack_o;
-wire yi2_wb_err_o;
-wire [`TC_DW-1:0] yi3_wb_dat_o;
-wire yi3_wb_ack_o;
-wire yi3_wb_err_o;
-wire [`TC_DW-1:0] yi4_wb_dat_o;
-wire yi4_wb_ack_o;
-wire yi4_wb_err_o;
-wire [`TC_DW-1:0] yi5_wb_dat_o;
-wire yi5_wb_ack_o;
-wire yi5_wb_err_o;
-wire [`TC_DW-1:0] yi6_wb_dat_o;
-wire yi6_wb_ack_o;
-wire yi6_wb_err_o;
-wire [`TC_DW-1:0] yi7_wb_dat_o;
-wire yi7_wb_ack_o;
-wire yi7_wb_err_o;
-
-//
-// Intermediate signals connecting peripheral channel's
-// mi_to_st and si_to_mt blocks.
-//
-wire z_wb_cyc_i;
-wire z_wb_stb_i;
-wire [`TC_AW-1:0] z_wb_adr_i;
-wire [`TC_BSW-1:0] z_wb_sel_i;
-wire z_wb_we_i;
-wire [`TC_DW-1:0] z_wb_dat_i;
-wire [`TC_DW-1:0] z_wb_dat_t;
-wire z_wb_ack_t;
-wire z_wb_err_t;
-wire [2:0] z_wb_cti_i;
-wire [1:0] z_wb_bte_i;
-
-//
-// Outputs for initiators are ORed from both mi_to_st blocks
-//
-assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o;
-assign i0_wb_ack_o = xi0_wb_ack_o | yi0_wb_ack_o;
-assign i0_wb_err_o = xi0_wb_err_o | yi0_wb_err_o;
-assign i1_wb_dat_o = xi1_wb_dat_o | yi1_wb_dat_o;
-assign i1_wb_ack_o = xi1_wb_ack_o | yi1_wb_ack_o;
-assign i1_wb_err_o = xi1_wb_err_o | yi1_wb_err_o;
-assign i2_wb_dat_o = xi2_wb_dat_o | yi2_wb_dat_o;
-assign i2_wb_ack_o = xi2_wb_ack_o | yi2_wb_ack_o;
-assign i2_wb_err_o = xi2_wb_err_o | yi2_wb_err_o;
-assign i3_wb_dat_o = xi3_wb_dat_o | yi3_wb_dat_o;
-assign i3_wb_ack_o = xi3_wb_ack_o | yi3_wb_ack_o;
-assign i3_wb_err_o = xi3_wb_err_o | yi3_wb_err_o;
-assign i4_wb_dat_o = xi4_wb_dat_o | yi4_wb_dat_o;
-assign i4_wb_ack_o = xi4_wb_ack_o | yi4_wb_ack_o;
-assign i4_wb_err_o = xi4_wb_err_o | yi4_wb_err_o;
-assign i5_wb_dat_o = xi5_wb_dat_o | yi5_wb_dat_o;
-assign i5_wb_ack_o = xi5_wb_ack_o | yi5_wb_ack_o;
-assign i5_wb_err_o = xi5_wb_err_o | yi5_wb_err_o;
-assign i6_wb_dat_o = xi6_wb_dat_o | yi6_wb_dat_o;
-assign i6_wb_ack_o = xi6_wb_ack_o | yi6_wb_ack_o;
-assign i6_wb_err_o = xi6_wb_err_o | yi6_wb_err_o;
-assign i7_wb_dat_o = xi7_wb_dat_o | yi7_wb_dat_o;
-assign i7_wb_ack_o = xi7_wb_ack_o | yi7_wb_ack_o;
-assign i7_wb_err_o = xi7_wb_err_o | yi7_wb_err_o;
-
-//
-// From initiators to target 0
-//
-tc_mi_to_st #(t0_addr_w, t0_addr,
- 0, t0_addr_w, t0_addr) t0_ch(
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
- .i0_wb_cyc_i(i0_wb_cyc_i),
- .i0_wb_stb_i(i0_wb_stb_i),
- .i0_wb_adr_i(i0_wb_adr_i),
- .i0_wb_sel_i(i0_wb_sel_i),
- .i0_wb_we_i(i0_wb_we_i),
- .i0_wb_dat_i(i0_wb_dat_i),
- .i0_wb_dat_o(xi0_wb_dat_o),
- .i0_wb_ack_o(xi0_wb_ack_o),
- .i0_wb_err_o(xi0_wb_err_o),
- .i0_wb_cti_i(i0_wb_cti_i),
- .i0_wb_bte_i(i0_wb_bte_i),
-
- .i1_wb_cyc_i(i1_wb_cyc_i),
- .i1_wb_stb_i(i1_wb_stb_i),
- .i1_wb_adr_i(i1_wb_adr_i),
- .i1_wb_sel_i(i1_wb_sel_i),
- .i1_wb_we_i(i1_wb_we_i),
- .i1_wb_dat_i(i1_wb_dat_i),
- .i1_wb_dat_o(xi1_wb_dat_o),
- .i1_wb_ack_o(xi1_wb_ack_o),
- .i1_wb_err_o(xi1_wb_err_o),
- .i1_wb_cti_i(i1_wb_cti_i),
- .i1_wb_bte_i(i1_wb_bte_i),
-
- .i2_wb_cyc_i(i2_wb_cyc_i),
- .i2_wb_stb_i(i2_wb_stb_i),
- .i2_wb_adr_i(i2_wb_adr_i),
- .i2_wb_sel_i(i2_wb_sel_i),
- .i2_wb_we_i(i2_wb_we_i),
- .i2_wb_dat_i(i2_wb_dat_i),
- .i2_wb_dat_o(xi2_wb_dat_o),
- .i2_wb_ack_o(xi2_wb_ack_o),
- .i2_wb_err_o(xi2_wb_err_o),
- .i2_wb_cti_i(i2_wb_cti_i),
- .i2_wb_bte_i(i2_wb_bte_i),
-
- .i3_wb_cyc_i(i3_wb_cyc_i),
- .i3_wb_stb_i(i3_wb_stb_i),
- .i3_wb_adr_i(i3_wb_adr_i),
- .i3_wb_sel_i(i3_wb_sel_i),
- .i3_wb_we_i(i3_wb_we_i),
- .i3_wb_dat_i(i3_wb_dat_i),
- .i3_wb_dat_o(xi3_wb_dat_o),
- .i3_wb_ack_o(xi3_wb_ack_o),
- .i3_wb_err_o(xi3_wb_err_o),
- .i3_wb_cti_i(i3_wb_cti_i),
- .i3_wb_bte_i(i3_wb_bte_i),
-
- .i4_wb_cyc_i(i4_wb_cyc_i),
- .i4_wb_stb_i(i4_wb_stb_i),
- .i4_wb_adr_i(i4_wb_adr_i),
- .i4_wb_sel_i(i4_wb_sel_i),
- .i4_wb_we_i(i4_wb_we_i),
- .i4_wb_dat_i(i4_wb_dat_i),
- .i4_wb_dat_o(xi4_wb_dat_o),
- .i4_wb_ack_o(xi4_wb_ack_o),
- .i4_wb_err_o(xi4_wb_err_o),
- .i4_wb_cti_i(i4_wb_cti_i),
- .i4_wb_bte_i(i4_wb_bte_i),
-
- .i5_wb_cyc_i(i5_wb_cyc_i),
- .i5_wb_stb_i(i5_wb_stb_i),
- .i5_wb_adr_i(i5_wb_adr_i),
- .i5_wb_sel_i(i5_wb_sel_i),
- .i5_wb_we_i(i5_wb_we_i),
- .i5_wb_dat_i(i5_wb_dat_i),
- .i5_wb_dat_o(xi5_wb_dat_o),
- .i5_wb_ack_o(xi5_wb_ack_o),
- .i5_wb_err_o(xi5_wb_err_o),
- .i5_wb_cti_i(i5_wb_cti_i),
- .i5_wb_bte_i(i5_wb_bte_i),
-
- .i6_wb_cyc_i(i6_wb_cyc_i),
- .i6_wb_stb_i(i6_wb_stb_i),
- .i6_wb_adr_i(i6_wb_adr_i),
- .i6_wb_sel_i(i6_wb_sel_i),
- .i6_wb_we_i(i6_wb_we_i),
- .i6_wb_dat_i(i6_wb_dat_i),
- .i6_wb_dat_o(xi6_wb_dat_o),
- .i6_wb_ack_o(xi6_wb_ack_o),
- .i6_wb_err_o(xi6_wb_err_o),
- .i6_wb_cti_i(i6_wb_cti_i),
- .i6_wb_bte_i(i6_wb_bte_i),
-
- .i7_wb_cyc_i(i7_wb_cyc_i),
- .i7_wb_stb_i(i7_wb_stb_i),
- .i7_wb_adr_i(i7_wb_adr_i),
- .i7_wb_sel_i(i7_wb_sel_i),
- .i7_wb_we_i(i7_wb_we_i),
- .i7_wb_dat_i(i7_wb_dat_i),
- .i7_wb_dat_o(xi7_wb_dat_o),
- .i7_wb_ack_o(xi7_wb_ack_o),
- .i7_wb_err_o(xi7_wb_err_o),
- .i7_wb_cti_i(i7_wb_cti_i),
- .i7_wb_bte_i(i7_wb_bte_i),
-
-
- .t0_wb_cyc_o(t0_wb_cyc_o),
- .t0_wb_stb_o(t0_wb_stb_o),
- .t0_wb_adr_o(t0_wb_adr_o),
- .t0_wb_sel_o(t0_wb_sel_o),
- .t0_wb_we_o(t0_wb_we_o),
- .t0_wb_dat_o(t0_wb_dat_o),
- .t0_wb_dat_i(t0_wb_dat_i),
- .t0_wb_ack_i(t0_wb_ack_i),
- .t0_wb_err_i(t0_wb_err_i),
- .t0_wb_cti_o(t0_wb_cti_o),
- .t0_wb_bte_o(t0_wb_bte_o)
-
-);
-
-//
-// From initiators to targets 1-8 (upper part)
-//
-tc_mi_to_st #(t1_addr_w, t1_addr,
- 1, t28c_addr_w, t28_addr) t18_ch_upper(
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
- .i0_wb_cyc_i(i0_wb_cyc_i),
- .i0_wb_stb_i(i0_wb_stb_i),
- .i0_wb_adr_i(i0_wb_adr_i),
- .i0_wb_sel_i(i0_wb_sel_i),
- .i0_wb_we_i(i0_wb_we_i),
- .i0_wb_dat_i(i0_wb_dat_i),
- .i0_wb_dat_o(yi0_wb_dat_o),
- .i0_wb_ack_o(yi0_wb_ack_o),
- .i0_wb_err_o(yi0_wb_err_o),
- .i0_wb_cti_i(i0_wb_cti_i),
- .i0_wb_bte_i(i0_wb_bte_i),
-
- .i1_wb_cyc_i(i1_wb_cyc_i),
- .i1_wb_stb_i(i1_wb_stb_i),
- .i1_wb_adr_i(i1_wb_adr_i),
- .i1_wb_sel_i(i1_wb_sel_i),
- .i1_wb_we_i(i1_wb_we_i),
- .i1_wb_dat_i(i1_wb_dat_i),
- .i1_wb_dat_o(yi1_wb_dat_o),
- .i1_wb_ack_o(yi1_wb_ack_o),
- .i1_wb_err_o(yi1_wb_err_o),
- .i1_wb_cti_i(i1_wb_cti_i),
- .i1_wb_bte_i(i1_wb_bte_i),
-
- .i2_wb_cyc_i(i2_wb_cyc_i),
- .i2_wb_stb_i(i2_wb_stb_i),
- .i2_wb_adr_i(i2_wb_adr_i),
- .i2_wb_sel_i(i2_wb_sel_i),
- .i2_wb_we_i(i2_wb_we_i),
- .i2_wb_dat_i(i2_wb_dat_i),
- .i2_wb_dat_o(yi2_wb_dat_o),
- .i2_wb_ack_o(yi2_wb_ack_o),
- .i2_wb_err_o(yi2_wb_err_o),
- .i2_wb_cti_i(i2_wb_cti_i),
- .i2_wb_bte_i(i2_wb_bte_i),
-
- .i3_wb_cyc_i(i3_wb_cyc_i),
- .i3_wb_stb_i(i3_wb_stb_i),
- .i3_wb_adr_i(i3_wb_adr_i),
- .i3_wb_sel_i(i3_wb_sel_i),
- .i3_wb_we_i(i3_wb_we_i),
- .i3_wb_dat_i(i3_wb_dat_i),
- .i3_wb_dat_o(yi3_wb_dat_o),
- .i3_wb_ack_o(yi3_wb_ack_o),
- .i3_wb_err_o(yi3_wb_err_o),
- .i3_wb_cti_i(i3_wb_cti_i),
- .i3_wb_bte_i(i3_wb_bte_i),
-
- .i4_wb_cyc_i(i4_wb_cyc_i),
- .i4_wb_stb_i(i4_wb_stb_i),
- .i4_wb_adr_i(i4_wb_adr_i),
- .i4_wb_sel_i(i4_wb_sel_i),
- .i4_wb_we_i(i4_wb_we_i),
- .i4_wb_dat_i(i4_wb_dat_i),
- .i4_wb_dat_o(yi4_wb_dat_o),
- .i4_wb_ack_o(yi4_wb_ack_o),
- .i4_wb_err_o(yi4_wb_err_o),
- .i4_wb_cti_i(i4_wb_cti_i),
- .i4_wb_bte_i(i4_wb_bte_i),
-
- .i5_wb_cyc_i(i5_wb_cyc_i),
- .i5_wb_stb_i(i5_wb_stb_i),
- .i5_wb_adr_i(i5_wb_adr_i),
- .i5_wb_sel_i(i5_wb_sel_i),
- .i5_wb_we_i(i5_wb_we_i),
- .i5_wb_dat_i(i5_wb_dat_i),
- .i5_wb_dat_o(yi5_wb_dat_o),
- .i5_wb_ack_o(yi5_wb_ack_o),
- .i5_wb_err_o(yi5_wb_err_o),
- .i5_wb_cti_i(i5_wb_cti_i),
- .i5_wb_bte_i(i5_wb_bte_i),
-
- .i6_wb_cyc_i(i6_wb_cyc_i),
- .i6_wb_stb_i(i6_wb_stb_i),
- .i6_wb_adr_i(i6_wb_adr_i),
- .i6_wb_sel_i(i6_wb_sel_i),
- .i6_wb_we_i(i6_wb_we_i),
- .i6_wb_dat_i(i6_wb_dat_i),
- .i6_wb_dat_o(yi6_wb_dat_o),
- .i6_wb_ack_o(yi6_wb_ack_o),
- .i6_wb_err_o(yi6_wb_err_o),
- .i6_wb_cti_i(i6_wb_cti_i),
- .i6_wb_bte_i(i6_wb_bte_i),
-
- .i7_wb_cyc_i(i7_wb_cyc_i),
- .i7_wb_stb_i(i7_wb_stb_i),
- .i7_wb_adr_i(i7_wb_adr_i),
- .i7_wb_sel_i(i7_wb_sel_i),
- .i7_wb_we_i(i7_wb_we_i),
- .i7_wb_dat_i(i7_wb_dat_i),
- .i7_wb_dat_o(yi7_wb_dat_o),
- .i7_wb_ack_o(yi7_wb_ack_o),
- .i7_wb_err_o(yi7_wb_err_o),
- .i7_wb_cti_i(i7_wb_cti_i),
- .i7_wb_bte_i(i7_wb_bte_i),
-
-
- .t0_wb_cyc_o(z_wb_cyc_i),
- .t0_wb_stb_o(z_wb_stb_i),
- .t0_wb_adr_o(z_wb_adr_i),
- .t0_wb_sel_o(z_wb_sel_i),
- .t0_wb_we_o(z_wb_we_i),
- .t0_wb_dat_o(z_wb_dat_i),
- .t0_wb_dat_i(z_wb_dat_t),
- .t0_wb_ack_i(z_wb_ack_t),
- .t0_wb_err_i(z_wb_err_t),
- .t0_wb_cti_o(z_wb_cti_i),
- .t0_wb_bte_o(z_wb_bte_i)
-
-);
-
-//
-// From initiators to targets 1-8 (lower part)
-//
-tc_si_to_mt #(t1_addr_w, t1_addr, t28i_addr_w, t2_addr, t3_addr,
- t4_addr, t5_addr, t6_addr, t7_addr, t8_addr) t18_ch_lower(
-
-
- .i0_wb_cyc_i(z_wb_cyc_i),
- .i0_wb_stb_i(z_wb_stb_i),
- .i0_wb_adr_i(z_wb_adr_i),
- .i0_wb_sel_i(z_wb_sel_i),
- .i0_wb_we_i(z_wb_we_i),
- .i0_wb_dat_i(z_wb_dat_i),
- .i0_wb_dat_o(z_wb_dat_t),
- .i0_wb_ack_o(z_wb_ack_t),
- .i0_wb_err_o(z_wb_err_t),
- .i0_wb_cti_i(z_wb_cti_i),
- .i0_wb_bte_i(z_wb_bte_i),
-
- .t0_wb_cyc_o(t1_wb_cyc_o),
- .t0_wb_stb_o(t1_wb_stb_o),
- .t0_wb_adr_o(t1_wb_adr_o),
- .t0_wb_sel_o(t1_wb_sel_o),
- .t0_wb_we_o(t1_wb_we_o),
- .t0_wb_dat_o(t1_wb_dat_o),
- .t0_wb_dat_i(t1_wb_dat_i),
- .t0_wb_ack_i(t1_wb_ack_i),
- .t0_wb_err_i(t1_wb_err_i),
- .t0_wb_cti_o(t1_wb_cti_o),
- .t0_wb_bte_o(t1_wb_bte_o),
-
- .t1_wb_cyc_o(t2_wb_cyc_o),
- .t1_wb_stb_o(t2_wb_stb_o),
- .t1_wb_adr_o(t2_wb_adr_o),
- .t1_wb_sel_o(t2_wb_sel_o),
- .t1_wb_we_o(t2_wb_we_o),
- .t1_wb_dat_o(t2_wb_dat_o),
- .t1_wb_dat_i(t2_wb_dat_i),
- .t1_wb_ack_i(t2_wb_ack_i),
- .t1_wb_err_i(t2_wb_err_i),
- .t1_wb_cti_o(t2_wb_cti_o),
- .t1_wb_bte_o(t2_wb_bte_o),
-
- .t2_wb_cyc_o(t3_wb_cyc_o),
- .t2_wb_stb_o(t3_wb_stb_o),
- .t2_wb_adr_o(t3_wb_adr_o),
- .t2_wb_sel_o(t3_wb_sel_o),
- .t2_wb_we_o(t3_wb_we_o),
- .t2_wb_dat_o(t3_wb_dat_o),
- .t2_wb_dat_i(t3_wb_dat_i),
- .t2_wb_ack_i(t3_wb_ack_i),
- .t2_wb_err_i(t3_wb_err_i),
- .t2_wb_cti_o(t3_wb_cti_o),
- .t2_wb_bte_o(t3_wb_bte_o),
-
- .t3_wb_cyc_o(t4_wb_cyc_o),
- .t3_wb_stb_o(t4_wb_stb_o),
- .t3_wb_adr_o(t4_wb_adr_o),
- .t3_wb_sel_o(t4_wb_sel_o),
- .t3_wb_we_o(t4_wb_we_o),
- .t3_wb_dat_o(t4_wb_dat_o),
- .t3_wb_dat_i(t4_wb_dat_i),
- .t3_wb_ack_i(t4_wb_ack_i),
- .t3_wb_err_i(t4_wb_err_i),
- .t3_wb_cti_o(t4_wb_cti_o),
- .t3_wb_bte_o(t4_wb_bte_o),
-
- .t4_wb_cyc_o(t5_wb_cyc_o),
- .t4_wb_stb_o(t5_wb_stb_o),
- .t4_wb_adr_o(t5_wb_adr_o),
- .t4_wb_sel_o(t5_wb_sel_o),
- .t4_wb_we_o(t5_wb_we_o),
- .t4_wb_dat_o(t5_wb_dat_o),
- .t4_wb_dat_i(t5_wb_dat_i),
- .t4_wb_ack_i(t5_wb_ack_i),
- .t4_wb_err_i(t5_wb_err_i),
- .t4_wb_cti_o(t5_wb_cti_o),
- .t4_wb_bte_o(t5_wb_bte_o),
-
- .t5_wb_cyc_o(t6_wb_cyc_o),
- .t5_wb_stb_o(t6_wb_stb_o),
- .t5_wb_adr_o(t6_wb_adr_o),
- .t5_wb_sel_o(t6_wb_sel_o),
- .t5_wb_we_o(t6_wb_we_o),
- .t5_wb_dat_o(t6_wb_dat_o),
- .t5_wb_dat_i(t6_wb_dat_i),
- .t5_wb_ack_i(t6_wb_ack_i),
- .t5_wb_err_i(t6_wb_err_i),
- .t5_wb_cti_o(t6_wb_cti_o),
- .t5_wb_bte_o(t6_wb_bte_o),
-
- .t6_wb_cyc_o(t7_wb_cyc_o),
- .t6_wb_stb_o(t7_wb_stb_o),
- .t6_wb_adr_o(t7_wb_adr_o),
- .t6_wb_sel_o(t7_wb_sel_o),
- .t6_wb_we_o(t7_wb_we_o),
- .t6_wb_dat_o(t7_wb_dat_o),
- .t6_wb_dat_i(t7_wb_dat_i),
- .t6_wb_ack_i(t7_wb_ack_i),
- .t6_wb_err_i(t7_wb_err_i),
- .t6_wb_cti_o(t7_wb_cti_o),
- .t6_wb_bte_o(t7_wb_bte_o),
-
- .t7_wb_cyc_o(t8_wb_cyc_o),
- .t7_wb_stb_o(t8_wb_stb_o),
- .t7_wb_adr_o(t8_wb_adr_o),
- .t7_wb_sel_o(t8_wb_sel_o),
- .t7_wb_we_o(t8_wb_we_o),
- .t7_wb_dat_o(t8_wb_dat_o),
- .t7_wb_dat_i(t8_wb_dat_i),
- .t7_wb_ack_i(t8_wb_ack_i),
- .t7_wb_err_i(t8_wb_err_i),
- .t7_wb_cti_o(t8_wb_cti_o),
- .t7_wb_bte_o(t8_wb_bte_o),
-
-
-);
-
-endmodule
-
-//
-// Multiple initiator to single target
-//
-module tc_mi_to_st (
- wb_clk_i,
- wb_rst_i,
- i0_wb_cyc_i,
- i0_wb_stb_i,
- i0_wb_adr_i,
- i0_wb_sel_i,
- i0_wb_we_i,
- i0_wb_dat_i,
- i0_wb_dat_o,
- i0_wb_ack_o,
- i0_wb_err_o,
- i0_wb_cti_i,
- i0_wb_bte_i,
-
- i1_wb_cyc_i,
- i1_wb_stb_i,
- i1_wb_adr_i,
- i1_wb_sel_i,
- i1_wb_we_i,
- i1_wb_dat_i,
- i1_wb_dat_o,
- i1_wb_ack_o,
- i1_wb_err_o,
- i1_wb_cti_i,
- i1_wb_bte_i,
-
- i2_wb_cyc_i,
- i2_wb_stb_i,
- i2_wb_adr_i,
- i2_wb_sel_i,
- i2_wb_we_i,
- i2_wb_dat_i,
- i2_wb_dat_o,
- i2_wb_ack_o,
- i2_wb_err_o,
- i2_wb_cti_i,
- i2_wb_bte_i,
-
- i3_wb_cyc_i,
- i3_wb_stb_i,
- i3_wb_adr_i,
- i3_wb_sel_i,
- i3_wb_we_i,
- i3_wb_dat_i,
- i3_wb_dat_o,
- i3_wb_ack_o,
- i3_wb_err_o,
- i3_wb_cti_i,
- i3_wb_bte_i,
-
- i4_wb_cyc_i,
- i4_wb_stb_i,
- i4_wb_adr_i,
- i4_wb_sel_i,
- i4_wb_we_i,
- i4_wb_dat_i,
- i4_wb_dat_o,
- i4_wb_ack_o,
- i4_wb_err_o,
- i4_wb_cti_i,
- i4_wb_bte_i,
-
- i5_wb_cyc_i,
- i5_wb_stb_i,
- i5_wb_adr_i,
- i5_wb_sel_i,
- i5_wb_we_i,
- i5_wb_dat_i,
- i5_wb_dat_o,
- i5_wb_ack_o,
- i5_wb_err_o,
- i5_wb_cti_i,
- i5_wb_bte_i,
-
- i6_wb_cyc_i,
- i6_wb_stb_i,
- i6_wb_adr_i,
- i6_wb_sel_i,
- i6_wb_we_i,
- i6_wb_dat_i,
- i6_wb_dat_o,
- i6_wb_ack_o,
- i6_wb_err_o,
- i6_wb_cti_i,
- i6_wb_bte_i,
-
- i7_wb_cyc_i,
- i7_wb_stb_i,
- i7_wb_adr_i,
- i7_wb_sel_i,
- i7_wb_we_i,
- i7_wb_dat_i,
- i7_wb_dat_o,
- i7_wb_ack_o,
- i7_wb_err_o,
- i7_wb_cti_i,
- i7_wb_bte_i,
-
-
- t0_wb_cyc_o,
- t0_wb_stb_o,
- t0_wb_adr_o,
- t0_wb_sel_o,
- t0_wb_we_o,
- t0_wb_dat_o,
- t0_wb_dat_i,
- t0_wb_ack_i,
- t0_wb_err_i,
- t0_wb_cti_o,
- t0_wb_bte_o
-
-);
-
-//
-// Parameters
-//
-parameter t0_addr_w = 2;
-parameter t0_addr = 2'b00;
-parameter multitarg = 1'b0;
-parameter t17_addr_w = 2;
-parameter t17_addr = 2'b00;
-
-//
-// I/O Ports
-//
-input wb_clk_i;
-input wb_rst_i;
-//
-// WB slave i/f connecting initiator 0
-//
-input i0_wb_cyc_i;
-input i0_wb_stb_i;
-input [`TC_AW-1:0] i0_wb_adr_i;
-input [`TC_BSW-1:0] i0_wb_sel_i;
-input i0_wb_we_i;
-input [`TC_DW-1:0] i0_wb_dat_i;
-output [`TC_DW-1:0] i0_wb_dat_o;
-output i0_wb_ack_o;
-output i0_wb_err_o;
-input [2:0] i0_wb_cti_i;
-input [1:0] i0_wb_bte_i;
-
-//
-// WB slave i/f connecting initiator 1
-//
-input i1_wb_cyc_i;
-input i1_wb_stb_i;
-input [`TC_AW-1:0] i1_wb_adr_i;
-input [`TC_BSW-1:0] i1_wb_sel_i;
-input i1_wb_we_i;
-input [`TC_DW-1:0] i1_wb_dat_i;
-output [`TC_DW-1:0] i1_wb_dat_o;
-output i1_wb_ack_o;
-output i1_wb_err_o;
-input [2:0] i1_wb_cti_i;
-input [1:0] i1_wb_bte_i;
-
-//
-// WB slave i/f connecting initiator 2
-//
-input i2_wb_cyc_i;
-input i2_wb_stb_i;
-input [`TC_AW-1:0] i2_wb_adr_i;
-input [`TC_BSW-1:0] i2_wb_sel_i;
-input i2_wb_we_i;
-input [`TC_DW-1:0] i2_wb_dat_i;
-output [`TC_DW-1:0] i2_wb_dat_o;
-output i2_wb_ack_o;
-output i2_wb_err_o;
-input [2:0] i2_wb_cti_i;
-input [1:0] i2_wb_bte_i;
-
-//
-// WB slave i/f connecting initiator 3
-//
-input i3_wb_cyc_i;
-input i3_wb_stb_i;
-input [`TC_AW-1:0] i3_wb_adr_i;
-input [`TC_BSW-1:0] i3_wb_sel_i;
-input i3_wb_we_i;
-input [`TC_DW-1:0] i3_wb_dat_i;
-output [`TC_DW-1:0] i3_wb_dat_o;
-output i3_wb_ack_o;
-output i3_wb_err_o;
-input [2:0] i3_wb_cti_i;
-input [1:0] i3_wb_bte_i;
-
-//
-// WB slave i/f connecting initiator 4
-//
-input i4_wb_cyc_i;
-input i4_wb_stb_i;
-input [`TC_AW-1:0] i4_wb_adr_i;
-input [`TC_BSW-1:0] i4_wb_sel_i;
-input i4_wb_we_i;
-input [`TC_DW-1:0] i4_wb_dat_i;
-output [`TC_DW-1:0] i4_wb_dat_o;
-output i4_wb_ack_o;
-output i4_wb_err_o;
-input [2:0] i4_wb_cti_i;
-input [1:0] i4_wb_bte_i;
-
-//
-// WB slave i/f connecting initiator 5
-//
-input i5_wb_cyc_i;
-input i5_wb_stb_i;
-input [`TC_AW-1:0] i5_wb_adr_i;
-input [`TC_BSW-1:0] i5_wb_sel_i;
-input i5_wb_we_i;
-input [`TC_DW-1:0] i5_wb_dat_i;
-output [`TC_DW-1:0] i5_wb_dat_o;
-output i5_wb_ack_o;
-output i5_wb_err_o;
-input [2:0] i5_wb_cti_i;
-input [1:0] i5_wb_bte_i;
-
-//
-// WB slave i/f connecting initiator 6
-//
-input i6_wb_cyc_i;
-input i6_wb_stb_i;
-input [`TC_AW-1:0] i6_wb_adr_i;
-input [`TC_BSW-1:0] i6_wb_sel_i;
-input i6_wb_we_i;
-input [`TC_DW-1:0] i6_wb_dat_i;
-output [`TC_DW-1:0] i6_wb_dat_o;
-output i6_wb_ack_o;
-output i6_wb_err_o;
-input [2:0] i6_wb_cti_i;
-input [1:0] i6_wb_bte_i;
-
-//
-// WB slave i/f connecting initiator 7
-//
-input i7_wb_cyc_i;
-input i7_wb_stb_i;
-input [`TC_AW-1:0] i7_wb_adr_i;
-input [`TC_BSW-1:0] i7_wb_sel_i;
-input i7_wb_we_i;
-input [`TC_DW-1:0] i7_wb_dat_i;
-output [`TC_DW-1:0] i7_wb_dat_o;
-output i7_wb_ack_o;
-output i7_wb_err_o;
-input [2:0] i7_wb_cti_i;
-input [1:0] i7_wb_bte_i;
-
-
-//
-// WB master i/f connecting target
-//
-output t0_wb_cyc_o;
-output t0_wb_stb_o;
-output [`TC_AW-1:0] t0_wb_adr_o;
-output [`TC_BSW-1:0] t0_wb_sel_o;
-output t0_wb_we_o;
-output [`TC_DW-1:0] t0_wb_dat_o;
-input [`TC_DW-1:0] t0_wb_dat_i;
-input t0_wb_ack_i;
-input t0_wb_err_i;
-output [2:0] t0_wb_cti_o;
-output [1:0] t0_wb_bte_o;
-
-//
-// Internal wires & registers
-//
-wire [`TC_IIN_W-1:0] i0_in, i1_in,
- i2_in, i3_in,
- i4_in, i5_in,
- i6_in, i7_in;
-wire [`TC_TIN_W-1:0] i0_out, i1_out,
- i2_out, i3_out,
- i4_out, i5_out,
- i6_out, i7_out;
-wire [`TC_IIN_W-1:0] t0_out;
-wire [`TC_TIN_W-1:0] t0_in;
-wire [7:0] req_i;
-wire [2:0] req_won;
-reg req_cont;
-reg [2:0] req_r;
-//
-// Group WB initiator 0 i/f inputs and outputs
-//
-assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i,
- i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i, i0_wb_cti_i, i0_wb_bte_i};
-assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out;
-
-//
-// Group WB initiator 1 i/f inputs and outputs
-//
-assign i1_in = {i1_wb_cyc_i, i1_wb_stb_i, i1_wb_adr_i,
- i1_wb_sel_i, i1_wb_we_i, i1_wb_dat_i, i1_wb_cti_i, i1_wb_bte_i};
-assign {i1_wb_dat_o, i1_wb_ack_o, i1_wb_err_o} = i1_out;
-
-//
-// Group WB initiator 2 i/f inputs and outputs
-//
-assign i2_in = {i2_wb_cyc_i, i2_wb_stb_i, i2_wb_adr_i,
- i2_wb_sel_i, i2_wb_we_i, i2_wb_dat_i, i2_wb_cti_i, i2_wb_bte_i};
-assign {i2_wb_dat_o, i2_wb_ack_o, i2_wb_err_o} = i2_out;
-
-//
-// Group WB initiator 3 i/f inputs and outputs
-//
-assign i3_in = {i3_wb_cyc_i, i3_wb_stb_i, i3_wb_adr_i,
- i3_wb_sel_i, i3_wb_we_i, i3_wb_dat_i, i3_wb_cti_i, i3_wb_bte_i};
-assign {i3_wb_dat_o, i3_wb_ack_o, i3_wb_err_o} = i3_out;
-
-//
-// Group WB initiator 4 i/f inputs and outputs
-//
-assign i4_in = {i4_wb_cyc_i, i4_wb_stb_i, i4_wb_adr_i,
- i4_wb_sel_i, i4_wb_we_i, i4_wb_dat_i, i4_wb_cti_i, i4_wb_bte_i};
-assign {i4_wb_dat_o, i4_wb_ack_o, i4_wb_err_o} = i4_out;
-
-//
-// Group WB initiator 5 i/f inputs and outputs
-//
-assign i5_in = {i5_wb_cyc_i, i5_wb_stb_i, i5_wb_adr_i,
- i5_wb_sel_i, i5_wb_we_i, i5_wb_dat_i, i5_wb_cti_i, i5_wb_bte_i};
-assign {i5_wb_dat_o, i5_wb_ack_o, i5_wb_err_o} = i5_out;
-
-//
-// Group WB initiator 6 i/f inputs and outputs
-//
-assign i6_in = {i6_wb_cyc_i, i6_wb_stb_i, i6_wb_adr_i,
- i6_wb_sel_i, i6_wb_we_i, i6_wb_dat_i, i6_wb_cti_i, i6_wb_bte_i};
-assign {i6_wb_dat_o, i6_wb_ack_o, i6_wb_err_o} = i6_out;
-
-//
-// Group WB initiator 7 i/f inputs and outputs
-//
-assign i7_in = {i7_wb_cyc_i, i7_wb_stb_i, i7_wb_adr_i,
- i7_wb_sel_i, i7_wb_we_i, i7_wb_dat_i, i7_wb_cti_i, i7_wb_bte_i};
-assign {i7_wb_dat_o, i7_wb_ack_o, i7_wb_err_o} = i7_out;
-
-
-//
-// Group WB target 0 i/f inputs and outputs
-//
-assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o,
- t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o, t0_wb_cti_o, t0_wb_bte_o} = t0_out;
-assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i};
-
-//
-// Assign to WB initiator i/f outputs
-//
-// Either inputs from the target are assigned or zeros.
-//
-assign i0_out = (req_won == 3'd0) ? t0_in : {`TC_TIN_W{1'b0}};
-assign i1_out = (req_won == 3'd1) ? t0_in : {`TC_TIN_W{1'b0}};
-assign i2_out = (req_won == 3'd2) ? t0_in : {`TC_TIN_W{1'b0}};
-assign i3_out = (req_won == 3'd3) ? t0_in : {`TC_TIN_W{1'b0}};
-assign i4_out = (req_won == 3'd4) ? t0_in : {`TC_TIN_W{1'b0}};
-assign i5_out = (req_won == 3'd5) ? t0_in : {`TC_TIN_W{1'b0}};
-assign i6_out = (req_won == 3'd6) ? t0_in : {`TC_TIN_W{1'b0}};
-assign i7_out = (req_won == 3'd7) ? t0_in : {`TC_TIN_W{1'b0}};
-
-//
-// Assign to WB target i/f outputs
-//
-// Assign inputs from initiator to target outputs according to
-// which initiator has won. If there is no request for the target,
-// assign zeros.
-//
-assign t0_out = (req_won == 3'd0) ? i0_in :
- (req_won == 3'd1) ? i1_in :
- (req_won == 3'd2) ? i2_in :
- (req_won == 3'd3) ? i3_in :
- (req_won == 3'd4) ? i4_in :
- (req_won == 3'd5) ? i5_in :
- (req_won == 3'd6) ? i6_in :
- (req_won == 3'd7) ? i7_in : {`TC_IIN_W{1'b0}};
-
-//
-// Determine if an initiator has address of the target.
-//
-assign req_i[0] = i0_wb_cyc_i &
- ((i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
- multitarg & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
-assign req_i[1] = i1_wb_cyc_i &
- ((i1_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
- multitarg & (i1_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
-assign req_i[2] = i2_wb_cyc_i &
- ((i2_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
- multitarg & (i2_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
-assign req_i[3] = i3_wb_cyc_i &
- ((i3_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
- multitarg & (i3_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
-assign req_i[4] = i4_wb_cyc_i &
- ((i4_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
- multitarg & (i4_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
-assign req_i[5] = i5_wb_cyc_i &
- ((i5_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
- multitarg & (i5_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
-assign req_i[6] = i6_wb_cyc_i &
- ((i6_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
- multitarg & (i6_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
-assign req_i[7] = i7_wb_cyc_i &
- ((i7_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
- multitarg & (i7_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
-
-//
-// Determine who gets current access to the target.
-//
-// If current initiator still asserts request, do nothing
-// (keep current initiator).
-// Otherwise check each initiator's request, starting from initiator 0
-// (highest priority).
-// If there is no requests from initiators, park initiator 0.
-//
-assign req_won = req_cont ? req_r :
- req_i[0] ? 3'd0 :
- req_i[1] ? 3'd1 :
- req_i[2] ? 3'd2 :
- req_i[3] ? 3'd3 :
- req_i[4] ? 3'd4 :
- req_i[5] ? 3'd5 :
- req_i[6] ? 3'd6 :
- req_i[7] ? 3'd7 : 3'd0;
-
-//
-// Check if current initiator still wants access to the target and if
-// it does, assert req_cont.
-//
-always @(req_r or req_i)
- case (req_r) // synopsys parallel_case
- 3'd0: req_cont = req_i[0];
- 3'd1: req_cont = req_i[1];
- 3'd2: req_cont = req_i[2];
- 3'd3: req_cont = req_i[3];
- 3'd4: req_cont = req_i[4];
- 3'd5: req_cont = req_i[5];
- 3'd6: req_cont = req_i[6];
- 3'd7: req_cont = req_i[7];
- endcase
-
-//
-// Register who has current access to the target.
-//
-always @(posedge wb_clk_i or posedge wb_rst_i)
- if (wb_rst_i)
- req_r <= #1 3'd0;
- else
- req_r <= #1 req_won;
-
-endmodule
-
-//
-// Single initiator to multiple targets
-//
-module tc_si_to_mt (
-
- i0_wb_cyc_i,
- i0_wb_stb_i,
- i0_wb_adr_i,
- i0_wb_sel_i,
- i0_wb_we_i,
- i0_wb_dat_i,
- i0_wb_dat_o,
- i0_wb_ack_o,
- i0_wb_err_o,
- i0_wb_cti_i,
- i0_wb_bte_i,
-
- t0_wb_cyc_o,
- t0_wb_stb_o,
- t0_wb_adr_o,
- t0_wb_sel_o,
- t0_wb_we_o,
- t0_wb_dat_o,
- t0_wb_dat_i,
- t0_wb_ack_i,
- t0_wb_err_i,
- t0_wb_cti_o,
- t0_wb_bte_o,
-
- t1_wb_cyc_o,
- t1_wb_stb_o,
- t1_wb_adr_o,
- t1_wb_sel_o,
- t1_wb_we_o,
- t1_wb_dat_o,
- t1_wb_dat_i,
- t1_wb_ack_i,
- t1_wb_err_i,
- t1_wb_cti_o,
- t1_wb_bte_o,
-
- t2_wb_cyc_o,
- t2_wb_stb_o,
- t2_wb_adr_o,
- t2_wb_sel_o,
- t2_wb_we_o,
- t2_wb_dat_o,
- t2_wb_dat_i,
- t2_wb_ack_i,
- t2_wb_err_i,
- t2_wb_cti_o,
- t2_wb_bte_o,
-
- t3_wb_cyc_o,
- t3_wb_stb_o,
- t3_wb_adr_o,
- t3_wb_sel_o,
- t3_wb_we_o,
- t3_wb_dat_o,
- t3_wb_dat_i,
- t3_wb_ack_i,
- t3_wb_err_i,
- t3_wb_cti_o,
- t3_wb_bte_o,
-
- t4_wb_cyc_o,
- t4_wb_stb_o,
- t4_wb_adr_o,
- t4_wb_sel_o,
- t4_wb_we_o,
- t4_wb_dat_o,
- t4_wb_dat_i,
- t4_wb_ack_i,
- t4_wb_err_i,
- t4_wb_cti_o,
- t4_wb_bte_o,
-
- t5_wb_cyc_o,
- t5_wb_stb_o,
- t5_wb_adr_o,
- t5_wb_sel_o,
- t5_wb_we_o,
- t5_wb_dat_o,
- t5_wb_dat_i,
- t5_wb_ack_i,
- t5_wb_err_i,
- t5_wb_cti_o,
- t5_wb_bte_o,
-
- t6_wb_cyc_o,
- t6_wb_stb_o,
- t6_wb_adr_o,
- t6_wb_sel_o,
- t6_wb_we_o,
- t6_wb_dat_o,
- t6_wb_dat_i,
- t6_wb_ack_i,
- t6_wb_err_i,
- t6_wb_cti_o,
- t6_wb_bte_o,
-
- t7_wb_cyc_o,
- t7_wb_stb_o,
- t7_wb_adr_o,
- t7_wb_sel_o,
- t7_wb_we_o,
- t7_wb_dat_o,
- t7_wb_dat_i,
- t7_wb_ack_i,
- t7_wb_err_i,
- t7_wb_cti_o,
- t7_wb_bte_o
-
-
-);
-
-//
-// Parameters
-//
-parameter t0_addr_w = 3;
-parameter t0_addr = 3'd0;
-parameter t17_addr_w = 3;
-parameter t1_addr = 3'd1;
-parameter t2_addr = 3'd2;
-parameter t3_addr = 3'd3;
-parameter t4_addr = 3'd4;
-parameter t5_addr = 3'd5;
-parameter t6_addr = 3'd6;
-parameter t7_addr = 3'd7;
-
-//
-// I/O Ports
-//
-
-//
-// WB slave i/f connecting initiator 0
-//
-input i0_wb_cyc_i;
-input i0_wb_stb_i;
-input [`TC_AW-1:0] i0_wb_adr_i;
-input [`TC_BSW-1:0] i0_wb_sel_i;
-input i0_wb_we_i;
-input [`TC_DW-1:0] i0_wb_dat_i;
-output [`TC_DW-1:0] i0_wb_dat_o;
-output i0_wb_ack_o;
-output i0_wb_err_o;
-input [2:0] i0_wb_cti_i;
-input [1:0] i0_wb_bte_i;
-//
-// WB master i/f connecting target 0
-//
-output t0_wb_cyc_o;
-output t0_wb_stb_o;
-output [`TC_AW-1:0] t0_wb_adr_o;
-output [`TC_BSW-1:0] t0_wb_sel_o;
-output t0_wb_we_o;
-output [`TC_DW-1:0] t0_wb_dat_o;
-input [`TC_DW-1:0] t0_wb_dat_i;
-input t0_wb_ack_i;
-input t0_wb_err_i;
-output [2:0] t0_wb_cti_o;
-output [1:0] t0_wb_bte_o;
-
-//
-// WB master i/f connecting target 1
-//
-output t1_wb_cyc_o;
-output t1_wb_stb_o;
-output [`TC_AW-1:0] t1_wb_adr_o;
-output [`TC_BSW-1:0] t1_wb_sel_o;
-output t1_wb_we_o;
-output [`TC_DW-1:0] t1_wb_dat_o;
-input [`TC_DW-1:0] t1_wb_dat_i;
-input t1_wb_ack_i;
-input t1_wb_err_i;
-output [2:0] t1_wb_cti_o;
-output [1:0] t1_wb_bte_o;
-
-//
-// WB master i/f connecting target 2
-//
-output t2_wb_cyc_o;
-output t2_wb_stb_o;
-output [`TC_AW-1:0] t2_wb_adr_o;
-output [`TC_BSW-1:0] t2_wb_sel_o;
-output t2_wb_we_o;
-output [`TC_DW-1:0] t2_wb_dat_o;
-input [`TC_DW-1:0] t2_wb_dat_i;
-input t2_wb_ack_i;
-input t2_wb_err_i;
-output [2:0] t2_wb_cti_o;
-output [1:0] t2_wb_bte_o;
-
-//
-// WB master i/f connecting target 3
-//
-output t3_wb_cyc_o;
-output t3_wb_stb_o;
-output [`TC_AW-1:0] t3_wb_adr_o;
-output [`TC_BSW-1:0] t3_wb_sel_o;
-output t3_wb_we_o;
-output [`TC_DW-1:0] t3_wb_dat_o;
-input [`TC_DW-1:0] t3_wb_dat_i;
-input t3_wb_ack_i;
-input t3_wb_err_i;
-output [2:0] t3_wb_cti_o;
-output [1:0] t3_wb_bte_o;
-
-//
-// WB master i/f connecting target 4
-//
-output t4_wb_cyc_o;
-output t4_wb_stb_o;
-output [`TC_AW-1:0] t4_wb_adr_o;
-output [`TC_BSW-1:0] t4_wb_sel_o;
-output t4_wb_we_o;
-output [`TC_DW-1:0] t4_wb_dat_o;
-input [`TC_DW-1:0] t4_wb_dat_i;
-input t4_wb_ack_i;
-input t4_wb_err_i;
-output [2:0] t4_wb_cti_o;
-output [1:0] t4_wb_bte_o;
-
-//
-// WB master i/f connecting target 5
-//
-output t5_wb_cyc_o;
-output t5_wb_stb_o;
-output [`TC_AW-1:0] t5_wb_adr_o;
-output [`TC_BSW-1:0] t5_wb_sel_o;
-output t5_wb_we_o;
-output [`TC_DW-1:0] t5_wb_dat_o;
-input [`TC_DW-1:0] t5_wb_dat_i;
-input t5_wb_ack_i;
-input t5_wb_err_i;
-output [2:0] t5_wb_cti_o;
-output [1:0] t5_wb_bte_o;
-
-//
-// WB master i/f connecting target 6
-//
-output t6_wb_cyc_o;
-output t6_wb_stb_o;
-output [`TC_AW-1:0] t6_wb_adr_o;
-output [`TC_BSW-1:0] t6_wb_sel_o;
-output t6_wb_we_o;
-output [`TC_DW-1:0] t6_wb_dat_o;
-input [`TC_DW-1:0] t6_wb_dat_i;
-input t6_wb_ack_i;
-input t6_wb_err_i;
-output [2:0] t6_wb_cti_o;
-output [1:0] t6_wb_bte_o;
-
-//
-// WB master i/f connecting target 7
-//
-output t7_wb_cyc_o;
-output t7_wb_stb_o;
-output [`TC_AW-1:0] t7_wb_adr_o;
-output [`TC_BSW-1:0] t7_wb_sel_o;
-output t7_wb_we_o;
-output [`TC_DW-1:0] t7_wb_dat_o;
-input [`TC_DW-1:0] t7_wb_dat_i;
-input t7_wb_ack_i;
-input t7_wb_err_i;
-output [2:0] t7_wb_cti_o;
-output [1:0] t7_wb_bte_o;
-
-
-//
-// Internal wires & registers
-//
-wire [`TC_IIN_W-1:0] i0_in;
-wire [`TC_TIN_W-1:0] i0_out;
-wire [`TC_IIN_W-1:0] t0_out, t1_out,
- t2_out, t3_out,
- t4_out, t5_out,
- t6_out, t7_out;
-wire [`TC_TIN_W-1:0] t0_in, t1_in,
- t2_in, t3_in,
- t4_in, t5_in,
- t6_in, t7_in;
-wire [7:0] req_t;
-
-//
-// Group WB initiator 0 i/f inputs and outputs
-//
-assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i,
- i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i, i0_wb_cti_i, i0_wb_bte_i};
-assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out;
-//
-// Group WB target 0 i/f inputs and outputs
-//
-assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o,
-t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o, t0_wb_cti_o, t0_wb_bte_o} = t0_out;
-assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i};
-
-//
-// Group WB target 1 i/f inputs and outputs
-//
-assign {t1_wb_cyc_o, t1_wb_stb_o, t1_wb_adr_o,
-t1_wb_sel_o, t1_wb_we_o, t1_wb_dat_o, t1_wb_cti_o, t1_wb_bte_o} = t1_out;
-assign t1_in = {t1_wb_dat_i, t1_wb_ack_i, t1_wb_err_i};
-
-//
-// Group WB target 2 i/f inputs and outputs
-//
-assign {t2_wb_cyc_o, t2_wb_stb_o, t2_wb_adr_o,
-t2_wb_sel_o, t2_wb_we_o, t2_wb_dat_o, t2_wb_cti_o, t2_wb_bte_o} = t2_out;
-assign t2_in = {t2_wb_dat_i, t2_wb_ack_i, t2_wb_err_i};
-
-//
-// Group WB target 3 i/f inputs and outputs
-//
-assign {t3_wb_cyc_o, t3_wb_stb_o, t3_wb_adr_o,
-t3_wb_sel_o, t3_wb_we_o, t3_wb_dat_o, t3_wb_cti_o, t3_wb_bte_o} = t3_out;
-assign t3_in = {t3_wb_dat_i, t3_wb_ack_i, t3_wb_err_i};
-
-//
-// Group WB target 4 i/f inputs and outputs
-//
-assign {t4_wb_cyc_o, t4_wb_stb_o, t4_wb_adr_o,
-t4_wb_sel_o, t4_wb_we_o, t4_wb_dat_o, t4_wb_cti_o, t4_wb_bte_o} = t4_out;
-assign t4_in = {t4_wb_dat_i, t4_wb_ack_i, t4_wb_err_i};
-
-//
-// Group WB target 5 i/f inputs and outputs
-//
-assign {t5_wb_cyc_o, t5_wb_stb_o, t5_wb_adr_o,
-t5_wb_sel_o, t5_wb_we_o, t5_wb_dat_o, t5_wb_cti_o, t5_wb_bte_o} = t5_out;
-assign t5_in = {t5_wb_dat_i, t5_wb_ack_i, t5_wb_err_i};
-
-//
-// Group WB target 6 i/f inputs and outputs
-//
-assign {t6_wb_cyc_o, t6_wb_stb_o, t6_wb_adr_o,
-t6_wb_sel_o, t6_wb_we_o, t6_wb_dat_o, t6_wb_cti_o, t6_wb_bte_o} = t6_out;
-assign t6_in = {t6_wb_dat_i, t6_wb_ack_i, t6_wb_err_i};
-
-//
-// Group WB target 7 i/f inputs and outputs
-//
-assign {t7_wb_cyc_o, t7_wb_stb_o, t7_wb_adr_o,
-t7_wb_sel_o, t7_wb_we_o, t7_wb_dat_o, t7_wb_cti_o, t7_wb_bte_o} = t7_out;
-assign t7_in = {t7_wb_dat_i, t7_wb_ack_i, t7_wb_err_i};
-
-//
-// Assign to WB target i/f outputs
-//
-// Either inputs from the initiator are assigned or zeros.
-//
-assign t0_out = req_t[0] ? i0_in : {`TC_IIN_W{1'b0}};
-assign t1_out = req_t[1] ? i0_in : {`TC_IIN_W{1'b0}};
-assign t2_out = req_t[2] ? i0_in : {`TC_IIN_W{1'b0}};
-assign t3_out = req_t[3] ? i0_in : {`TC_IIN_W{1'b0}};
-assign t4_out = req_t[4] ? i0_in : {`TC_IIN_W{1'b0}};
-assign t5_out = req_t[5] ? i0_in : {`TC_IIN_W{1'b0}};
-assign t6_out = req_t[6] ? i0_in : {`TC_IIN_W{1'b0}};
-assign t7_out = req_t[7] ? i0_in : {`TC_IIN_W{1'b0}};
-
-//
-// Assign to WB initiator i/f outputs
-//
-// Assign inputs from target to initiator outputs according to
-// which target is accessed. If there is no request for a target,
-// assign zeros.
-//
-assign i0_out = req_t[0] ? t0_in :
- req_t[1] ? t1_in :
- req_t[2] ? t2_in :
- req_t[3] ? t3_in :
- req_t[4] ? t4_in :
- req_t[5] ? t5_in :
- req_t[6] ? t6_in :
- req_t[7] ? t7_in : {`TC_TIN_W{1'b0}};
-
-//
-// Determine which target is being accessed.
-//
-assign req_t[0] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr);
-assign req_t[1] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t1_addr);
-assign req_t[2] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t2_addr);
-assign req_t[3] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t3_addr);
-assign req_t[4] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t4_addr);
-assign req_t[5] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t5_addr);
-assign req_t[6] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t6_addr);
-assign req_t[7] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t7_addr);
-
-endmodule
Index: eth_transf_linux/eth1_mac_recv.c
===================================================================
--- eth_transf_linux/eth1_mac_recv.c (revision 109)
+++ eth_transf_linux/eth1_mac_recv.c (nonexistent)
@@ -1,118 +0,0 @@
-#include
-
-#include
-
-//packet socket
-#include
-#include
-#include
-
-//protocol
-#include
-
-//netdevice stuff
-#include
-#include
-
-//file open stuff
-#include
-#include
-#include
-
-//arp stuff
-//#include
-
-#define MAC_ADDR_LEN 6
-typedef unsigned char MacAddress[MAC_ADDR_LEN];
-
-int main()
-{
- int socket_id, new_sock, iRet = -1;
- int addrlen, bytesread, nfound =0;
-
- int i = 0;
-
- MacAddress localMac = {0x00, 0x00, 0xC0, 0x41, 0x36, 0xD3};
-// MacAddress localMac = {0xD3, 0x36, 0x41, 0xC0, 0x00, 0x00};
-
- char buf[256];
-
- struct sockaddr_ll my_addr;
-
- struct ifreq ethreq;
-
- int if_index;
-
- //create packet socket from type sock_dgram where headers are automatically thrown out
- if ( ( socket_id = socket(PF_PACKET, SOCK_DGRAM, htons(ETH_P_ALL) ) ) < 0 )
- {
- perror("socket");
- exit(1);
- }
- else
- {
- printf("Socket has been created: socket_number %d\n", socket_id);
- }
-
-
- //GET ethreq for if "eth1"
- strncpy(ethreq.ifr_name,"eth1",IFNAMSIZ);
- ioctl(socket_id, SIOCGIFFLAGS, ðreq);
- //SET promisc mode for if ethreq
-// ethreq.ifr_flags |= IFF_PROMISC;
-// ioctl(socket_id, SIOCSIFFLAGS, ðreq);
- //request index
- ioctl(socket_id, SIOCGIFINDEX, ðreq);
-
- if_index = ethreq.ifr_ifindex;
-
- printf("This is the index of the interface: %d\n", if_index );
-
- memset(&my_addr, '0', sizeof(my_addr) );
-
- my_addr.sll_family = AF_PACKET;
- my_addr.sll_protocol = htons(ETH_P_ALL); //defaults to socket protocol
- my_addr.sll_ifindex = if_index;
-// my_addr.sll_hatype = htons(ARPHRD_ETHER);
-// my_addr.sll_pkttype = PACKET_OTHERHOST;
- my_addr.sll_halen = 6;
- memcpy( &(my_addr.sll_addr), localMac, MAC_ADDR_LEN );
-
- //request hw_addres
- ioctl(socket_id, SIOCGIFHWADDR, ðreq);
-
- printf("This is the address of my card: %d\n", my_addr.sll_addr[5] );
-
- //bind to interface goten from ioctl SIOCGIFHWADDR directive (otherwise all packets are recved)
- if ( bind( socket_id, (struct sockaddr *) &my_addr, sizeof(my_addr) ) )
- {
- perror("bind");
- exit(1);
- }
-
- struct sockaddr_ll from;
- int fromlen;
-
- fromlen = sizeof(from);
-
- for (;;)
- {
- iRet = recvfrom(socket_id, buf, 256, 0, &from, &fromlen);
- if ( iRet == -1 )
- {
- perror("recvfrom");
- exit(1);
- }
- else
- {
- printf("Received %d bytes of data.\n", iRet);
- printf("This is the received data:\n");
- for ( i = 0; i < iRet; i++)
- printf("Byte %d: %X\n", i, (int)buf[i]);
- printf("End of transmission!\n");
- }
- }
-
- return 0;
-}
-
Index: eth_transf_linux/eth1_mac_snd.c
===================================================================
--- eth_transf_linux/eth1_mac_snd.c (revision 109)
+++ eth_transf_linux/eth1_mac_snd.c (nonexistent)
@@ -1,139 +0,0 @@
-#include
-
-#include
-
-//packet socket
-#include
-#include
-#include
-
-//protocol
-#include
-
-//netdevice stuff
-#include
-#include
-
-//file open stuff
-#include
-#include
-#include
-
-//arp stuff
-//#include
-
-#define MAC_ADDR_LEN 6
-typedef unsigned char MacAddress[MAC_ADDR_LEN];
-
-int main()
-{
- int socket_id, new_sock, iRet = -1;
- int addrlen, bytesread, nfound =0;
-
- int i = 0;
-
- MacAddress localMac = {0x00, 0x00, 0xC0, 0x41, 0x36, 0xD3};
- MacAddress extMac = {0x55, 0x47, 0x34, 0x22, 0x88, 0x92};
-// MacAddress extMac = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
-
- char buf[256];
-
- struct sockaddr_ll my_addr;
-
- struct ifreq ethreq;
-
- int if_index;
-
- if ( ( socket_id = socket(PF_PACKET, SOCK_DGRAM, htons(ETH_P_ALL) ) ) < 0 )
- {
- perror("socket");
- exit(1);
- }
- else
- {
- printf("Socket has been created: socket_number %d\n", socket_id);
- }
-
-
- //GET ethreq for if "eth1"
- strncpy(ethreq.ifr_name,"eth1",IFNAMSIZ);
- ioctl(socket_id, SIOCGIFFLAGS, ðreq);
- //SET promisc mode for if ethreq
-// ethreq.ifr_flags |= IFF_PROMISC;
-// ioctl(socket_id, SIOCSIFFLAGS, ðreq);
- //request index
- ioctl(socket_id, SIOCGIFINDEX, ðreq);
- if_index = ethreq.ifr_ifindex;
-
- printf("This is the index of the interface: %d\n", if_index );
-
- memset(&my_addr, '0', sizeof(my_addr) );
-
- my_addr.sll_family = AF_PACKET;
- my_addr.sll_protocol = htons(ETH_P_ALL); //defaults to socket protocol
- my_addr.sll_ifindex = if_index;
-// my_addr.sll_hatype = htons(ARPHRD_ETHER);
-// my_addr.sll_pkttype = PACKET_OTHERHOST;
- my_addr.sll_halen = 6;
- memcpy( &(my_addr.sll_addr), localMac, MAC_ADDR_LEN );
-
- //request hw_addres
- ioctl(socket_id, SIOCGIFHWADDR, ðreq);
-
- printf("This is the address of my card: %d\n", my_addr.sll_addr[5] );
-
- if ( bind( socket_id, (struct sockaddr *) &my_addr, sizeof(my_addr) ) )
- {
- perror("bind");
- exit(1);
- }
-
- struct sockaddr_ll addr_to;
- int addr_toLen;
-
- addr_toLen = sizeof(addr_to);
-
- memset(&addr_to, '0', sizeof(addr_to) );
-
- addr_to.sll_family = AF_PACKET;
- addr_to.sll_ifindex = if_index;
- addr_to.sll_halen = 6;
- memcpy( &(addr_to.sll_addr), extMac, MAC_ADDR_LEN );
-
- for (i=0; i<256 ; i++ )
- buf[i] = 0;
-
- //first 2 bytes are gathered with length and are ignored
- buf[0] = 0xAA;
- buf[1] = 0xAA;
- //now it gets to fpga: send opcode 0xBA8
- buf[2] = 0xBA;
- buf[3] = 0x87;
- //opcode sent
- buf[4] = 0xAA;
- buf[5] = 0xAA;
- buf[6] = 0xAA;
- buf[7] = 0xAA;
- buf[8] = 0xAA;
- buf[9] = 0xAA;
- buf[10] = 0xAA;
- buf[11] = 0xAA;
-
-// for (;;)
-// {
- iRet = sendto(socket_id, buf, 46, 0, (struct sockaddr *) &addr_to, addr_toLen);
- if ( iRet == -1 )
- {
- perror("sendto");
- exit(1);
- }
- else
- {
-// printf("%s\n", buf);
- printf("Data sent!\nExiting...\n");
- }
-// }
-
- return 0;
-}
-